src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 #include "nv50/g80_texture.xml.h"
  42
  43 static boolean
  44 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  45                                 enum pipe_format format,
  46                                 enum pipe_texture_target target,
  47                                 unsigned sample_count,
  48                                 unsigned bindings)
  49 {
  50    const struct util_format_description *desc = util_format_description(format);
  51
  52    if (sample_count > 8)
  53       return false;
  54    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  55       return false;
  56
  57    /* Short-circuit the rest of the logic -- this is used by the state tracker
  58     * to determine valid MS levels in a no-attachments scenario.
  59     */
  60    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  61       return true;
  62
  63    if (!util_format_is_supported(format, bindings))
  64       return false;
  65
  66    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  67       if (util_format_get_blocksizebits(format) == 3 * 32)
  68          return false;
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  79     */
  80    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  81         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  82        /* The claim is that this should work on GM107 but it doesn't. Need to
  83         * test further and figure out if it's a nouveau issue or a HW one.
  84        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  85         */
  86        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  87       return false;
  88
  89    /* shared is always supported */
  90    bindings &= ~(PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
  94        nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
  95       /* MS images are currently unsupported on Maxwell because they have to
  96        * be handled explicitly. */
  97       return false;
  98    }
  99
 100    return (( nvc0_format_table[format].usage |
 101             nvc0_vertex_format[format].usage) & bindings) == bindings;
 102 }
 103
 104 static int
 105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 106 {
 107    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 108    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 109
 110    switch (param) {
 111    /* non-boolean caps */
 112    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 113    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 114       return 15;
 115    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 116       return 12;
 117    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 118       return 2048;
 119    case PIPE_CAP_MIN_TEXEL_OFFSET:
 120       return -8;
 121    case PIPE_CAP_MAX_TEXEL_OFFSET:
 122       return 7;
 123    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 124       return -32;
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126       return 31;
 127    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 128       return 128 * 1024 * 1024;
 129    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 130       return 430;
 131    case PIPE_CAP_MAX_RENDER_TARGETS:
 132       return 8;
 133    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 134       return 1;
 135    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 136       return 4;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 138    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 139       return 128;
 140    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 141    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 142       return 1024;
 143    case PIPE_CAP_MAX_VERTEX_STREAMS:
 144       return 4;
 145    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 146       return 2048;
 147    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 148       return 256;
 149    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 150       return 16; /* 256 for binding as RT, but that's not possible in GL */
 151    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 152       return 16;
 153    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 154       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 155    case PIPE_CAP_MAX_VIEWPORTS:
 156       return NVC0_MAX_VIEWPORTS;
 157    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 158       return 4;
 159    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 160       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 161    case PIPE_CAP_ENDIANNESS:
 162       return PIPE_ENDIAN_LITTLE;
 163    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 164       return 30;
 165    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 166       return NVC0_MAX_WINDOW_RECTANGLES;
 167
 168    /* supported caps */
 169    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 170    case PIPE_CAP_TEXTURE_SWIZZLE:
 171    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 172    case PIPE_CAP_NPOT_TEXTURES:
 173    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 174    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 175    case PIPE_CAP_ANISOTROPIC_FILTER:
 176    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 177    case PIPE_CAP_CUBE_MAP_ARRAY:
 178    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 179    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180    case PIPE_CAP_TWO_SIDED_STENCIL:
 181    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 182    case PIPE_CAP_POINT_SPRITE:
 183    case PIPE_CAP_TGSI_TEXCOORD:
 184    case PIPE_CAP_SM3:
 185    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 186    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 187    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 188    case PIPE_CAP_QUERY_TIMESTAMP:
 189    case PIPE_CAP_QUERY_TIME_ELAPSED:
 190    case PIPE_CAP_OCCLUSION_QUERY:
 191    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 192    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 193    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 194    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 195    case PIPE_CAP_INDEP_BLEND_ENABLE:
 196    case PIPE_CAP_INDEP_BLEND_FUNC:
 197    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 198    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 199    case PIPE_CAP_PRIMITIVE_RESTART:
 200    case PIPE_CAP_TGSI_INSTANCEID:
 201    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 202    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 203    case PIPE_CAP_CONDITIONAL_RENDER:
 204    case PIPE_CAP_TEXTURE_BARRIER:
 205    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 206    case PIPE_CAP_START_INSTANCE:
 207    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 208    case PIPE_CAP_DRAW_INDIRECT:
 209    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 210    case PIPE_CAP_USER_INDEX_BUFFERS:
 211    case PIPE_CAP_USER_VERTEX_BUFFERS:
 212    case PIPE_CAP_TEXTURE_QUERY_LOD:
 213    case PIPE_CAP_SAMPLE_SHADING:
 214    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 215    case PIPE_CAP_TEXTURE_GATHER_SM5:
 216    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 217    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 218    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 219    case PIPE_CAP_CLIP_HALFZ:
 220    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 221    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 222    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 223    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 224    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 225    case PIPE_CAP_TGSI_TXQS:
 226    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 227    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 228    case PIPE_CAP_SHAREABLE_SHADERS:
 229    case PIPE_CAP_CLEAR_TEXTURE:
 230    case PIPE_CAP_DRAW_PARAMETERS:
 231    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 232    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 233    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 234    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 235    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 236    case PIPE_CAP_INVALIDATE_BUFFER:
 237    case PIPE_CAP_STRING_MARKER:
 238    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 239    case PIPE_CAP_CULL_DISTANCE:
 240    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 241    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 242    case PIPE_CAP_TGSI_VOTE:
 243    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 244    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 245       return 1;
 246    case PIPE_CAP_COMPUTE:
 247       return (class_3d < GP100_3D_CLASS);
 248    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 249       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 250    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 251       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 252    case PIPE_CAP_TGSI_FS_FBFETCH:
 253       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 254
 255    /* unsupported caps */
 256    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 257    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 258    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 259    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 260    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 261    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 262    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 263    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 264    case PIPE_CAP_FAKE_SW_MSAA:
 265    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 266    case PIPE_CAP_VERTEXID_NOBASE:
 267    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 268    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 269    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 270    case PIPE_CAP_GENERATE_MIPMAP:
 271    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 272    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 273    case PIPE_CAP_QUERY_MEMORY_INFO:
 274    case PIPE_CAP_PCI_GROUP:
 275    case PIPE_CAP_PCI_BUS:
 276    case PIPE_CAP_PCI_DEVICE:
 277    case PIPE_CAP_PCI_FUNCTION:
 278    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 279    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 280    case PIPE_CAP_NATIVE_FENCE_FD:
 281    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 282       return 0;
 283
 284    case PIPE_CAP_VENDOR_ID:
 285       return 0x10de;
 286    case PIPE_CAP_DEVICE_ID: {
 287       uint64_t device_id;
 288       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 289          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 290          return -1;
 291       }
 292       return device_id;
 293    }
 294    case PIPE_CAP_ACCELERATED:
 295       return 1;
 296    case PIPE_CAP_VIDEO_MEMORY:
 297       return dev->vram_size >> 20;
 298    case PIPE_CAP_UMA:
 299       return 0;
 300    }
 301
 302    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 303    return 0;
 304 }
 305
 306 static int
 307 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 308                              enum pipe_shader_cap param)
 309 {
 310    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 311
 312    switch (shader) {
 313    case PIPE_SHADER_VERTEX:
 314    case PIPE_SHADER_GEOMETRY:
 315    case PIPE_SHADER_FRAGMENT:
 316    case PIPE_SHADER_COMPUTE:
 317    case PIPE_SHADER_TESS_CTRL:
 318    case PIPE_SHADER_TESS_EVAL:
 319       break;
 320    default:
 321       return 0;
 322    }
 323
 324    switch (param) {
 325    case PIPE_SHADER_CAP_PREFERRED_IR:
 326       return PIPE_SHADER_IR_TGSI;
 327    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 328       return 1 << PIPE_SHADER_IR_TGSI;
 329    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 330    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 331    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 332    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 333       return 16384;
 334    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 335       return 16;
 336    case PIPE_SHADER_CAP_MAX_INPUTS:
 337       if (shader == PIPE_SHADER_VERTEX)
 338          return 32;
 339       /* NOTE: These only count our slots for GENERIC varyings.
 340        * The address space may be larger, but the actual hard limit seems to be
 341        * less than what the address space layout permits, so don't add TEXCOORD,
 342        * COLOR, etc. here.
 343        */
 344       if (shader == PIPE_SHADER_FRAGMENT)
 345          return 0x1f0 / 16;
 346       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 347        * and excludes 0x60 per-patch inputs.
 348        */
 349       return 0x200 / 16;
 350    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 351       return 32;
 352    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 353       return 65536;
 354    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 355       return NVC0_MAX_PIPE_CONSTBUFS;
 356    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 357       return shader != PIPE_SHADER_FRAGMENT;
 358    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 359    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 360    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 361       return 1;
 362    case PIPE_SHADER_CAP_MAX_PREDS:
 363       return 0;
 364    case PIPE_SHADER_CAP_MAX_TEMPS:
 365       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 366    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 367       return 1;
 368    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 369       return 1;
 370    case PIPE_SHADER_CAP_SUBROUTINES:
 371       return 1;
 372    case PIPE_SHADER_CAP_INTEGERS:
 373       return 1;
 374    case PIPE_SHADER_CAP_DOUBLES:
 375       return 1;
 376    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 377       return 1;
 378    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 379       return 1;
 380    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 381    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 382    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 383       return 0;
 384    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 385       return NVC0_MAX_BUFFERS;
 386    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 387       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 388    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 389       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 390    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 391       return 32;
 392    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 393       if (class_3d >= NVE4_3D_CLASS)
 394          return NVC0_MAX_IMAGES;
 395       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 396          return NVC0_MAX_IMAGES;
 397       return 0;
 398    default:
 399       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 400       return 0;
 401    }
 402 }
 403
 404 static float
 405 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 406 {
 407    switch (param) {
 408    case PIPE_CAPF_MAX_LINE_WIDTH:
 409    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 410       return 10.0f;
 411    case PIPE_CAPF_MAX_POINT_WIDTH:
 412       return 63.0f;
 413    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 414       return 63.375f;
 415    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 416       return 16.0f;
 417    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 418       return 15.0f;
 419    case PIPE_CAPF_GUARD_BAND_LEFT:
 420    case PIPE_CAPF_GUARD_BAND_TOP:
 421       return 0.0f;
 422    case PIPE_CAPF_GUARD_BAND_RIGHT:
 423    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 424       return 0.0f; /* that or infinity */
 425    }
 426
 427    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 428    return 0.0f;
 429 }
 430
 431 static int
 432 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 433                               enum pipe_shader_ir ir_type,
 434                               enum pipe_compute_cap param, void *data)
 435 {
 436    struct nvc0_screen *screen = nvc0_screen(pscreen);
 437    const uint16_t obj_class = screen->compute->oclass;
 438
 439 #define RET(x) do {                  \
 440    if (data)                         \
 441       memcpy(data, x, sizeof(x));    \
 442    return sizeof(x);                 \
 443 } while (0)
 444
 445    switch (param) {
 446    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 447       RET((uint64_t []) { 3 });
 448    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 449       if (obj_class >= NVE4_COMPUTE_CLASS) {
 450          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 451       } else {
 452          RET(((uint64_t []) { 65535, 65535, 65535 }));
 453       }
 454    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 455       RET(((uint64_t []) { 1024, 1024, 64 }));
 456    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 457       RET((uint64_t []) { 1024 });
 458    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 459       if (obj_class >= NVE4_COMPUTE_CLASS) {
 460          RET((uint64_t []) { 1024 });
 461       } else {
 462          RET((uint64_t []) { 512 });
 463       }
 464    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 465       RET((uint64_t []) { 1ULL << 40 });
 466    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 467       switch (obj_class) {
 468       case GM200_COMPUTE_CLASS:
 469          RET((uint64_t []) { 96 << 10 });
 470          break;
 471       case GM107_COMPUTE_CLASS:
 472          RET((uint64_t []) { 64 << 10 });
 473          break;
 474       default:
 475          RET((uint64_t []) { 48 << 10 });
 476          break;
 477       }
 478    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 479       RET((uint64_t []) { 512 << 10 });
 480    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 481       RET((uint64_t []) { 4096 });
 482    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 483       RET((uint32_t []) { 32 });
 484    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 485       RET((uint64_t []) { 1ULL << 40 });
 486    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 487       RET((uint32_t []) { 0 });
 488    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 489       RET((uint32_t []) { screen->mp_count_compute });
 490    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 491       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 492    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 493       RET((uint32_t []) { 64 });
 494    default:
 495       return 0;
 496    }
 497
 498 #undef RET
 499 }
 500
 501 static void
 502 nvc0_screen_destroy(struct pipe_screen *pscreen)
 503 {
 504    struct nvc0_screen *screen = nvc0_screen(pscreen);
 505
 506    if (!nouveau_drm_screen_unref(&screen->base))
 507       return;
 508
 509    if (screen->base.fence.current) {
 510       struct nouveau_fence *current = NULL;
 511
 512       /* nouveau_fence_wait will create a new current fence, so wait on the
 513        * _current_ one, and remove both.
 514        */
 515       nouveau_fence_ref(screen->base.fence.current, &current);
 516       nouveau_fence_wait(current, NULL);
 517       nouveau_fence_ref(NULL, &current);
 518       nouveau_fence_ref(NULL, &screen->base.fence.current);
 519    }
 520    if (screen->base.pushbuf)
 521       screen->base.pushbuf->user_priv = NULL;
 522
 523    if (screen->blitter)
 524       nvc0_blitter_destroy(screen);
 525    if (screen->pm.prog) {
 526       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 527       nvc0_program_destroy(NULL, screen->pm.prog);
 528       FREE(screen->pm.prog);
 529    }
 530
 531    nouveau_bo_ref(NULL, &screen->text);
 532    nouveau_bo_ref(NULL, &screen->uniform_bo);
 533    nouveau_bo_ref(NULL, &screen->tls);
 534    nouveau_bo_ref(NULL, &screen->txc);
 535    nouveau_bo_ref(NULL, &screen->fence.bo);
 536    nouveau_bo_ref(NULL, &screen->poly_cache);
 537
 538    nouveau_heap_destroy(&screen->lib_code);
 539    nouveau_heap_destroy(&screen->text_heap);
 540
 541    FREE(screen->default_tsc);
 542    FREE(screen->tic.entries);
 543
 544    nouveau_object_del(&screen->eng3d);
 545    nouveau_object_del(&screen->eng2d);
 546    nouveau_object_del(&screen->m2mf);
 547    nouveau_object_del(&screen->compute);
 548    nouveau_object_del(&screen->nvsw);
 549
 550    nouveau_screen_fini(&screen->base);
 551
 552    FREE(screen);
 553 }
 554
 555 static int
 556 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 557                      unsigned size, const uint32_t *data)
 558 {
 559    struct nouveau_pushbuf *push = screen->base.pushbuf;
 560
 561    size /= 4;
 562
 563    assert((pos + size) <= 0x800);
 564
 565    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 566    PUSH_DATA (push, (m - 0x3800) / 8);
 567    PUSH_DATA (push, pos);
 568    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 569    PUSH_DATA (push, pos);
 570    PUSH_DATAp(push, data, size);
 571
 572    return pos + size;
 573 }
 574
 575 static void
 576 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 577 {
 578    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 579    PUSH_DATA (push, 0xff);
 580    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 581    PUSH_DATA (push, 0xff);
 582    PUSH_DATA (push, 0xff);
 583    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 584    PUSH_DATA (push, 0xff);
 585    PUSH_DATA (push, 0xff);
 586    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 587    PUSH_DATA (push, 0x3f);
 588
 589    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 590    PUSH_DATA (push, (3 << 16) | 3);
 591    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 592    PUSH_DATA (push, (2 << 16) | 2);
 593
 594    if (obj_class < GM107_3D_CLASS) {
 595       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 596       PUSH_DATA (push, 0);
 597    }
 598    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 599    PUSH_DATA (push, 0x10);
 600    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 601    PUSH_DATA (push, 0x10);
 602    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 603    PUSH_DATA (push, 0x10);
 604    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 605    PUSH_DATA (push, 0x10);
 606    PUSH_DATA (push, 0x10);
 607    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 608    PUSH_DATA (push, 0x10);
 609    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 610    PUSH_DATA (push, 0xe);
 611
 612    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 613    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 614    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 615    PUSH_DATA (push, 0);
 616    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 617    PUSH_DATA (push, 3);
 618
 619    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 620    PUSH_DATA (push, 0x3fffff);
 621    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 622    PUSH_DATA (push, 1);
 623    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 624    PUSH_DATA (push, 1);
 625
 626    if (obj_class < GM107_3D_CLASS) {
 627       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 628       PUSH_DATA (push, 3);
 629
 630       if (obj_class >= NVE4_3D_CLASS) {
 631          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 632          PUSH_DATA (push, 1);
 633       }
 634    }
 635
 636    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 637     * are supposed to do */
 638 }
 639
 640 static void
 641 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 642 {
 643    struct nvc0_screen *screen = nvc0_screen(pscreen);
 644    struct nouveau_pushbuf *push = screen->base.pushbuf;
 645
 646    /* we need to do it after possible flush in MARK_RING */
 647    *sequence = ++screen->base.fence.sequence;
 648
 649    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 650    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 651    PUSH_DATAh(push, screen->fence.bo->offset);
 652    PUSH_DATA (push, screen->fence.bo->offset);
 653    PUSH_DATA (push, *sequence);
 654    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 655               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 656 }
 657
 658 static u32
 659 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 660 {
 661    struct nvc0_screen *screen = nvc0_screen(pscreen);
 662    return screen->fence.map[0];
 663 }
 664
 665 static int
 666 nvc0_screen_init_compute(struct nvc0_screen *screen)
 667 {
 668    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 669
 670    switch (screen->base.device->chipset & ~0xf) {
 671    case 0xc0:
 672    case 0xd0:
 673       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 674    case 0xe0:
 675    case 0xf0:
 676    case 0x100:
 677    case 0x110:
 678    case 0x120:
 679       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 680    case 0x130:
 681       return 0;
 682    default:
 683       return -1;
 684    }
 685 }
 686
 687 static int
 688 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 689                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 690 {
 691    struct nouveau_bo *bo = NULL;
 692    int ret;
 693    uint64_t size = (lpos + lneg) * 32 + cstack;
 694
 695    if (size >= (1 << 20)) {
 696       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 697       return -1;
 698    }
 699
 700    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 701    size  = align(size, 0x8000);
 702    size *= screen->mp_count;
 703
 704    size = align(size, 1 << 17);
 705
 706    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 707                         NULL, &bo);
 708    if (ret)
 709       return ret;
 710    nouveau_bo_ref(NULL, &screen->tls);
 711    screen->tls = bo;
 712    return 0;
 713 }
 714
 715 int
 716 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 717 {
 718    struct nouveau_pushbuf *push = screen->base.pushbuf;
 719    struct nouveau_bo *bo;
 720    int ret;
 721
 722    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 723                         1 << 17, size, NULL, &bo);
 724    if (ret)
 725       return ret;
 726
 727    nouveau_bo_ref(NULL, &screen->text);
 728    screen->text = bo;
 729
 730    nouveau_heap_destroy(&screen->lib_code);
 731    nouveau_heap_destroy(&screen->text_heap);
 732
 733    /* XXX: getting a page fault at the end of the code buffer every few
 734     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 735     */
 736    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 737
 738    /* update the code segment setup */
 739    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 740    PUSH_DATAh(push, screen->text->offset);
 741    PUSH_DATA (push, screen->text->offset);
 742    if (screen->compute) {
 743       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 744       PUSH_DATAh(push, screen->text->offset);
 745       PUSH_DATA (push, screen->text->offset);
 746    }
 747
 748    return 0;
 749 }
 750
 751 #define FAIL_SCREEN_INIT(str, err)                    \
 752    do {                                               \
 753       NOUVEAU_ERR(str, err);                          \
 754       goto fail;                                      \
 755    } while(0)
 756
 757 struct nouveau_screen *
 758 nvc0_screen_create(struct nouveau_device *dev)
 759 {
 760    struct nvc0_screen *screen;
 761    struct pipe_screen *pscreen;
 762    struct nouveau_object *chan;
 763    struct nouveau_pushbuf *push;
 764    uint64_t value;
 765    uint32_t obj_class;
 766    uint32_t flags;
 767    int ret;
 768    unsigned i;
 769
 770    switch (dev->chipset & ~0xf) {
 771    case 0xc0:
 772    case 0xd0:
 773    case 0xe0:
 774    case 0xf0:
 775    case 0x100:
 776    case 0x110:
 777    case 0x120:
 778    case 0x130:
 779       break;
 780    default:
 781       return NULL;
 782    }
 783
 784    screen = CALLOC_STRUCT(nvc0_screen);
 785    if (!screen)
 786       return NULL;
 787    pscreen = &screen->base.base;
 788    pscreen->destroy = nvc0_screen_destroy;
 789
 790    ret = nouveau_screen_init(&screen->base, dev);
 791    if (ret)
 792       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 793    chan = screen->base.channel;
 794    push = screen->base.pushbuf;
 795    push->user_priv = screen;
 796    push->rsvd_kick = 5;
 797
 798    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 799       PIPE_BIND_SHADER_BUFFER |
 800       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 801       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 802    screen->base.sysmem_bindings |=
 803       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 804
 805    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 806       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 807       screen->base.vidmem_bindings = 0;
 808    }
 809
 810    pscreen->context_create = nvc0_create;
 811    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 812    pscreen->get_param = nvc0_screen_get_param;
 813    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 814    pscreen->get_paramf = nvc0_screen_get_paramf;
 815    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 816    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 817
 818    nvc0_screen_init_resource_functions(pscreen);
 819
 820    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 821    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 822
 823    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 824    if (screen->base.drm->version >= 0x01000202)
 825       flags |= NOUVEAU_BO_COHERENT;
 826
 827    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 828    if (ret)
 829       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 830    nouveau_bo_map(screen->fence.bo, 0, NULL);
 831    screen->fence.map = screen->fence.bo->map;
 832    screen->base.fence.emit = nvc0_screen_fence_emit;
 833    screen->base.fence.update = nvc0_screen_fence_update;
 834
 835
 836    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 837                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 838    if (ret)
 839       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 840
 841    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 842    PUSH_DATA (push, screen->nvsw->handle);
 843
 844    switch (dev->chipset & ~0xf) {
 845    case 0x130:
 846    case 0x120:
 847    case 0x110:
 848    case 0x100:
 849    case 0xf0:
 850       obj_class = NVF0_P2MF_CLASS;
 851       break;
 852    case 0xe0:
 853       obj_class = NVE4_P2MF_CLASS;
 854       break;
 855    default:
 856       obj_class = NVC0_M2MF_CLASS;
 857       break;
 858    }
 859    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 860                             &screen->m2mf);
 861    if (ret)
 862       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 863
 864    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 865    PUSH_DATA (push, screen->m2mf->oclass);
 866    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 867       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 868       PUSH_DATA (push, 0xa0b5);
 869    }
 870
 871    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 872                             &screen->eng2d);
 873    if (ret)
 874       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 875
 876    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 877    PUSH_DATA (push, screen->eng2d->oclass);
 878    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 879    PUSH_DATA (push, 0);
 880    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 881    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 882    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 883    PUSH_DATA (push, 0);
 884    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 885    PUSH_DATA (push, 0);
 886    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 887    PUSH_DATA (push, 0x3f);
 888    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 889    PUSH_DATA (push, 1);
 890    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 891    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 892
 893    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 894    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 895    PUSH_DATA (push, screen->fence.bo->offset + 16);
 896
 897    switch (dev->chipset & ~0xf) {
 898    case 0x130:
 899       obj_class = GP100_3D_CLASS;
 900       break;
 901    case 0x120:
 902       obj_class = GM200_3D_CLASS;
 903       break;
 904    case 0x110:
 905       obj_class = GM107_3D_CLASS;
 906       break;
 907    case 0x100:
 908    case 0xf0:
 909       obj_class = NVF0_3D_CLASS;
 910       break;
 911    case 0xe0:
 912       switch (dev->chipset) {
 913       case 0xea:
 914          obj_class = NVEA_3D_CLASS;
 915          break;
 916       default:
 917          obj_class = NVE4_3D_CLASS;
 918          break;
 919       }
 920       break;
 921    case 0xd0:
 922       obj_class = NVC8_3D_CLASS;
 923       break;
 924    case 0xc0:
 925    default:
 926       switch (dev->chipset) {
 927       case 0xc8:
 928          obj_class = NVC8_3D_CLASS;
 929          break;
 930       case 0xc1:
 931          obj_class = NVC1_3D_CLASS;
 932          break;
 933       default:
 934          obj_class = NVC0_3D_CLASS;
 935          break;
 936       }
 937       break;
 938    }
 939    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 940                             &screen->eng3d);
 941    if (ret)
 942       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 943    screen->base.class_3d = obj_class;
 944
 945    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 946    PUSH_DATA (push, screen->eng3d->oclass);
 947
 948    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 949    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 950
 951    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 952       /* kill shaders after about 1 second (at 100 MHz) */
 953       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 954       PUSH_DATA (push, 0x17);
 955    }
 956
 957    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 958                     screen->base.drm->version >= 0x01000101);
 959    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 960    for (i = 0; i < 8; ++i)
 961       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 962
 963    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 964    PUSH_DATA (push, 1);
 965
 966    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 967    PUSH_DATA (push, 0);
 968    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 969    PUSH_DATA (push, 0);
 970    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 971    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 972    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 973    PUSH_DATA (push, 0);
 974    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 975    PUSH_DATA (push, 1);
 976    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 977    PUSH_DATA (push, 1);
 978    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 979    PUSH_DATA (push, 1);
 980    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 981    PUSH_DATA (push, 0);
 982    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 983    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 984    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 985       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 986    } else {
 987       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 988       PUSH_DATA (push, 15);
 989    }
 990    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 991    PUSH_DATA (push, 8); /* 128 */
 992    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 993    PUSH_DATA (push, 1);
 994    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 995       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 996       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 997    }
 998
 999    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1000
1001    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1002    if (ret)
1003       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1004
1005    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1006                         &screen->uniform_bo);
1007    if (ret)
1008       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1009
1010    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1011
1012    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1013    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1014    PUSH_DATA (push, 256);
1015    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1016    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1017    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1018    PUSH_DATA (push, 0);
1019    PUSH_DATAf(push, 0.0f);
1020    PUSH_DATAf(push, 0.0f);
1021    PUSH_DATAf(push, 0.0f);
1022    PUSH_DATAf(push, 0.0f);
1023    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1024    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1025    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1026
1027    if (screen->base.drm->version >= 0x01000101) {
1028       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1029       if (ret)
1030          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1031    } else {
1032       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1033          value = (8 << 8) | 4;
1034       else
1035          value = (16 << 8) | 4;
1036    }
1037    screen->gpc_count = value & 0x000000ff;
1038    screen->mp_count = value >> 8;
1039    screen->mp_count_compute = screen->mp_count;
1040
1041    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1042    if (ret)
1043       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1044
1045    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1046    PUSH_DATAh(push, screen->tls->offset);
1047    PUSH_DATA (push, screen->tls->offset);
1048    PUSH_DATA (push, screen->tls->size >> 32);
1049    PUSH_DATA (push, screen->tls->size);
1050    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1051    PUSH_DATA (push, 0);
1052    /* Reduce likelihood of collision with real buffers by placing the hole at
1053     * the top of the 4G area. This will have to be dealt with for real
1054     * eventually by blocking off that area from the VM.
1055     */
1056    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1057    PUSH_DATA (push, 0xff << 24);
1058
1059    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1060       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1061                            &screen->poly_cache);
1062       if (ret)
1063          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1064
1065       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1066       PUSH_DATAh(push, screen->poly_cache->offset);
1067       PUSH_DATA (push, screen->poly_cache->offset);
1068       PUSH_DATA (push, 3);
1069    }
1070
1071    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1072                         &screen->txc);
1073    if (ret)
1074       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1075
1076    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1077    PUSH_DATAh(push, screen->txc->offset);
1078    PUSH_DATA (push, screen->txc->offset);
1079    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1080    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1081       screen->tic.maxwell = true;
1082       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1083          screen->tic.maxwell =
1084             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1085          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1086       }
1087    }
1088
1089    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1090    PUSH_DATAh(push, screen->txc->offset + 65536);
1091    PUSH_DATA (push, screen->txc->offset + 65536);
1092    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1093
1094    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1095    PUSH_DATA (push, 0);
1096    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1097    PUSH_DATA (push, 0);
1098    PUSH_DATA (push, 0);
1099    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1100    PUSH_DATA (push, 0x3f);
1101
1102    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1103    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1104    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1105    for (i = 0; i < 8 * 2; ++i)
1106       PUSH_DATA(push, 0);
1107    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1108    PUSH_DATA (push, 0);
1109    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1110    PUSH_DATA (push, 0);
1111
1112    /* neither scissors, viewport nor stencil mask should affect clears */
1113    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1114    PUSH_DATA (push, 0);
1115
1116    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1117    PUSH_DATA (push, 1);
1118    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1119       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1120       PUSH_DATAf(push, 0.0f);
1121       PUSH_DATAf(push, 1.0f);
1122    }
1123    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1124    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1125
1126    /* We use scissors instead of exact view volume clipping,
1127     * so they're always enabled.
1128     */
1129    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1130       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1131       PUSH_DATA (push, 1);
1132       PUSH_DATA (push, 8192 << 16);
1133       PUSH_DATA (push, 8192 << 16);
1134    }
1135
1136 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1137
1138    i = 0;
1139    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1140    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1141    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1142    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1143    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1144    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1145    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1146    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1147    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1148    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1149    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1150    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1151    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1152
1153    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1154    PUSH_DATA (push, 1);
1155    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1156    PUSH_DATA (push, 1);
1157    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1158    PUSH_DATA (push, 0x40);
1159    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1160    PUSH_DATA (push, 0);
1161    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1162    PUSH_DATA (push, 0x30);
1163    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1164    PUSH_DATA (push, 3);
1165    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1166    PUSH_DATA (push, 0x20);
1167    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1168    PUSH_DATA (push, 0x00);
1169    screen->save_state.patch_vertices = 3;
1170
1171    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1172    PUSH_DATA (push, 0);
1173    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1174    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1175
1176    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1177
1178    if (nvc0_screen_init_compute(screen))
1179       goto fail;
1180
1181    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1182    for (i = 0; i < 5; ++i) {
1183       /* TIC and TSC entries for each unit (nve4+ only) */
1184       /* auxiliary constants (6 user clip planes, base instance id) */
1185       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1186       PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1187       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1188       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1189       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1190       PUSH_DATA (push, (15 << 4) | 1);
1191       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1192          unsigned j;
1193          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1194          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1195          for (j = 0; j < 8; ++j)
1196             PUSH_DATA(push, j);
1197       } else {
1198          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1199          PUSH_DATA (push, 0x54);
1200       }
1201
1202       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1203       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1204       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1205       PUSH_DATA (push, 0); /* 0 */
1206       PUSH_DATA (push, 0);
1207       PUSH_DATA (push, 1); /* 1 */
1208       PUSH_DATA (push, 0);
1209       PUSH_DATA (push, 0); /* 2 */
1210       PUSH_DATA (push, 1);
1211       PUSH_DATA (push, 1); /* 3 */
1212       PUSH_DATA (push, 1);
1213       PUSH_DATA (push, 2); /* 4 */
1214       PUSH_DATA (push, 0);
1215       PUSH_DATA (push, 3); /* 5 */
1216       PUSH_DATA (push, 0);
1217       PUSH_DATA (push, 2); /* 6 */
1218       PUSH_DATA (push, 1);
1219       PUSH_DATA (push, 3); /* 7 */
1220       PUSH_DATA (push, 1);
1221    }
1222    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1223    PUSH_DATA (push, 0);
1224
1225    PUSH_KICK (push);
1226
1227    screen->tic.entries = CALLOC(4096, sizeof(void *));
1228    screen->tsc.entries = screen->tic.entries + 2048;
1229
1230    if (!nvc0_blitter_create(screen))
1231       goto fail;
1232
1233    screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1234    screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1235
1236    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1237
1238    return &screen->base;
1239
1240 fail:
1241    screen->base.base.context_create = NULL;
1242    return &screen->base;
1243 }
1244
1245 int
1246 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1247 {
1248    int i = screen->tic.next;
1249
1250    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1251       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1252
1253    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1254
1255    if (screen->tic.entries[i])
1256       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1257
1258    screen->tic.entries[i] = entry;
1259    return i;
1260 }
1261
1262 int
1263 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1264 {
1265    int i = screen->tsc.next;
1266
1267    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1268       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1269
1270    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1271
1272    if (screen->tsc.entries[i])
1273       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1274
1275    screen->tsc.entries[i] = entry;
1276    return i;
1277 }