src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/format/u_format.h"
  27 #include "util/format/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30 #include "compiler/nir/nir.h"
  31
  32 #include "nouveau_vp3_video.h"
  33
  34 #include "nvc0/nvc0_context.h"
  35 #include "nvc0/nvc0_screen.h"
  36
  37 #include "nvc0/mme/com9097.mme.h"
  38 #include "nvc0/mme/com90c0.mme.h"
  39
  40 #include "nv50/g80_texture.xml.h"
  41
  42 static bool
  43 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  44                                 enum pipe_format format,
  45                                 enum pipe_texture_target target,
  46                                 unsigned sample_count,
  47                                 unsigned storage_sample_count,
  48                                 unsigned bindings)
  49 {
  50    const struct util_format_description *desc = util_format_description(format);
  51
  52    if (sample_count > 8)
  53       return false;
  54    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  55       return false;
  56
  57    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  58       return false;
  59
  60    /* Short-circuit the rest of the logic -- this is used by the state tracker
  61     * to determine valid MS levels in a no-attachments scenario.
  62     */
  63    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  64       return true;
  65
  66    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  67       if (util_format_get_blocksizebits(format) == 3 * 32)
  68          return false;
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A
  79     * and GM20B.
  80     */
  81    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  82         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  83        nouveau_screen(pscreen)->device->chipset != 0x12b &&
  84        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  85       return false;
  86
  87    /* shared is always supported */
  88    bindings &= ~(PIPE_BIND_LINEAR |
  89                  PIPE_BIND_SHARED);
  90
  91    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  92       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  93           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
  94          /* This should work on Fermi, but for currently unknown reasons it
  95           * does not and results in breaking reads from pbos. */
  96          return false;
  97       }
  98    }
  99
 100    return (( nvc0_format_table[format].usage |
 101             nvc0_vertex_format[format].usage) & bindings) == bindings;
 102 }
 103
 104 static int
 105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 106 {
 107    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 108    const struct nouveau_screen *screen = nouveau_screen(pscreen);
 109    struct nouveau_device *dev = screen->device;
 110
 111    switch (param) {
 112    /* non-boolean caps */
 113    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 114       return 16384;
 115    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 116       return 15;
 117    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 118       return 12;
 119    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 120       return 2048;
 121    case PIPE_CAP_MIN_TEXEL_OFFSET:
 122       return -8;
 123    case PIPE_CAP_MAX_TEXEL_OFFSET:
 124       return 7;
 125    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 126       return -32;
 127    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 128       return 31;
 129    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 130       return 128 * 1024 * 1024;
 131    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 132       return 430;
 133    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 134       return 430;
 135    case PIPE_CAP_MAX_RENDER_TARGETS:
 136       return 8;
 137    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 138       return 1;
 139    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 140    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 141       return 8;
 142    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 143       return 4;
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 145    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 146       return 128;
 147    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 148    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 149       return 1024;
 150    case PIPE_CAP_MAX_VERTEX_STREAMS:
 151       return 4;
 152    case PIPE_CAP_MAX_GS_INVOCATIONS:
 153       return 32;
 154    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 155       return 1 << 27;
 156    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 157       return 2048;
 158    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 159       return 2047;
 160    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 161       return 256;
 162    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 163       if (class_3d < GM107_3D_CLASS)
 164          return 256; /* IMAGE bindings require alignment to 256 */
 165       return 16;
 166    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 167       return 16;
 168    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 169       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 170    case PIPE_CAP_MAX_VIEWPORTS:
 171       return NVC0_MAX_VIEWPORTS;
 172    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 173       return 4;
 174    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 175       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 176    case PIPE_CAP_ENDIANNESS:
 177       return PIPE_ENDIAN_LITTLE;
 178    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 179       return 30;
 180    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 181       return NVC0_MAX_WINDOW_RECTANGLES;
 182    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 183       return class_3d >= GM200_3D_CLASS ? 8 : 0;
 184    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 185       return 64 * 1024 * 1024;
 186    case PIPE_CAP_MAX_VARYINGS:
 187       /* NOTE: These only count our slots for GENERIC varyings.
 188        * The address space may be larger, but the actual hard limit seems to be
 189        * less than what the address space layout permits, so don't add TEXCOORD,
 190        * COLOR, etc. here.
 191        */
 192       return 0x1f0 / 16;
 193    case PIPE_CAP_MAX_VERTEX_BUFFERS:
 194       return 16;
 195
 196    /* supported caps */
 197    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 198    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 199    case PIPE_CAP_TEXTURE_SWIZZLE:
 200    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 201    case PIPE_CAP_NPOT_TEXTURES:
 202    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 203    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 204    case PIPE_CAP_ANISOTROPIC_FILTER:
 205    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 206    case PIPE_CAP_CUBE_MAP_ARRAY:
 207    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 208    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 209    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 210    case PIPE_CAP_POINT_SPRITE:
 211    case PIPE_CAP_TGSI_TEXCOORD:
 212    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 213    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 214    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 215    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 216    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 217    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 218    case PIPE_CAP_QUERY_TIMESTAMP:
 219    case PIPE_CAP_QUERY_TIME_ELAPSED:
 220    case PIPE_CAP_OCCLUSION_QUERY:
 221    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 222    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 223    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 224    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 225    case PIPE_CAP_INDEP_BLEND_ENABLE:
 226    case PIPE_CAP_INDEP_BLEND_FUNC:
 227    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 228    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 229    case PIPE_CAP_PRIMITIVE_RESTART:
 230    case PIPE_CAP_TGSI_INSTANCEID:
 231    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 232    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 233    case PIPE_CAP_CONDITIONAL_RENDER:
 234    case PIPE_CAP_TEXTURE_BARRIER:
 235    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 236    case PIPE_CAP_START_INSTANCE:
 237    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 238    case PIPE_CAP_DRAW_INDIRECT:
 239    case PIPE_CAP_USER_VERTEX_BUFFERS:
 240    case PIPE_CAP_TEXTURE_QUERY_LOD:
 241    case PIPE_CAP_SAMPLE_SHADING:
 242    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 243    case PIPE_CAP_TEXTURE_GATHER_SM5:
 244    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 245    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 246    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 247    case PIPE_CAP_CLIP_HALFZ:
 248    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 249    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 250    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 251    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 252    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 253    case PIPE_CAP_TGSI_TXQS:
 254    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 255    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 256    case PIPE_CAP_SHAREABLE_SHADERS:
 257    case PIPE_CAP_CLEAR_TEXTURE:
 258    case PIPE_CAP_DRAW_PARAMETERS:
 259    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 260    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 261    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 262    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 263    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 264    case PIPE_CAP_INVALIDATE_BUFFER:
 265    case PIPE_CAP_STRING_MARKER:
 266    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 267    case PIPE_CAP_CULL_DISTANCE:
 268    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 269    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 270    case PIPE_CAP_TGSI_VOTE:
 271    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 272    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 273    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 274    case PIPE_CAP_DOUBLES:
 275    case PIPE_CAP_INT64:
 276    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 277    case PIPE_CAP_TGSI_CLOCK:
 278    case PIPE_CAP_COMPUTE:
 279    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 280    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 281    case PIPE_CAP_QUERY_SO_OVERFLOW:
 282    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 283    case PIPE_CAP_TGSI_DIV:
 284    case PIPE_CAP_TGSI_ATOMINC_WRAP:
 285    case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
 286    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 287    case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 288    case PIPE_CAP_FLATSHADE:
 289    case PIPE_CAP_ALPHA_TEST:
 290    case PIPE_CAP_POINT_SIZE_FIXED:
 291    case PIPE_CAP_TWO_SIDED_COLOR:
 292    case PIPE_CAP_CLIP_PLANES:
 293    case PIPE_CAP_TEXTURE_SHADOW_LOD:
 294       return 1;
 295    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 296       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 297    case PIPE_CAP_FBFETCH:
 298       return class_3d >= NVE4_3D_CLASS ? 1 : 0; /* needs testing on fermi */
 299    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 300    case PIPE_CAP_TGSI_BALLOT:
 301       return class_3d >= NVE4_3D_CLASS;
 302    case PIPE_CAP_BINDLESS_TEXTURE:
 303       return class_3d >= NVE4_3D_CLASS;
 304    case PIPE_CAP_TGSI_ATOMFADD:
 305       return class_3d < GM107_3D_CLASS; /* needs additional lowering */
 306    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 307    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 308    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 309    case PIPE_CAP_POST_DEPTH_COVERAGE:
 310    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 311    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 312    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 313    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 314    case PIPE_CAP_VIEWPORT_SWIZZLE:
 315    case PIPE_CAP_VIEWPORT_MASK:
 316       return class_3d >= GM200_3D_CLASS;
 317    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 318       return class_3d >= GP100_3D_CLASS;
 319
 320    /* caps has to be turned on with nir */
 321    case PIPE_CAP_INT64_DIVMOD:
 322       return screen->prefer_nir ? 1 : 0;
 323
 324    /* unsupported caps */
 325    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 326    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 327    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 328    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 329    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 330    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 331    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 332    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 333    case PIPE_CAP_FAKE_SW_MSAA:
 334    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 335    case PIPE_CAP_VERTEXID_NOBASE:
 336    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 337    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 338    case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 339    case PIPE_CAP_GENERATE_MIPMAP:
 340    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 341    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 342    case PIPE_CAP_QUERY_MEMORY_INFO:
 343    case PIPE_CAP_PCI_GROUP:
 344    case PIPE_CAP_PCI_BUS:
 345    case PIPE_CAP_PCI_DEVICE:
 346    case PIPE_CAP_PCI_FUNCTION:
 347    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 348    case PIPE_CAP_NATIVE_FENCE_FD:
 349    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 350    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 351    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 352    case PIPE_CAP_MEMOBJ:
 353    case PIPE_CAP_LOAD_CONSTBUF:
 354    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 355    case PIPE_CAP_TILE_RASTER_ORDER:
 356    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 357    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 358    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 359    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 360    case PIPE_CAP_FENCE_SIGNAL:
 361    case PIPE_CAP_CONSTBUF0_FLAGS:
 362    case PIPE_CAP_PACKED_UNIFORMS:
 363    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 364    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 365    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 366    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 367    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 368    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 369    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 370    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 371    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 372    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 373    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 374    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 375    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 376    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 377    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 378    case PIPE_CAP_FBFETCH_COHERENT:
 379    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
 380    case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
 381    case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS: /* could be done */
 382    case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
 383    case PIPE_CAP_FRONTEND_NOOP:
 384    case PIPE_CAP_GL_SPIRV:
 385    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 386       return 0;
 387
 388    case PIPE_CAP_VENDOR_ID:
 389       return 0x10de;
 390    case PIPE_CAP_DEVICE_ID: {
 391       uint64_t device_id;
 392       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 393          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 394          return -1;
 395       }
 396       return device_id;
 397    }
 398    case PIPE_CAP_ACCELERATED:
 399       return 1;
 400    case PIPE_CAP_VIDEO_MEMORY:
 401       return dev->vram_size >> 20;
 402    case PIPE_CAP_UMA:
 403       return 0;
 404
 405    default:
 406       debug_printf("%s: unhandled cap %d\n", __func__, param);
 407       /* fallthrough */
 408    /* caps where we want the default value */
 409    case PIPE_CAP_DMABUF:
 410    case PIPE_CAP_ESSL_FEATURE_LEVEL:
 411    case PIPE_CAP_THROTTLE:
 412       return u_pipe_screen_get_param_defaults(pscreen, param);
 413    }
 414 }
 415
 416 static int
 417 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 418                              enum pipe_shader_type shader,
 419                              enum pipe_shader_cap param)
 420 {
 421    const struct nouveau_screen *screen = nouveau_screen(pscreen);
 422    const uint16_t class_3d = screen->class_3d;
 423
 424    switch (shader) {
 425    case PIPE_SHADER_VERTEX:
 426    case PIPE_SHADER_GEOMETRY:
 427    case PIPE_SHADER_FRAGMENT:
 428    case PIPE_SHADER_COMPUTE:
 429    case PIPE_SHADER_TESS_CTRL:
 430    case PIPE_SHADER_TESS_EVAL:
 431       break;
 432    default:
 433       return 0;
 434    }
 435
 436    switch (param) {
 437    case PIPE_SHADER_CAP_PREFERRED_IR:
 438       return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
 439    case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 440       uint32_t irs = 1 << PIPE_SHADER_IR_TGSI |
 441                      1 << PIPE_SHADER_IR_NIR;
 442       if (screen->force_enable_cl)
 443          irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED;
 444       return irs;
 445    }
 446    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 447    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 448    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 449    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 450       return 16384;
 451    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 452       return 16;
 453    case PIPE_SHADER_CAP_MAX_INPUTS:
 454       return 0x200 / 16;
 455    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 456       return 32;
 457    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 458       return NVC0_MAX_CONSTBUF_SIZE;
 459    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 460       return NVC0_MAX_PIPE_CONSTBUFS;
 461    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 462       return shader != PIPE_SHADER_FRAGMENT;
 463    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 464    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 465    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 466       return 1;
 467    case PIPE_SHADER_CAP_MAX_TEMPS:
 468       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 469    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 470       return 1;
 471    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 472       return 1;
 473    case PIPE_SHADER_CAP_SUBROUTINES:
 474       return 1;
 475    case PIPE_SHADER_CAP_INTEGERS:
 476       return 1;
 477    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 478       return 1;
 479    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 480       return 1;
 481    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 482       return 1;
 483    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 484    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 485    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 486    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 487    case PIPE_SHADER_CAP_INT64_ATOMICS:
 488    case PIPE_SHADER_CAP_FP16:
 489    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 490    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 491       return 0;
 492    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 493       return NVC0_MAX_BUFFERS;
 494    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 495       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 496    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 497       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 498    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 499       return 32;
 500    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 501       if (class_3d >= NVE4_3D_CLASS)
 502          return NVC0_MAX_IMAGES;
 503       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 504          return NVC0_MAX_IMAGES;
 505       return 0;
 506    default:
 507       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 508       return 0;
 509    }
 510 }
 511
 512 static float
 513 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 514 {
 515    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 516
 517    switch (param) {
 518    case PIPE_CAPF_MAX_LINE_WIDTH:
 519    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 520       return 10.0f;
 521    case PIPE_CAPF_MAX_POINT_WIDTH:
 522       return 63.0f;
 523    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 524       return 63.375f;
 525    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 526       return 16.0f;
 527    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 528       return 15.0f;
 529    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 530       return 0.0f;
 531    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 532       return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
 533    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 534       return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
 535    }
 536
 537    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 538    return 0.0f;
 539 }
 540
 541 static int
 542 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 543                               enum pipe_shader_ir ir_type,
 544                               enum pipe_compute_cap param, void *data)
 545 {
 546    struct nvc0_screen *screen = nvc0_screen(pscreen);
 547    const uint16_t obj_class = screen->compute->oclass;
 548
 549 #define RET(x) do {                  \
 550    if (data)                         \
 551       memcpy(data, x, sizeof(x));    \
 552    return sizeof(x);                 \
 553 } while (0)
 554
 555    switch (param) {
 556    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 557       RET((uint64_t []) { 3 });
 558    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 559       if (obj_class >= NVE4_COMPUTE_CLASS) {
 560          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 561       } else {
 562          RET(((uint64_t []) { 65535, 65535, 65535 }));
 563       }
 564    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 565       RET(((uint64_t []) { 1024, 1024, 64 }));
 566    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 567       RET((uint64_t []) { 1024 });
 568    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 569       if (obj_class >= NVE4_COMPUTE_CLASS) {
 570          RET((uint64_t []) { 1024 });
 571       } else {
 572          RET((uint64_t []) { 512 });
 573       }
 574    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 575       RET((uint64_t []) { 1ULL << 40 });
 576    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 577       switch (obj_class) {
 578       case GM200_COMPUTE_CLASS:
 579          RET((uint64_t []) { 96 << 10 });
 580          break;
 581       case GM107_COMPUTE_CLASS:
 582          RET((uint64_t []) { 64 << 10 });
 583          break;
 584       default:
 585          RET((uint64_t []) { 48 << 10 });
 586          break;
 587       }
 588    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 589       RET((uint64_t []) { 512 << 10 });
 590    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 591       RET((uint64_t []) { 4096 });
 592    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 593       RET((uint32_t []) { 32 });
 594    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 595       RET((uint64_t []) { 1ULL << 40 });
 596    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 597       RET((uint32_t []) { 0 });
 598    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 599       RET((uint32_t []) { screen->mp_count_compute });
 600    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 601       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 602    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 603       RET((uint32_t []) { 64 });
 604    default:
 605       return 0;
 606    }
 607
 608 #undef RET
 609 }
 610
 611 static void
 612 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
 613                                   unsigned sample_count,
 614                                   unsigned *width, unsigned *height)
 615 {
 616    switch (sample_count) {
 617    case 0:
 618    case 1:
 619       /* this could be 4x4, but the GL state tracker makes it difficult to
 620        * create a 1x MSAA texture and smaller grids save CB space */
 621       *width = 2;
 622       *height = 4;
 623       break;
 624    case 2:
 625       *width = 2;
 626       *height = 4;
 627       break;
 628    case 4:
 629       *width = 2;
 630       *height = 2;
 631       break;
 632    case 8:
 633       *width = 1;
 634       *height = 2;
 635       break;
 636    default:
 637       assert(0);
 638    }
 639 }
 640
 641 static void
 642 nvc0_screen_destroy(struct pipe_screen *pscreen)
 643 {
 644    struct nvc0_screen *screen = nvc0_screen(pscreen);
 645
 646    if (!nouveau_drm_screen_unref(&screen->base))
 647       return;
 648
 649    if (screen->base.fence.current) {
 650       struct nouveau_fence *current = NULL;
 651
 652       /* nouveau_fence_wait will create a new current fence, so wait on the
 653        * _current_ one, and remove both.
 654        */
 655       nouveau_fence_ref(screen->base.fence.current, &current);
 656       nouveau_fence_wait(current, NULL);
 657       nouveau_fence_ref(NULL, &current);
 658       nouveau_fence_ref(NULL, &screen->base.fence.current);
 659    }
 660    if (screen->base.pushbuf)
 661       screen->base.pushbuf->user_priv = NULL;
 662
 663    if (screen->blitter)
 664       nvc0_blitter_destroy(screen);
 665    if (screen->pm.prog) {
 666       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 667       nvc0_program_destroy(NULL, screen->pm.prog);
 668       FREE(screen->pm.prog);
 669    }
 670
 671    nouveau_bo_ref(NULL, &screen->text);
 672    nouveau_bo_ref(NULL, &screen->uniform_bo);
 673    nouveau_bo_ref(NULL, &screen->tls);
 674    nouveau_bo_ref(NULL, &screen->txc);
 675    nouveau_bo_ref(NULL, &screen->fence.bo);
 676    nouveau_bo_ref(NULL, &screen->poly_cache);
 677
 678    nouveau_heap_destroy(&screen->lib_code);
 679    nouveau_heap_destroy(&screen->text_heap);
 680
 681    FREE(screen->tic.entries);
 682
 683    nouveau_object_del(&screen->eng3d);
 684    nouveau_object_del(&screen->eng2d);
 685    nouveau_object_del(&screen->m2mf);
 686    nouveau_object_del(&screen->compute);
 687    nouveau_object_del(&screen->nvsw);
 688
 689    nouveau_screen_fini(&screen->base);
 690
 691    FREE(screen);
 692 }
 693
 694 static int
 695 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 696                      unsigned size, const uint32_t *data)
 697 {
 698    struct nouveau_pushbuf *push = screen->base.pushbuf;
 699
 700    size /= 4;
 701
 702    assert((pos + size) <= 0x800);
 703
 704    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 705    PUSH_DATA (push, (m - 0x3800) / 8);
 706    PUSH_DATA (push, pos);
 707    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 708    PUSH_DATA (push, pos);
 709    PUSH_DATAp(push, data, size);
 710
 711    return pos + size;
 712 }
 713
 714 static void
 715 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 716 {
 717    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 718    PUSH_DATA (push, 0xff);
 719    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 720    PUSH_DATA (push, 0xff);
 721    PUSH_DATA (push, 0xff);
 722    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 723    PUSH_DATA (push, 0xff);
 724    PUSH_DATA (push, 0xff);
 725    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 726    PUSH_DATA (push, 0x3f);
 727
 728    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 729    PUSH_DATA (push, (3 << 16) | 3);
 730    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 731    PUSH_DATA (push, (2 << 16) | 2);
 732
 733    if (obj_class < GM107_3D_CLASS) {
 734       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 735       PUSH_DATA (push, 0);
 736    }
 737    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 738    PUSH_DATA (push, 0x10);
 739    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 740    PUSH_DATA (push, 0x10);
 741    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 742    PUSH_DATA (push, 0x10);
 743    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 744    PUSH_DATA (push, 0x10);
 745    PUSH_DATA (push, 0x10);
 746    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 747    PUSH_DATA (push, 0x10);
 748    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 749    PUSH_DATA (push, 0xe);
 750
 751    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 752    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 753    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 754    PUSH_DATA (push, 0);
 755    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 756    PUSH_DATA (push, 3);
 757
 758    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 759    PUSH_DATA (push, 0x3fffff);
 760    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 761    PUSH_DATA (push, 1);
 762    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 763    PUSH_DATA (push, 1);
 764
 765    if (obj_class < GM107_3D_CLASS) {
 766       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 767       PUSH_DATA (push, 3);
 768
 769       if (obj_class >= NVE4_3D_CLASS) {
 770          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 771          PUSH_DATA (push, 1);
 772       }
 773    }
 774
 775    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 776     * are supposed to do */
 777 }
 778
 779 static void
 780 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 781 {
 782    struct nvc0_screen *screen = nvc0_screen(pscreen);
 783    struct nouveau_pushbuf *push = screen->base.pushbuf;
 784
 785    /* we need to do it after possible flush in MARK_RING */
 786    *sequence = ++screen->base.fence.sequence;
 787
 788    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 789    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 790    PUSH_DATAh(push, screen->fence.bo->offset);
 791    PUSH_DATA (push, screen->fence.bo->offset);
 792    PUSH_DATA (push, *sequence);
 793    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 794               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 795 }
 796
 797 static u32
 798 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 799 {
 800    struct nvc0_screen *screen = nvc0_screen(pscreen);
 801    return screen->fence.map[0];
 802 }
 803
 804 static int
 805 nvc0_screen_init_compute(struct nvc0_screen *screen)
 806 {
 807    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 808
 809    switch (screen->base.device->chipset & ~0xf) {
 810    case 0xc0:
 811    case 0xd0:
 812       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 813    case 0xe0:
 814    case 0xf0:
 815    case 0x100:
 816    case 0x110:
 817    case 0x120:
 818    case 0x130:
 819       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 820    default:
 821       return -1;
 822    }
 823 }
 824
 825 static int
 826 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 827                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 828 {
 829    struct nouveau_bo *bo = NULL;
 830    int ret;
 831    uint64_t size = (lpos + lneg) * 32 + cstack;
 832
 833    if (size >= (1 << 20)) {
 834       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 835       return -1;
 836    }
 837
 838    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 839    size  = align(size, 0x8000);
 840    size *= screen->mp_count;
 841
 842    size = align(size, 1 << 17);
 843
 844    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 845                         NULL, &bo);
 846    if (ret)
 847       return ret;
 848
 849    /* Make sure that the pushbuf has acquired a reference to the old tls
 850     * segment, as it may have commands that will reference it.
 851     */
 852    if (screen->tls)
 853       PUSH_REFN(screen->base.pushbuf, screen->tls,
 854                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
 855    nouveau_bo_ref(NULL, &screen->tls);
 856    screen->tls = bo;
 857    return 0;
 858 }
 859
 860 int
 861 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 862 {
 863    struct nouveau_pushbuf *push = screen->base.pushbuf;
 864    struct nouveau_bo *bo;
 865    int ret;
 866
 867    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 868                         1 << 17, size, NULL, &bo);
 869    if (ret)
 870       return ret;
 871
 872    /* Make sure that the pushbuf has acquired a reference to the old text
 873     * segment, as it may have commands that will reference it.
 874     */
 875    if (screen->text)
 876       PUSH_REFN(push, screen->text,
 877                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
 878    nouveau_bo_ref(NULL, &screen->text);
 879    screen->text = bo;
 880
 881    nouveau_heap_destroy(&screen->lib_code);
 882    nouveau_heap_destroy(&screen->text_heap);
 883
 884    /* XXX: getting a page fault at the end of the code buffer every few
 885     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 886     */
 887    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 888
 889    /* update the code segment setup */
 890    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 891    PUSH_DATAh(push, screen->text->offset);
 892    PUSH_DATA (push, screen->text->offset);
 893    if (screen->compute) {
 894       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 895       PUSH_DATAh(push, screen->text->offset);
 896       PUSH_DATA (push, screen->text->offset);
 897    }
 898
 899    return 0;
 900 }
 901
 902 void
 903 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
 904                        int stage, int index, int size, uint64_t addr)
 905 {
 906    assert(stage != 5);
 907
 908    struct nouveau_pushbuf *push = screen->base.pushbuf;
 909
 910    if (screen->base.class_3d >= GM107_3D_CLASS) {
 911       struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
 912
 913       // TODO: Better figure out the conditions in which this is needed
 914       bool serialize = binding->addr == addr && binding->size != size;
 915       if (can_serialize)
 916          serialize = serialize && *can_serialize;
 917       if (serialize) {
 918          IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 919          if (can_serialize)
 920             *can_serialize = false;
 921       }
 922
 923       binding->addr = addr;
 924       binding->size = size;
 925    }
 926
 927    if (size >= 0) {
 928       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 929       PUSH_DATA (push, size);
 930       PUSH_DATAh(push, addr);
 931       PUSH_DATA (push, addr);
 932    }
 933    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
 934 }
 935
 936 static const nir_shader_compiler_options nir_options = {
 937    .lower_fdiv = false,
 938    .lower_ffma = false,
 939    .fuse_ffma = false, /* nir doesn't track mad vs fma */
 940    .lower_flrp32 = true,
 941    .lower_flrp64 = true,
 942    .lower_fpow = false,
 943    .lower_fsat = false,
 944    .lower_fsqrt = false, // TODO: only before gm200
 945    .lower_fmod = true,
 946    .lower_bitfield_extract = false,
 947    .lower_bitfield_extract_to_shifts = false,
 948    .lower_bitfield_insert = false,
 949    .lower_bitfield_insert_to_shifts = false,
 950    .lower_bitfield_reverse = false,
 951    .lower_bit_count = false,
 952    .lower_ifind_msb = false,
 953    .lower_find_lsb = false,
 954    .lower_uadd_carry = true, // TODO
 955    .lower_usub_borrow = true, // TODO
 956    .lower_mul_high = false,
 957    .lower_negate = false,
 958    .lower_sub = true,
 959    .lower_scmp = true, // TODO: not implemented yet
 960    .lower_idiv = true,
 961    .lower_isign = false, // TODO
 962    .fdot_replicates = false, // TODO
 963    .lower_ffloor = false, // TODO
 964    .lower_ffract = true,
 965    .lower_fceil = false, // TODO
 966    .lower_ldexp = true,
 967    .lower_pack_half_2x16 = true,
 968    .lower_pack_unorm_2x16 = true,
 969    .lower_pack_snorm_2x16 = true,
 970    .lower_pack_unorm_4x8 = true,
 971    .lower_pack_snorm_4x8 = true,
 972    .lower_unpack_half_2x16 = true,
 973    .lower_unpack_unorm_2x16 = true,
 974    .lower_unpack_snorm_2x16 = true,
 975    .lower_unpack_unorm_4x8 = true,
 976    .lower_unpack_snorm_4x8 = true,
 977    .lower_extract_byte = true,
 978    .lower_extract_word = true,
 979    .lower_all_io_to_temps = false,
 980    .vertex_id_zero_based = false,
 981    .lower_base_vertex = false,
 982    .lower_helper_invocation = false,
 983    .lower_cs_local_index_from_id = true,
 984    .lower_cs_local_id_from_index = false,
 985    .lower_device_index_to_zero = false, // TODO
 986    .lower_wpos_pntc = false, // TODO
 987    .lower_hadd = true, // TODO
 988    .lower_add_sat = true, // TODO
 989    .use_interpolated_input_intrinsics = true,
 990    .lower_mul_2x32_64 = true, // TODO
 991    .max_unroll_iterations = 32,
 992    .lower_int64_options = nir_lower_ufind_msb64|nir_lower_divmod64, // TODO
 993    .lower_doubles_options = nir_lower_dmod, // TODO
 994    .lower_to_scalar = true,
 995 };
 996
 997 static const void *
 998 nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
 999                                  enum pipe_shader_ir ir,
1000                                  enum pipe_shader_type shader)
1001 {
1002    if (ir == PIPE_SHADER_IR_NIR)
1003       return &nir_options;
1004    return NULL;
1005 }
1006
1007 #define FAIL_SCREEN_INIT(str, err)                    \
1008    do {                                               \
1009       NOUVEAU_ERR(str, err);                          \
1010       goto fail;                                      \
1011    } while(0)
1012
1013 struct nouveau_screen *
1014 nvc0_screen_create(struct nouveau_device *dev)
1015 {
1016    struct nvc0_screen *screen;
1017    struct pipe_screen *pscreen;
1018    struct nouveau_object *chan;
1019    struct nouveau_pushbuf *push;
1020    uint64_t value;
1021    uint32_t obj_class;
1022    uint32_t flags;
1023    int ret;
1024    unsigned i;
1025
1026    switch (dev->chipset & ~0xf) {
1027    case 0xc0:
1028    case 0xd0:
1029    case 0xe0:
1030    case 0xf0:
1031    case 0x100:
1032    case 0x110:
1033    case 0x120:
1034    case 0x130:
1035       break;
1036    default:
1037       return NULL;
1038    }
1039
1040    screen = CALLOC_STRUCT(nvc0_screen);
1041    if (!screen)
1042       return NULL;
1043    pscreen = &screen->base.base;
1044    pscreen->destroy = nvc0_screen_destroy;
1045
1046    ret = nouveau_screen_init(&screen->base, dev);
1047    if (ret)
1048       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
1049    chan = screen->base.channel;
1050    push = screen->base.pushbuf;
1051    push->user_priv = screen;
1052    push->rsvd_kick = 5;
1053
1054    /* TODO: could this be higher on Kepler+? how does reclocking vs no
1055     * reclocking affect performance?
1056     * TODO: could this be higher on Fermi?
1057     */
1058    if (dev->chipset >= 0xe0)
1059       screen->base.transfer_pushbuf_threshold = 1024;
1060
1061    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
1062       PIPE_BIND_SHADER_BUFFER |
1063       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
1064       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
1065    screen->base.sysmem_bindings |=
1066       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
1067
1068    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
1069       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
1070       screen->base.vidmem_bindings = 0;
1071    }
1072
1073    pscreen->context_create = nvc0_create;
1074    pscreen->is_format_supported = nvc0_screen_is_format_supported;
1075    pscreen->get_param = nvc0_screen_get_param;
1076    pscreen->get_shader_param = nvc0_screen_get_shader_param;
1077    pscreen->get_paramf = nvc0_screen_get_paramf;
1078    pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
1079    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
1080    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
1081    /* nir stuff */
1082    pscreen->get_compiler_options = nvc0_screen_get_compiler_options;
1083
1084    nvc0_screen_init_resource_functions(pscreen);
1085
1086    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1087    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1088
1089    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
1090    if (screen->base.drm->version >= 0x01000202)
1091       flags |= NOUVEAU_BO_COHERENT;
1092
1093    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
1094    if (ret)
1095       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
1096    nouveau_bo_map(screen->fence.bo, 0, NULL);
1097    screen->fence.map = screen->fence.bo->map;
1098    screen->base.fence.emit = nvc0_screen_fence_emit;
1099    screen->base.fence.update = nvc0_screen_fence_update;
1100
1101
1102    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
1103                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
1104    if (ret)
1105       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
1106
1107    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
1108    PUSH_DATA (push, screen->nvsw->handle);
1109
1110    switch (dev->chipset & ~0xf) {
1111    case 0x130:
1112    case 0x120:
1113    case 0x110:
1114    case 0x100:
1115    case 0xf0:
1116       obj_class = NVF0_P2MF_CLASS;
1117       break;
1118    case 0xe0:
1119       obj_class = NVE4_P2MF_CLASS;
1120       break;
1121    default:
1122       obj_class = NVC0_M2MF_CLASS;
1123       break;
1124    }
1125    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
1126                             &screen->m2mf);
1127    if (ret)
1128       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
1129
1130    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
1131    PUSH_DATA (push, screen->m2mf->oclass);
1132    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1133       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1134       PUSH_DATA (push, 0xa0b5);
1135    }
1136
1137    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1138                             &screen->eng2d);
1139    if (ret)
1140       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1141
1142    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1143    PUSH_DATA (push, screen->eng2d->oclass);
1144    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1145    PUSH_DATA (push, 0);
1146    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1147    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1148    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1149    PUSH_DATA (push, 0);
1150    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1151    PUSH_DATA (push, 0);
1152    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1153    PUSH_DATA (push, 0x3f);
1154    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1155    PUSH_DATA (push, 1);
1156    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1157    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1158
1159    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1160    PUSH_DATAh(push, screen->fence.bo->offset + 16);
1161    PUSH_DATA (push, screen->fence.bo->offset + 16);
1162
1163    switch (dev->chipset & ~0xf) {
1164    case 0x130:
1165       switch (dev->chipset) {
1166       case 0x130:
1167       case 0x13b:
1168          obj_class = GP100_3D_CLASS;
1169          break;
1170       default:
1171          obj_class = GP102_3D_CLASS;
1172          break;
1173       }
1174       break;
1175    case 0x120:
1176       obj_class = GM200_3D_CLASS;
1177       break;
1178    case 0x110:
1179       obj_class = GM107_3D_CLASS;
1180       break;
1181    case 0x100:
1182    case 0xf0:
1183       obj_class = NVF0_3D_CLASS;
1184       break;
1185    case 0xe0:
1186       switch (dev->chipset) {
1187       case 0xea:
1188          obj_class = NVEA_3D_CLASS;
1189          break;
1190       default:
1191          obj_class = NVE4_3D_CLASS;
1192          break;
1193       }
1194       break;
1195    case 0xd0:
1196       obj_class = NVC8_3D_CLASS;
1197       break;
1198    case 0xc0:
1199    default:
1200       switch (dev->chipset) {
1201       case 0xc8:
1202          obj_class = NVC8_3D_CLASS;
1203          break;
1204       case 0xc1:
1205          obj_class = NVC1_3D_CLASS;
1206          break;
1207       default:
1208          obj_class = NVC0_3D_CLASS;
1209          break;
1210       }
1211       break;
1212    }
1213    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1214                             &screen->eng3d);
1215    if (ret)
1216       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1217    screen->base.class_3d = obj_class;
1218
1219    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1220    PUSH_DATA (push, screen->eng3d->oclass);
1221
1222    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1223    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1224
1225    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1226       /* kill shaders after about 1 second (at 100 MHz) */
1227       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1228       PUSH_DATA (push, 0x17);
1229    }
1230
1231    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1232                     screen->base.drm->version >= 0x01000101);
1233    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1234    for (i = 0; i < 8; ++i)
1235       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1236
1237    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1238    PUSH_DATA (push, 1);
1239
1240    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1241    PUSH_DATA (push, 0);
1242    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1243    PUSH_DATA (push, 0);
1244    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1245    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1246    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1247    PUSH_DATA (push, 0);
1248    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1249    PUSH_DATA (push, 1);
1250    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1251    PUSH_DATA (push, 1);
1252    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1253    PUSH_DATA (push, 1);
1254    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1255    PUSH_DATA (push, 0);
1256    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1257    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1258    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1259       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1260    } else {
1261       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1262       PUSH_DATA (push, 15);
1263    }
1264    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1265    PUSH_DATA (push, 8); /* 128 */
1266    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1267    PUSH_DATA (push, 1);
1268    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1269       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1270       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1271    }
1272
1273    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1274
1275    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1276    if (ret)
1277       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1278
1279    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1280    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1281                         &screen->uniform_bo);
1282    if (ret)
1283       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1284
1285    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1286
1287    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1288    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1289    PUSH_DATA (push, 256);
1290    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1291    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1292    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1293    PUSH_DATA (push, 0);
1294    PUSH_DATAf(push, 0.0f);
1295    PUSH_DATAf(push, 0.0f);
1296    PUSH_DATAf(push, 0.0f);
1297    PUSH_DATAf(push, 0.0f);
1298    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1299    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1300    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1301
1302    if (screen->base.drm->version >= 0x01000101) {
1303       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1304       if (ret)
1305          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1306    } else {
1307       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1308          value = (8 << 8) | 4;
1309       else
1310          value = (16 << 8) | 4;
1311    }
1312    screen->gpc_count = value & 0x000000ff;
1313    screen->mp_count = value >> 8;
1314    screen->mp_count_compute = screen->mp_count;
1315
1316    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1317    if (ret)
1318       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1319
1320    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1321    PUSH_DATAh(push, screen->tls->offset);
1322    PUSH_DATA (push, screen->tls->offset);
1323    PUSH_DATA (push, screen->tls->size >> 32);
1324    PUSH_DATA (push, screen->tls->size);
1325    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1326    PUSH_DATA (push, 0);
1327    /* Reduce likelihood of collision with real buffers by placing the hole at
1328     * the top of the 4G area. This will have to be dealt with for real
1329     * eventually by blocking off that area from the VM.
1330     */
1331    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1332    PUSH_DATA (push, 0xff << 24);
1333
1334    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1335       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1336                            &screen->poly_cache);
1337       if (ret)
1338          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1339
1340       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1341       PUSH_DATAh(push, screen->poly_cache->offset);
1342       PUSH_DATA (push, screen->poly_cache->offset);
1343       PUSH_DATA (push, 3);
1344    }
1345
1346    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1347                         &screen->txc);
1348    if (ret)
1349       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1350
1351    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1352    PUSH_DATAh(push, screen->txc->offset);
1353    PUSH_DATA (push, screen->txc->offset);
1354    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1355    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1356       screen->tic.maxwell = true;
1357       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1358          screen->tic.maxwell =
1359             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1360          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1361       }
1362    }
1363
1364    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1365    PUSH_DATAh(push, screen->txc->offset + 65536);
1366    PUSH_DATA (push, screen->txc->offset + 65536);
1367    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1368
1369    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1370    PUSH_DATA (push, 0);
1371    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1372    PUSH_DATA (push, 0);
1373    PUSH_DATA (push, 0);
1374    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1375    PUSH_DATA (push, 0x3f);
1376
1377    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1378    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1379    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1380    for (i = 0; i < 8 * 2; ++i)
1381       PUSH_DATA(push, 0);
1382    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1383    PUSH_DATA (push, 0);
1384    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1385    PUSH_DATA (push, 0);
1386
1387    /* neither scissors, viewport nor stencil mask should affect clears */
1388    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1389    PUSH_DATA (push, 0);
1390
1391    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1392    PUSH_DATA (push, 1);
1393    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1394       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1395       PUSH_DATAf(push, 0.0f);
1396       PUSH_DATAf(push, 1.0f);
1397    }
1398    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1399    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1400
1401    /* We use scissors instead of exact view volume clipping,
1402     * so they're always enabled.
1403     */
1404    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1405       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1406       PUSH_DATA (push, 1);
1407       PUSH_DATA (push, 16384 << 16);
1408       PUSH_DATA (push, 16384 << 16);
1409    }
1410
1411 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1412
1413    i = 0;
1414    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1415    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1416    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1417    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1418    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1419    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1420    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1421    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1422    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1423    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1424    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1425    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1426    MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1427    MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
1428    MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
1429    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1430
1431    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1432    PUSH_DATA (push, 1);
1433    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1434    PUSH_DATA (push, 1);
1435    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1436    PUSH_DATA (push, 0x40);
1437    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1438    PUSH_DATA (push, 0);
1439    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1440    PUSH_DATA (push, 0x30);
1441    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1442    PUSH_DATA (push, 3);
1443    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1444    PUSH_DATA (push, 0x20);
1445    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1446    PUSH_DATA (push, 0x00);
1447    screen->save_state.patch_vertices = 3;
1448
1449    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1450    PUSH_DATA (push, 0);
1451    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1452    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1453
1454    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1455
1456    if (nvc0_screen_init_compute(screen))
1457       goto fail;
1458
1459    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1460    for (i = 0; i < 5; ++i) {
1461       unsigned j = 0;
1462       for (j = 0; j < 16; j++)
1463          screen->cb_bindings[i][j].size = -1;
1464
1465       /* TIC and TSC entries for each unit (nve4+ only) */
1466       /* auxiliary constants (6 user clip planes, base instance id) */
1467       nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1468                              screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1469       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1470          unsigned j;
1471          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1472          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1473          for (j = 0; j < 8; ++j)
1474             PUSH_DATA(push, j);
1475       } else {
1476          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1477          PUSH_DATA (push, 0x54);
1478       }
1479
1480       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1481       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1482       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1483       PUSH_DATA (push, 0); /* 0 */
1484       PUSH_DATA (push, 0);
1485       PUSH_DATA (push, 1); /* 1 */
1486       PUSH_DATA (push, 0);
1487       PUSH_DATA (push, 0); /* 2 */
1488       PUSH_DATA (push, 1);
1489       PUSH_DATA (push, 1); /* 3 */
1490       PUSH_DATA (push, 1);
1491       PUSH_DATA (push, 2); /* 4 */
1492       PUSH_DATA (push, 0);
1493       PUSH_DATA (push, 3); /* 5 */
1494       PUSH_DATA (push, 0);
1495       PUSH_DATA (push, 2); /* 6 */
1496       PUSH_DATA (push, 1);
1497       PUSH_DATA (push, 3); /* 7 */
1498       PUSH_DATA (push, 1);
1499    }
1500    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1501    PUSH_DATA (push, 0);
1502
1503    PUSH_KICK (push);
1504
1505    screen->tic.entries = CALLOC(
1506          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1507          sizeof(void *));
1508    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1509    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1510
1511    if (!nvc0_blitter_create(screen))
1512       goto fail;
1513
1514    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1515
1516    return &screen->base;
1517
1518 fail:
1519    screen->base.base.context_create = NULL;
1520    return &screen->base;
1521 }
1522
1523 int
1524 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1525 {
1526    int i = screen->tic.next;
1527
1528    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1529       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1530
1531    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1532
1533    if (screen->tic.entries[i])
1534       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1535
1536    screen->tic.entries[i] = entry;
1537    return i;
1538 }
1539
1540 int
1541 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1542 {
1543    int i = screen->tsc.next;
1544
1545    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1546       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1547
1548    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1549
1550    if (screen->tsc.entries[i])
1551       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1552
1553    screen->tsc.entries[i] = entry;
1554    return i;
1555 }