src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30 #include "compiler/nir/nir.h"
  31
  32 #include "nouveau_vp3_video.h"
  33
  34 #include "nvc0/nvc0_context.h"
  35 #include "nvc0/nvc0_screen.h"
  36
  37 #include "nvc0/mme/com9097.mme.h"
  38 #include "nvc0/mme/com90c0.mme.h"
  39
  40 #include "nv50/g80_texture.xml.h"
  41
  42 static bool
  43 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  44                                 enum pipe_format format,
  45                                 enum pipe_texture_target target,
  46                                 unsigned sample_count,
  47                                 unsigned storage_sample_count,
  48                                 unsigned bindings)
  49 {
  50    const struct util_format_description *desc = util_format_description(format);
  51
  52    if (sample_count > 8)
  53       return false;
  54    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  55       return false;
  56
  57    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  58       return false;
  59
  60    /* Short-circuit the rest of the logic -- this is used by the state tracker
  61     * to determine valid MS levels in a no-attachments scenario.
  62     */
  63    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  64       return true;
  65
  66    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  67       if (util_format_get_blocksizebits(format) == 3 * 32)
  68          return false;
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  79     */
  80    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  81         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  82        /* The claim is that this should work on GM107 but it doesn't. Need to
  83         * test further and figure out if it's a nouveau issue or a HW one.
  84        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  85         */
  86        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  87       return false;
  88
  89    /* shared is always supported */
  90    bindings &= ~(PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  94       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  95           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
  96          /* This should work on Fermi, but for currently unknown reasons it
  97           * does not and results in breaking reads from pbos. */
  98          return false;
  99       }
 100    }
 101
 102    return (( nvc0_format_table[format].usage |
 103             nvc0_vertex_format[format].usage) & bindings) == bindings;
 104 }
 105
 106 static int
 107 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 108 {
 109    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 110    const struct nouveau_screen *screen = nouveau_screen(pscreen);
 111    struct nouveau_device *dev = screen->device;
 112
 113    switch (param) {
 114    /* non-boolean caps */
 115    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 116       return 16384;
 117    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 118       return 15;
 119    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 120       return 12;
 121    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 122       return 2048;
 123    case PIPE_CAP_MIN_TEXEL_OFFSET:
 124       return -8;
 125    case PIPE_CAP_MAX_TEXEL_OFFSET:
 126       return 7;
 127    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 128       return -32;
 129    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 130       return 31;
 131    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 132       return 128 * 1024 * 1024;
 133    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 134       return 430;
 135    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 136       return 430;
 137    case PIPE_CAP_MAX_RENDER_TARGETS:
 138       return 8;
 139    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 140       return 1;
 141    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 142    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 143       return 8;
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 145       return 4;
 146    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 147    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 148       return 128;
 149    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 150    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 151       return 1024;
 152    case PIPE_CAP_MAX_VERTEX_STREAMS:
 153       return 4;
 154    case PIPE_CAP_MAX_GS_INVOCATIONS:
 155       return 32;
 156    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 157       return 1 << 27;
 158    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 159       return 2048;
 160    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 161       return 2047;
 162    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 163       return 256;
 164    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 165       if (class_3d < GM107_3D_CLASS)
 166          return 256; /* IMAGE bindings require alignment to 256 */
 167       return 16;
 168    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 169       return 16;
 170    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 171       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 172    case PIPE_CAP_MAX_VIEWPORTS:
 173       return NVC0_MAX_VIEWPORTS;
 174    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 175       return 4;
 176    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 177       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 178    case PIPE_CAP_ENDIANNESS:
 179       return PIPE_ENDIAN_LITTLE;
 180    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 181       return 30;
 182    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 183       return NVC0_MAX_WINDOW_RECTANGLES;
 184    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 185       return class_3d >= GM200_3D_CLASS ? 8 : 0;
 186    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 187       return 64 * 1024 * 1024;
 188    case PIPE_CAP_MAX_VARYINGS:
 189       /* NOTE: These only count our slots for GENERIC varyings.
 190        * The address space may be larger, but the actual hard limit seems to be
 191        * less than what the address space layout permits, so don't add TEXCOORD,
 192        * COLOR, etc. here.
 193        */
 194       return 0x1f0 / 16;
 195
 196    /* supported caps */
 197    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 198    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 199    case PIPE_CAP_TEXTURE_SWIZZLE:
 200    case PIPE_CAP_NPOT_TEXTURES:
 201    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 202    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 203    case PIPE_CAP_ANISOTROPIC_FILTER:
 204    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 205    case PIPE_CAP_CUBE_MAP_ARRAY:
 206    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 207    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 208    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 209    case PIPE_CAP_POINT_SPRITE:
 210    case PIPE_CAP_TGSI_TEXCOORD:
 211    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 212    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 213    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 214    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 215    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 216    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 217    case PIPE_CAP_QUERY_TIMESTAMP:
 218    case PIPE_CAP_QUERY_TIME_ELAPSED:
 219    case PIPE_CAP_OCCLUSION_QUERY:
 220    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 221    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 222    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 223    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 224    case PIPE_CAP_INDEP_BLEND_ENABLE:
 225    case PIPE_CAP_INDEP_BLEND_FUNC:
 226    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 227    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 228    case PIPE_CAP_PRIMITIVE_RESTART:
 229    case PIPE_CAP_TGSI_INSTANCEID:
 230    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 231    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 232    case PIPE_CAP_CONDITIONAL_RENDER:
 233    case PIPE_CAP_TEXTURE_BARRIER:
 234    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 235    case PIPE_CAP_START_INSTANCE:
 236    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 237    case PIPE_CAP_DRAW_INDIRECT:
 238    case PIPE_CAP_USER_VERTEX_BUFFERS:
 239    case PIPE_CAP_TEXTURE_QUERY_LOD:
 240    case PIPE_CAP_SAMPLE_SHADING:
 241    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 242    case PIPE_CAP_TEXTURE_GATHER_SM5:
 243    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 244    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 245    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 246    case PIPE_CAP_CLIP_HALFZ:
 247    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 248    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 249    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 250    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 251    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 252    case PIPE_CAP_TGSI_TXQS:
 253    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 254    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 255    case PIPE_CAP_SHAREABLE_SHADERS:
 256    case PIPE_CAP_CLEAR_TEXTURE:
 257    case PIPE_CAP_DRAW_PARAMETERS:
 258    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 259    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 260    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 261    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 262    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 263    case PIPE_CAP_INVALIDATE_BUFFER:
 264    case PIPE_CAP_STRING_MARKER:
 265    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 266    case PIPE_CAP_CULL_DISTANCE:
 267    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 268    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 269    case PIPE_CAP_TGSI_VOTE:
 270    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 271    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 272    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 273    case PIPE_CAP_DOUBLES:
 274    case PIPE_CAP_INT64:
 275    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 276    case PIPE_CAP_TGSI_CLOCK:
 277    case PIPE_CAP_COMPUTE:
 278    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 279    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 280    case PIPE_CAP_QUERY_SO_OVERFLOW:
 281    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 282    case PIPE_CAP_TGSI_DIV:
 283       return 1;
 284    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 285       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 286    case PIPE_CAP_FBFETCH:
 287       return class_3d >= NVE4_3D_CLASS ? 1 : 0; /* needs testing on fermi */
 288    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 289    case PIPE_CAP_TGSI_BALLOT:
 290       return class_3d >= NVE4_3D_CLASS;
 291    case PIPE_CAP_BINDLESS_TEXTURE:
 292       return class_3d >= NVE4_3D_CLASS;
 293    case PIPE_CAP_TGSI_ATOMFADD:
 294       return class_3d < GM107_3D_CLASS; /* needs additional lowering */
 295    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 296    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 297    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 298    case PIPE_CAP_POST_DEPTH_COVERAGE:
 299    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 300    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 301    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 302    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 303       return class_3d >= GM200_3D_CLASS;
 304    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 305       return class_3d >= GP100_3D_CLASS;
 306
 307    /* caps has to be turned on with nir */
 308    case PIPE_CAP_INT64_DIVMOD:
 309       return screen->prefer_nir ? 1 : 0;
 310
 311    /* unsupported caps */
 312    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 313    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 314    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 315    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 316    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 317    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 318    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 319    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 320    case PIPE_CAP_FAKE_SW_MSAA:
 321    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 322    case PIPE_CAP_VERTEXID_NOBASE:
 323    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 324    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 325    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 326    case PIPE_CAP_GENERATE_MIPMAP:
 327    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 328    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 329    case PIPE_CAP_QUERY_MEMORY_INFO:
 330    case PIPE_CAP_PCI_GROUP:
 331    case PIPE_CAP_PCI_BUS:
 332    case PIPE_CAP_PCI_DEVICE:
 333    case PIPE_CAP_PCI_FUNCTION:
 334    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 335    case PIPE_CAP_NATIVE_FENCE_FD:
 336    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 337    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 338    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 339    case PIPE_CAP_MEMOBJ:
 340    case PIPE_CAP_LOAD_CONSTBUF:
 341    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 342    case PIPE_CAP_TILE_RASTER_ORDER:
 343    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 344    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 345    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 346    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 347    case PIPE_CAP_FENCE_SIGNAL:
 348    case PIPE_CAP_CONSTBUF0_FLAGS:
 349    case PIPE_CAP_PACKED_UNIFORMS:
 350    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 351    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 352    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 353    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 354    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 355    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 356    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 357    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 358    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 359    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 360    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 361    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 362    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 363    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 364    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 365    case PIPE_CAP_FBFETCH_COHERENT:
 366    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
 367       return 0;
 368
 369    case PIPE_CAP_VENDOR_ID:
 370       return 0x10de;
 371    case PIPE_CAP_DEVICE_ID: {
 372       uint64_t device_id;
 373       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 374          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 375          return -1;
 376       }
 377       return device_id;
 378    }
 379    case PIPE_CAP_ACCELERATED:
 380       return 1;
 381    case PIPE_CAP_VIDEO_MEMORY:
 382       return dev->vram_size >> 20;
 383    case PIPE_CAP_UMA:
 384       return 0;
 385
 386    default:
 387       debug_printf("%s: unhandled cap %d\n", __func__, param);
 388       /* fallthrough */
 389    /* caps where we want the default value */
 390    case PIPE_CAP_DMABUF:
 391    case PIPE_CAP_ESSL_FEATURE_LEVEL:
 392    case PIPE_CAP_MAX_FRAMES_IN_FLIGHT:
 393       return u_pipe_screen_get_param_defaults(pscreen, param);
 394    }
 395 }
 396
 397 static int
 398 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 399                              enum pipe_shader_type shader,
 400                              enum pipe_shader_cap param)
 401 {
 402    const struct nouveau_screen *screen = nouveau_screen(pscreen);
 403    const uint16_t class_3d = screen->class_3d;
 404
 405    switch (shader) {
 406    case PIPE_SHADER_VERTEX:
 407    case PIPE_SHADER_GEOMETRY:
 408    case PIPE_SHADER_FRAGMENT:
 409    case PIPE_SHADER_COMPUTE:
 410    case PIPE_SHADER_TESS_CTRL:
 411    case PIPE_SHADER_TESS_EVAL:
 412       break;
 413    default:
 414       return 0;
 415    }
 416
 417    switch (param) {
 418    case PIPE_SHADER_CAP_PREFERRED_IR:
 419       return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
 420    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 421       return 1 << PIPE_SHADER_IR_TGSI |
 422              1 << PIPE_SHADER_IR_NIR;
 423    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 424    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 425    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 426    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 427       return 16384;
 428    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 429       return 16;
 430    case PIPE_SHADER_CAP_MAX_INPUTS:
 431       return 0x200 / 16;
 432    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 433       return 32;
 434    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 435       return NVC0_MAX_CONSTBUF_SIZE;
 436    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 437       return NVC0_MAX_PIPE_CONSTBUFS;
 438    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 439       return shader != PIPE_SHADER_FRAGMENT;
 440    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 441    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 442    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 443       return 1;
 444    case PIPE_SHADER_CAP_MAX_TEMPS:
 445       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 446    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 447       return 1;
 448    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 449       return 1;
 450    case PIPE_SHADER_CAP_SUBROUTINES:
 451       return 1;
 452    case PIPE_SHADER_CAP_INTEGERS:
 453       return 1;
 454    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 455       return 1;
 456    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 457       return 1;
 458    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 459       return 1;
 460    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 461    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 462    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 463    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 464    case PIPE_SHADER_CAP_INT64_ATOMICS:
 465    case PIPE_SHADER_CAP_FP16:
 466    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 467    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 468       return 0;
 469    case PIPE_SHADER_CAP_SCALAR_ISA:
 470       return 1;
 471    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 472       return NVC0_MAX_BUFFERS;
 473    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 474       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 475    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 476       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 477    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 478       return 32;
 479    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 480       if (class_3d >= NVE4_3D_CLASS)
 481          return NVC0_MAX_IMAGES;
 482       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 483          return NVC0_MAX_IMAGES;
 484       return 0;
 485    default:
 486       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 487       return 0;
 488    }
 489 }
 490
 491 static float
 492 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 493 {
 494    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 495
 496    switch (param) {
 497    case PIPE_CAPF_MAX_LINE_WIDTH:
 498    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 499       return 10.0f;
 500    case PIPE_CAPF_MAX_POINT_WIDTH:
 501       return 63.0f;
 502    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 503       return 63.375f;
 504    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 505       return 16.0f;
 506    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 507       return 15.0f;
 508    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 509       return 0.0f;
 510    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 511       return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
 512    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 513       return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
 514    }
 515
 516    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 517    return 0.0f;
 518 }
 519
 520 static int
 521 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 522                               enum pipe_shader_ir ir_type,
 523                               enum pipe_compute_cap param, void *data)
 524 {
 525    struct nvc0_screen *screen = nvc0_screen(pscreen);
 526    const uint16_t obj_class = screen->compute->oclass;
 527
 528 #define RET(x) do {                  \
 529    if (data)                         \
 530       memcpy(data, x, sizeof(x));    \
 531    return sizeof(x);                 \
 532 } while (0)
 533
 534    switch (param) {
 535    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 536       RET((uint64_t []) { 3 });
 537    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 538       if (obj_class >= NVE4_COMPUTE_CLASS) {
 539          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 540       } else {
 541          RET(((uint64_t []) { 65535, 65535, 65535 }));
 542       }
 543    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 544       RET(((uint64_t []) { 1024, 1024, 64 }));
 545    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 546       RET((uint64_t []) { 1024 });
 547    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 548       if (obj_class >= NVE4_COMPUTE_CLASS) {
 549          RET((uint64_t []) { 1024 });
 550       } else {
 551          RET((uint64_t []) { 512 });
 552       }
 553    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 554       RET((uint64_t []) { 1ULL << 40 });
 555    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 556       switch (obj_class) {
 557       case GM200_COMPUTE_CLASS:
 558          RET((uint64_t []) { 96 << 10 });
 559          break;
 560       case GM107_COMPUTE_CLASS:
 561          RET((uint64_t []) { 64 << 10 });
 562          break;
 563       default:
 564          RET((uint64_t []) { 48 << 10 });
 565          break;
 566       }
 567    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 568       RET((uint64_t []) { 512 << 10 });
 569    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 570       RET((uint64_t []) { 4096 });
 571    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 572       RET((uint32_t []) { 32 });
 573    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 574       RET((uint64_t []) { 1ULL << 40 });
 575    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 576       RET((uint32_t []) { 0 });
 577    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 578       RET((uint32_t []) { screen->mp_count_compute });
 579    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 580       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 581    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 582       RET((uint32_t []) { 64 });
 583    default:
 584       return 0;
 585    }
 586
 587 #undef RET
 588 }
 589
 590 static void
 591 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
 592                                   unsigned sample_count,
 593                                   unsigned *width, unsigned *height)
 594 {
 595    switch (sample_count) {
 596    case 0:
 597    case 1:
 598       /* this could be 4x4, but the GL state tracker makes it difficult to
 599        * create a 1x MSAA texture and smaller grids save CB space */
 600       *width = 2;
 601       *height = 4;
 602       break;
 603    case 2:
 604       *width = 2;
 605       *height = 4;
 606       break;
 607    case 4:
 608       *width = 2;
 609       *height = 2;
 610       break;
 611    case 8:
 612       *width = 1;
 613       *height = 2;
 614       break;
 615    default:
 616       assert(0);
 617    }
 618 }
 619
 620 static void
 621 nvc0_screen_destroy(struct pipe_screen *pscreen)
 622 {
 623    struct nvc0_screen *screen = nvc0_screen(pscreen);
 624
 625    if (!nouveau_drm_screen_unref(&screen->base))
 626       return;
 627
 628    if (screen->base.fence.current) {
 629       struct nouveau_fence *current = NULL;
 630
 631       /* nouveau_fence_wait will create a new current fence, so wait on the
 632        * _current_ one, and remove both.
 633        */
 634       nouveau_fence_ref(screen->base.fence.current, &current);
 635       nouveau_fence_wait(current, NULL);
 636       nouveau_fence_ref(NULL, &current);
 637       nouveau_fence_ref(NULL, &screen->base.fence.current);
 638    }
 639    if (screen->base.pushbuf)
 640       screen->base.pushbuf->user_priv = NULL;
 641
 642    if (screen->blitter)
 643       nvc0_blitter_destroy(screen);
 644    if (screen->pm.prog) {
 645       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 646       nvc0_program_destroy(NULL, screen->pm.prog);
 647       FREE(screen->pm.prog);
 648    }
 649
 650    nouveau_bo_ref(NULL, &screen->text);
 651    nouveau_bo_ref(NULL, &screen->uniform_bo);
 652    nouveau_bo_ref(NULL, &screen->tls);
 653    nouveau_bo_ref(NULL, &screen->txc);
 654    nouveau_bo_ref(NULL, &screen->fence.bo);
 655    nouveau_bo_ref(NULL, &screen->poly_cache);
 656
 657    nouveau_heap_destroy(&screen->lib_code);
 658    nouveau_heap_destroy(&screen->text_heap);
 659
 660    FREE(screen->tic.entries);
 661
 662    nouveau_object_del(&screen->eng3d);
 663    nouveau_object_del(&screen->eng2d);
 664    nouveau_object_del(&screen->m2mf);
 665    nouveau_object_del(&screen->compute);
 666    nouveau_object_del(&screen->nvsw);
 667
 668    nouveau_screen_fini(&screen->base);
 669
 670    FREE(screen);
 671 }
 672
 673 static int
 674 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 675                      unsigned size, const uint32_t *data)
 676 {
 677    struct nouveau_pushbuf *push = screen->base.pushbuf;
 678
 679    size /= 4;
 680
 681    assert((pos + size) <= 0x800);
 682
 683    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 684    PUSH_DATA (push, (m - 0x3800) / 8);
 685    PUSH_DATA (push, pos);
 686    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 687    PUSH_DATA (push, pos);
 688    PUSH_DATAp(push, data, size);
 689
 690    return pos + size;
 691 }
 692
 693 static void
 694 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 695 {
 696    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 697    PUSH_DATA (push, 0xff);
 698    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 699    PUSH_DATA (push, 0xff);
 700    PUSH_DATA (push, 0xff);
 701    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 702    PUSH_DATA (push, 0xff);
 703    PUSH_DATA (push, 0xff);
 704    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 705    PUSH_DATA (push, 0x3f);
 706
 707    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 708    PUSH_DATA (push, (3 << 16) | 3);
 709    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 710    PUSH_DATA (push, (2 << 16) | 2);
 711
 712    if (obj_class < GM107_3D_CLASS) {
 713       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 714       PUSH_DATA (push, 0);
 715    }
 716    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 717    PUSH_DATA (push, 0x10);
 718    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 719    PUSH_DATA (push, 0x10);
 720    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 721    PUSH_DATA (push, 0x10);
 722    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 723    PUSH_DATA (push, 0x10);
 724    PUSH_DATA (push, 0x10);
 725    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 726    PUSH_DATA (push, 0x10);
 727    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 728    PUSH_DATA (push, 0xe);
 729
 730    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 731    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 732    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 733    PUSH_DATA (push, 0);
 734    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 735    PUSH_DATA (push, 3);
 736
 737    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 738    PUSH_DATA (push, 0x3fffff);
 739    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 740    PUSH_DATA (push, 1);
 741    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 742    PUSH_DATA (push, 1);
 743
 744    if (obj_class < GM107_3D_CLASS) {
 745       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 746       PUSH_DATA (push, 3);
 747
 748       if (obj_class >= NVE4_3D_CLASS) {
 749          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 750          PUSH_DATA (push, 1);
 751       }
 752    }
 753
 754    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 755     * are supposed to do */
 756 }
 757
 758 static void
 759 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 760 {
 761    struct nvc0_screen *screen = nvc0_screen(pscreen);
 762    struct nouveau_pushbuf *push = screen->base.pushbuf;
 763
 764    /* we need to do it after possible flush in MARK_RING */
 765    *sequence = ++screen->base.fence.sequence;
 766
 767    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 768    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 769    PUSH_DATAh(push, screen->fence.bo->offset);
 770    PUSH_DATA (push, screen->fence.bo->offset);
 771    PUSH_DATA (push, *sequence);
 772    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 773               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 774 }
 775
 776 static u32
 777 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 778 {
 779    struct nvc0_screen *screen = nvc0_screen(pscreen);
 780    return screen->fence.map[0];
 781 }
 782
 783 static int
 784 nvc0_screen_init_compute(struct nvc0_screen *screen)
 785 {
 786    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 787
 788    switch (screen->base.device->chipset & ~0xf) {
 789    case 0xc0:
 790    case 0xd0:
 791       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 792    case 0xe0:
 793    case 0xf0:
 794    case 0x100:
 795    case 0x110:
 796    case 0x120:
 797    case 0x130:
 798       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 799    default:
 800       return -1;
 801    }
 802 }
 803
 804 static int
 805 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 806                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 807 {
 808    struct nouveau_bo *bo = NULL;
 809    int ret;
 810    uint64_t size = (lpos + lneg) * 32 + cstack;
 811
 812    if (size >= (1 << 20)) {
 813       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 814       return -1;
 815    }
 816
 817    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 818    size  = align(size, 0x8000);
 819    size *= screen->mp_count;
 820
 821    size = align(size, 1 << 17);
 822
 823    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 824                         NULL, &bo);
 825    if (ret)
 826       return ret;
 827
 828    /* Make sure that the pushbuf has acquired a reference to the old tls
 829     * segment, as it may have commands that will reference it.
 830     */
 831    if (screen->tls)
 832       PUSH_REFN(screen->base.pushbuf, screen->tls,
 833                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
 834    nouveau_bo_ref(NULL, &screen->tls);
 835    screen->tls = bo;
 836    return 0;
 837 }
 838
 839 int
 840 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 841 {
 842    struct nouveau_pushbuf *push = screen->base.pushbuf;
 843    struct nouveau_bo *bo;
 844    int ret;
 845
 846    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 847                         1 << 17, size, NULL, &bo);
 848    if (ret)
 849       return ret;
 850
 851    /* Make sure that the pushbuf has acquired a reference to the old text
 852     * segment, as it may have commands that will reference it.
 853     */
 854    if (screen->text)
 855       PUSH_REFN(push, screen->text,
 856                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
 857    nouveau_bo_ref(NULL, &screen->text);
 858    screen->text = bo;
 859
 860    nouveau_heap_destroy(&screen->lib_code);
 861    nouveau_heap_destroy(&screen->text_heap);
 862
 863    /* XXX: getting a page fault at the end of the code buffer every few
 864     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 865     */
 866    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 867
 868    /* update the code segment setup */
 869    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 870    PUSH_DATAh(push, screen->text->offset);
 871    PUSH_DATA (push, screen->text->offset);
 872    if (screen->compute) {
 873       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 874       PUSH_DATAh(push, screen->text->offset);
 875       PUSH_DATA (push, screen->text->offset);
 876    }
 877
 878    return 0;
 879 }
 880
 881 void
 882 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
 883                        int stage, int index, int size, uint64_t addr)
 884 {
 885    assert(stage != 5);
 886
 887    struct nouveau_pushbuf *push = screen->base.pushbuf;
 888
 889    if (screen->base.class_3d >= GM107_3D_CLASS) {
 890       struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
 891
 892       // TODO: Better figure out the conditions in which this is needed
 893       bool serialize = binding->addr == addr && binding->size != size;
 894       if (can_serialize)
 895          serialize = serialize && *can_serialize;
 896       if (serialize) {
 897          IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 898          if (can_serialize)
 899             *can_serialize = false;
 900       }
 901
 902       binding->addr = addr;
 903       binding->size = size;
 904    }
 905
 906    if (size >= 0) {
 907       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 908       PUSH_DATA (push, size);
 909       PUSH_DATAh(push, addr);
 910       PUSH_DATA (push, addr);
 911    }
 912    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
 913 }
 914
 915 static const nir_shader_compiler_options nir_options = {
 916    .lower_fdiv = false,
 917    .lower_ffma = false,
 918    .fuse_ffma = false, /* nir doesn't track mad vs fma */
 919    .lower_flrp32 = true,
 920    .lower_flrp64 = true,
 921    .lower_fpow = false,
 922    .lower_fsat = false,
 923    .lower_fsqrt = false, // TODO: only before gm200
 924    .lower_fmod = true,
 925    .lower_bitfield_extract = false,
 926    .lower_bitfield_extract_to_shifts = false,
 927    .lower_bitfield_insert = false,
 928    .lower_bitfield_insert_to_shifts = false,
 929    .lower_bitfield_reverse = false,
 930    .lower_bit_count = false,
 931    .lower_ifind_msb = false,
 932    .lower_find_lsb = false,
 933    .lower_uadd_carry = true, // TODO
 934    .lower_usub_borrow = true, // TODO
 935    .lower_mul_high = false,
 936    .lower_negate = false,
 937    .lower_sub = false, // TODO
 938    .lower_scmp = true, // TODO: not implemented yet
 939    .lower_idiv = true,
 940    .lower_isign = false, // TODO
 941    .fdot_replicates = false, // TODO
 942    .lower_ffloor = false, // TODO
 943    .lower_ffract = true,
 944    .lower_fceil = false, // TODO
 945    .lower_ldexp = true,
 946    .lower_pack_half_2x16 = true,
 947    .lower_pack_unorm_2x16 = true,
 948    .lower_pack_snorm_2x16 = true,
 949    .lower_pack_unorm_4x8 = true,
 950    .lower_pack_snorm_4x8 = true,
 951    .lower_unpack_half_2x16 = true,
 952    .lower_unpack_unorm_2x16 = true,
 953    .lower_unpack_snorm_2x16 = true,
 954    .lower_unpack_unorm_4x8 = true,
 955    .lower_unpack_snorm_4x8 = true,
 956    .lower_extract_byte = true,
 957    .lower_extract_word = true,
 958    .lower_all_io_to_temps = false,
 959    .vertex_id_zero_based = false,
 960    .lower_base_vertex = false,
 961    .lower_helper_invocation = false,
 962    .lower_cs_local_index_from_id = true,
 963    .lower_cs_local_id_from_index = false,
 964    .lower_device_index_to_zero = false, // TODO
 965    .lower_wpos_pntc = false, // TODO
 966    .lower_hadd = true, // TODO
 967    .lower_add_sat = true, // TODO
 968    .use_interpolated_input_intrinsics = true,
 969    .lower_mul_2x32_64 = true, // TODO
 970    .max_unroll_iterations = 32,
 971    .lower_int64_options = nir_lower_divmod64, // TODO
 972    .lower_doubles_options = nir_lower_dmod, // TODO
 973 };
 974
 975 static const void *
 976 nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
 977                                  enum pipe_shader_ir ir,
 978                                  enum pipe_shader_type shader)
 979 {
 980    if (ir == PIPE_SHADER_IR_NIR)
 981       return &nir_options;
 982    return NULL;
 983 }
 984
 985 #define FAIL_SCREEN_INIT(str, err)                    \
 986    do {                                               \
 987       NOUVEAU_ERR(str, err);                          \
 988       goto fail;                                      \
 989    } while(0)
 990
 991 struct nouveau_screen *
 992 nvc0_screen_create(struct nouveau_device *dev)
 993 {
 994    struct nvc0_screen *screen;
 995    struct pipe_screen *pscreen;
 996    struct nouveau_object *chan;
 997    struct nouveau_pushbuf *push;
 998    uint64_t value;
 999    uint32_t obj_class;
1000    uint32_t flags;
1001    int ret;
1002    unsigned i;
1003
1004    switch (dev->chipset & ~0xf) {
1005    case 0xc0:
1006    case 0xd0:
1007    case 0xe0:
1008    case 0xf0:
1009    case 0x100:
1010    case 0x110:
1011    case 0x120:
1012    case 0x130:
1013       break;
1014    default:
1015       return NULL;
1016    }
1017
1018    screen = CALLOC_STRUCT(nvc0_screen);
1019    if (!screen)
1020       return NULL;
1021    pscreen = &screen->base.base;
1022    pscreen->destroy = nvc0_screen_destroy;
1023
1024    ret = nouveau_screen_init(&screen->base, dev);
1025    if (ret)
1026       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
1027    chan = screen->base.channel;
1028    push = screen->base.pushbuf;
1029    push->user_priv = screen;
1030    push->rsvd_kick = 5;
1031
1032    /* TODO: could this be higher on Kepler+? how does reclocking vs no
1033     * reclocking affect performance?
1034     * TODO: could this be higher on Fermi?
1035     */
1036    if (dev->chipset >= 0xe0)
1037       screen->base.transfer_pushbuf_threshold = 1024;
1038
1039    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
1040       PIPE_BIND_SHADER_BUFFER |
1041       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
1042       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
1043    screen->base.sysmem_bindings |=
1044       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
1045
1046    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
1047       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
1048       screen->base.vidmem_bindings = 0;
1049    }
1050
1051    pscreen->context_create = nvc0_create;
1052    pscreen->is_format_supported = nvc0_screen_is_format_supported;
1053    pscreen->get_param = nvc0_screen_get_param;
1054    pscreen->get_shader_param = nvc0_screen_get_shader_param;
1055    pscreen->get_paramf = nvc0_screen_get_paramf;
1056    pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
1057    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
1058    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
1059    /* nir stuff */
1060    pscreen->get_compiler_options = nvc0_screen_get_compiler_options;
1061
1062    nvc0_screen_init_resource_functions(pscreen);
1063
1064    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1065    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1066
1067    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
1068    if (screen->base.drm->version >= 0x01000202)
1069       flags |= NOUVEAU_BO_COHERENT;
1070
1071    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
1072    if (ret)
1073       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
1074    nouveau_bo_map(screen->fence.bo, 0, NULL);
1075    screen->fence.map = screen->fence.bo->map;
1076    screen->base.fence.emit = nvc0_screen_fence_emit;
1077    screen->base.fence.update = nvc0_screen_fence_update;
1078
1079
1080    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
1081                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
1082    if (ret)
1083       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
1084
1085    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
1086    PUSH_DATA (push, screen->nvsw->handle);
1087
1088    switch (dev->chipset & ~0xf) {
1089    case 0x130:
1090    case 0x120:
1091    case 0x110:
1092    case 0x100:
1093    case 0xf0:
1094       obj_class = NVF0_P2MF_CLASS;
1095       break;
1096    case 0xe0:
1097       obj_class = NVE4_P2MF_CLASS;
1098       break;
1099    default:
1100       obj_class = NVC0_M2MF_CLASS;
1101       break;
1102    }
1103    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
1104                             &screen->m2mf);
1105    if (ret)
1106       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
1107
1108    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
1109    PUSH_DATA (push, screen->m2mf->oclass);
1110    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1111       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1112       PUSH_DATA (push, 0xa0b5);
1113    }
1114
1115    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1116                             &screen->eng2d);
1117    if (ret)
1118       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1119
1120    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1121    PUSH_DATA (push, screen->eng2d->oclass);
1122    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1123    PUSH_DATA (push, 0);
1124    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1125    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1126    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1127    PUSH_DATA (push, 0);
1128    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1129    PUSH_DATA (push, 0);
1130    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1131    PUSH_DATA (push, 0x3f);
1132    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1133    PUSH_DATA (push, 1);
1134    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1135    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1136
1137    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1138    PUSH_DATAh(push, screen->fence.bo->offset + 16);
1139    PUSH_DATA (push, screen->fence.bo->offset + 16);
1140
1141    switch (dev->chipset & ~0xf) {
1142    case 0x130:
1143       switch (dev->chipset) {
1144       case 0x130:
1145       case 0x13b:
1146          obj_class = GP100_3D_CLASS;
1147          break;
1148       default:
1149          obj_class = GP102_3D_CLASS;
1150          break;
1151       }
1152       break;
1153    case 0x120:
1154       obj_class = GM200_3D_CLASS;
1155       break;
1156    case 0x110:
1157       obj_class = GM107_3D_CLASS;
1158       break;
1159    case 0x100:
1160    case 0xf0:
1161       obj_class = NVF0_3D_CLASS;
1162       break;
1163    case 0xe0:
1164       switch (dev->chipset) {
1165       case 0xea:
1166          obj_class = NVEA_3D_CLASS;
1167          break;
1168       default:
1169          obj_class = NVE4_3D_CLASS;
1170          break;
1171       }
1172       break;
1173    case 0xd0:
1174       obj_class = NVC8_3D_CLASS;
1175       break;
1176    case 0xc0:
1177    default:
1178       switch (dev->chipset) {
1179       case 0xc8:
1180          obj_class = NVC8_3D_CLASS;
1181          break;
1182       case 0xc1:
1183          obj_class = NVC1_3D_CLASS;
1184          break;
1185       default:
1186          obj_class = NVC0_3D_CLASS;
1187          break;
1188       }
1189       break;
1190    }
1191    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1192                             &screen->eng3d);
1193    if (ret)
1194       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1195    screen->base.class_3d = obj_class;
1196
1197    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1198    PUSH_DATA (push, screen->eng3d->oclass);
1199
1200    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1201    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1202
1203    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1204       /* kill shaders after about 1 second (at 100 MHz) */
1205       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1206       PUSH_DATA (push, 0x17);
1207    }
1208
1209    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1210                     screen->base.drm->version >= 0x01000101);
1211    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1212    for (i = 0; i < 8; ++i)
1213       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1214
1215    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1216    PUSH_DATA (push, 1);
1217
1218    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1219    PUSH_DATA (push, 0);
1220    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1221    PUSH_DATA (push, 0);
1222    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1223    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1224    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1225    PUSH_DATA (push, 0);
1226    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1227    PUSH_DATA (push, 1);
1228    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1229    PUSH_DATA (push, 1);
1230    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1231    PUSH_DATA (push, 1);
1232    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1233    PUSH_DATA (push, 0);
1234    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1235    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1236    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1237       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1238    } else {
1239       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1240       PUSH_DATA (push, 15);
1241    }
1242    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1243    PUSH_DATA (push, 8); /* 128 */
1244    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1245    PUSH_DATA (push, 1);
1246    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1247       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1248       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1249    }
1250
1251    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1252
1253    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1254    if (ret)
1255       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1256
1257    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1258    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1259                         &screen->uniform_bo);
1260    if (ret)
1261       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1262
1263    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1264
1265    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1266    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1267    PUSH_DATA (push, 256);
1268    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1269    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1270    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1271    PUSH_DATA (push, 0);
1272    PUSH_DATAf(push, 0.0f);
1273    PUSH_DATAf(push, 0.0f);
1274    PUSH_DATAf(push, 0.0f);
1275    PUSH_DATAf(push, 0.0f);
1276    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1277    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1278    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1279
1280    if (screen->base.drm->version >= 0x01000101) {
1281       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1282       if (ret)
1283          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1284    } else {
1285       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1286          value = (8 << 8) | 4;
1287       else
1288          value = (16 << 8) | 4;
1289    }
1290    screen->gpc_count = value & 0x000000ff;
1291    screen->mp_count = value >> 8;
1292    screen->mp_count_compute = screen->mp_count;
1293
1294    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1295    if (ret)
1296       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1297
1298    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1299    PUSH_DATAh(push, screen->tls->offset);
1300    PUSH_DATA (push, screen->tls->offset);
1301    PUSH_DATA (push, screen->tls->size >> 32);
1302    PUSH_DATA (push, screen->tls->size);
1303    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1304    PUSH_DATA (push, 0);
1305    /* Reduce likelihood of collision with real buffers by placing the hole at
1306     * the top of the 4G area. This will have to be dealt with for real
1307     * eventually by blocking off that area from the VM.
1308     */
1309    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1310    PUSH_DATA (push, 0xff << 24);
1311
1312    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1313       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1314                            &screen->poly_cache);
1315       if (ret)
1316          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1317
1318       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1319       PUSH_DATAh(push, screen->poly_cache->offset);
1320       PUSH_DATA (push, screen->poly_cache->offset);
1321       PUSH_DATA (push, 3);
1322    }
1323
1324    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1325                         &screen->txc);
1326    if (ret)
1327       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1328
1329    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1330    PUSH_DATAh(push, screen->txc->offset);
1331    PUSH_DATA (push, screen->txc->offset);
1332    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1333    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1334       screen->tic.maxwell = true;
1335       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1336          screen->tic.maxwell =
1337             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1338          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1339       }
1340    }
1341
1342    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1343    PUSH_DATAh(push, screen->txc->offset + 65536);
1344    PUSH_DATA (push, screen->txc->offset + 65536);
1345    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1346
1347    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1348    PUSH_DATA (push, 0);
1349    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1350    PUSH_DATA (push, 0);
1351    PUSH_DATA (push, 0);
1352    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1353    PUSH_DATA (push, 0x3f);
1354
1355    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1356    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1357    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1358    for (i = 0; i < 8 * 2; ++i)
1359       PUSH_DATA(push, 0);
1360    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1361    PUSH_DATA (push, 0);
1362    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1363    PUSH_DATA (push, 0);
1364
1365    /* neither scissors, viewport nor stencil mask should affect clears */
1366    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1367    PUSH_DATA (push, 0);
1368
1369    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1370    PUSH_DATA (push, 1);
1371    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1372       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1373       PUSH_DATAf(push, 0.0f);
1374       PUSH_DATAf(push, 1.0f);
1375    }
1376    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1377    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1378
1379    /* We use scissors instead of exact view volume clipping,
1380     * so they're always enabled.
1381     */
1382    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1383       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1384       PUSH_DATA (push, 1);
1385       PUSH_DATA (push, 16384 << 16);
1386       PUSH_DATA (push, 16384 << 16);
1387    }
1388
1389 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1390
1391    i = 0;
1392    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1393    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1394    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1395    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1396    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1397    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1398    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1399    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1400    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1401    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1402    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1403    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1404    MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1405    MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
1406    MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
1407    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1408
1409    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1410    PUSH_DATA (push, 1);
1411    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1412    PUSH_DATA (push, 1);
1413    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1414    PUSH_DATA (push, 0x40);
1415    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1416    PUSH_DATA (push, 0);
1417    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1418    PUSH_DATA (push, 0x30);
1419    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1420    PUSH_DATA (push, 3);
1421    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1422    PUSH_DATA (push, 0x20);
1423    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1424    PUSH_DATA (push, 0x00);
1425    screen->save_state.patch_vertices = 3;
1426
1427    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1428    PUSH_DATA (push, 0);
1429    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1430    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1431
1432    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1433
1434    if (nvc0_screen_init_compute(screen))
1435       goto fail;
1436
1437    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1438    for (i = 0; i < 5; ++i) {
1439       unsigned j = 0;
1440       for (j = 0; j < 16; j++)
1441          screen->cb_bindings[i][j].size = -1;
1442
1443       /* TIC and TSC entries for each unit (nve4+ only) */
1444       /* auxiliary constants (6 user clip planes, base instance id) */
1445       nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1446                              screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1447       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1448          unsigned j;
1449          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1450          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1451          for (j = 0; j < 8; ++j)
1452             PUSH_DATA(push, j);
1453       } else {
1454          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1455          PUSH_DATA (push, 0x54);
1456       }
1457
1458       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1459       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1460       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1461       PUSH_DATA (push, 0); /* 0 */
1462       PUSH_DATA (push, 0);
1463       PUSH_DATA (push, 1); /* 1 */
1464       PUSH_DATA (push, 0);
1465       PUSH_DATA (push, 0); /* 2 */
1466       PUSH_DATA (push, 1);
1467       PUSH_DATA (push, 1); /* 3 */
1468       PUSH_DATA (push, 1);
1469       PUSH_DATA (push, 2); /* 4 */
1470       PUSH_DATA (push, 0);
1471       PUSH_DATA (push, 3); /* 5 */
1472       PUSH_DATA (push, 0);
1473       PUSH_DATA (push, 2); /* 6 */
1474       PUSH_DATA (push, 1);
1475       PUSH_DATA (push, 3); /* 7 */
1476       PUSH_DATA (push, 1);
1477    }
1478    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1479    PUSH_DATA (push, 0);
1480
1481    PUSH_KICK (push);
1482
1483    screen->tic.entries = CALLOC(
1484          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1485          sizeof(void *));
1486    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1487    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1488
1489    if (!nvc0_blitter_create(screen))
1490       goto fail;
1491
1492    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1493
1494    return &screen->base;
1495
1496 fail:
1497    screen->base.base.context_create = NULL;
1498    return &screen->base;
1499 }
1500
1501 int
1502 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1503 {
1504    int i = screen->tic.next;
1505
1506    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1507       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1508
1509    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1510
1511    if (screen->tic.entries[i])
1512       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1513
1514    screen->tic.entries[i] = entry;
1515    return i;
1516 }
1517
1518 int
1519 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1520 {
1521    int i = screen->tsc.next;
1522
1523    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1524       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1525
1526    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1527
1528    if (screen->tsc.entries[i])
1529       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1530
1531    screen->tsc.entries[i] = entry;
1532    return i;
1533 }