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nvc0: add GK20A 3D class
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/mme/com9097.mme.h"
36
37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
39 #endif
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 if (sample_count > 8)
49 return FALSE;
50 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
51 return FALSE;
52
53 if (!util_format_is_supported(format, bindings))
54 return FALSE;
55
56 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
57 if (util_format_get_blocksizebits(format) == 3 * 32)
58 return FALSE;
59
60 /* transfers & shared are always supported */
61 bindings &= ~(PIPE_BIND_TRANSFER_READ |
62 PIPE_BIND_TRANSFER_WRITE |
63 PIPE_BIND_SHARED);
64
65 return (nvc0_format_table[format].usage & bindings) == bindings;
66 }
67
68 static int
69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
70 {
71 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
72
73 switch (param) {
74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
76 return 15;
77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
78 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
80 return 2048;
81 case PIPE_CAP_MIN_TEXEL_OFFSET:
82 return -8;
83 case PIPE_CAP_MAX_TEXEL_OFFSET:
84 return 7;
85 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
86 return -32;
87 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
88 return 31;
89 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
90 case PIPE_CAP_TEXTURE_SWIZZLE:
91 case PIPE_CAP_TEXTURE_SHADOW_MAP:
92 case PIPE_CAP_NPOT_TEXTURES:
93 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
94 case PIPE_CAP_ANISOTROPIC_FILTER:
95 case PIPE_CAP_SEAMLESS_CUBE_MAP:
96 case PIPE_CAP_CUBE_MAP_ARRAY:
97 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
98 case PIPE_CAP_TEXTURE_MULTISAMPLE:
99 return 1;
100 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
101 return 65536;
102 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
103 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
104 case PIPE_CAP_TWO_SIDED_STENCIL:
105 case PIPE_CAP_DEPTH_CLIP_DISABLE:
106 case PIPE_CAP_POINT_SPRITE:
107 case PIPE_CAP_TGSI_TEXCOORD:
108 return 1;
109 case PIPE_CAP_SM3:
110 return 1;
111 case PIPE_CAP_GLSL_FEATURE_LEVEL:
112 return 330;
113 case PIPE_CAP_MAX_RENDER_TARGETS:
114 return 8;
115 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
116 return 1;
117 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
118 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
119 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
120 return 1;
121 case PIPE_CAP_QUERY_TIMESTAMP:
122 case PIPE_CAP_QUERY_TIME_ELAPSED:
123 case PIPE_CAP_OCCLUSION_QUERY:
124 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
125 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
126 return 1;
127 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
128 return 4;
129 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
130 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
131 return 128;
132 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
133 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
134 return 1024;
135 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
136 case PIPE_CAP_INDEP_BLEND_ENABLE:
137 case PIPE_CAP_INDEP_BLEND_FUNC:
138 return 1;
139 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
140 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
141 return 1;
142 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
143 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
144 return 0;
145 case PIPE_CAP_SHADER_STENCIL_EXPORT:
146 return 0;
147 case PIPE_CAP_PRIMITIVE_RESTART:
148 case PIPE_CAP_TGSI_INSTANCEID:
149 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
150 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
151 case PIPE_CAP_CONDITIONAL_RENDER:
152 case PIPE_CAP_TEXTURE_BARRIER:
153 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
154 case PIPE_CAP_START_INSTANCE:
155 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
156 return 1;
157 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
158 return 0; /* state trackers will know better */
159 case PIPE_CAP_USER_CONSTANT_BUFFERS:
160 case PIPE_CAP_USER_INDEX_BUFFERS:
161 case PIPE_CAP_USER_VERTEX_BUFFERS:
162 return 1;
163 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
164 return 256;
165 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
166 return 1; /* 256 for binding as RT, but that's not possible in GL */
167 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
168 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
169 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
170 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
171 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
172 return 0;
173 case PIPE_CAP_COMPUTE:
174 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
175 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
176 return 1;
177 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
178 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
179 case PIPE_CAP_ENDIANNESS:
180 return PIPE_ENDIAN_LITTLE;
181 case PIPE_CAP_TGSI_VS_LAYER:
182 case PIPE_CAP_TEXTURE_GATHER_SM5:
183 case PIPE_CAP_FAKE_SW_MSAA:
184 return 0;
185 case PIPE_CAP_MAX_VIEWPORTS:
186 return 1;
187 case PIPE_CAP_TEXTURE_QUERY_LOD:
188 case PIPE_CAP_SAMPLE_SHADING:
189 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
190 return 1;
191 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
192 return 4;
193 default:
194 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
195 return 0;
196 }
197 }
198
199 static int
200 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
201 enum pipe_shader_cap param)
202 {
203 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
204
205 switch (shader) {
206 case PIPE_SHADER_VERTEX:
207 /*
208 case PIPE_SHADER_TESSELLATION_CONTROL:
209 case PIPE_SHADER_TESSELLATION_EVALUATION:
210 */
211 case PIPE_SHADER_GEOMETRY:
212 case PIPE_SHADER_FRAGMENT:
213 break;
214 case PIPE_SHADER_COMPUTE:
215 if (class_3d < NVE4_3D_CLASS)
216 return 0;
217 break;
218 default:
219 return 0;
220 }
221
222 switch (param) {
223 case PIPE_SHADER_CAP_PREFERRED_IR:
224 return PIPE_SHADER_IR_TGSI;
225 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
226 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
227 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
228 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
229 return 16384;
230 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
231 return 16;
232 case PIPE_SHADER_CAP_MAX_INPUTS:
233 if (shader == PIPE_SHADER_VERTEX)
234 return 32;
235 /* NOTE: These only count our slots for GENERIC varyings.
236 * The address space may be larger, but the actual hard limit seems to be
237 * less than what the address space layout permits, so don't add TEXCOORD,
238 * COLOR, etc. here.
239 */
240 if (shader == PIPE_SHADER_FRAGMENT)
241 return 0x1f0 / 16;
242 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
243 * and excludes 0x60 per-patch inputs.
244 */
245 return 0x200 / 16;
246 case PIPE_SHADER_CAP_MAX_CONSTS:
247 return 65536 / 16;
248 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
249 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
250 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
251 return NVC0_MAX_PIPE_CONSTBUFS;
252 case PIPE_SHADER_CAP_MAX_ADDRS:
253 return 1;
254 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
255 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
256 return shader != PIPE_SHADER_FRAGMENT;
257 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
258 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
259 return 1;
260 case PIPE_SHADER_CAP_MAX_PREDS:
261 return 0;
262 case PIPE_SHADER_CAP_MAX_TEMPS:
263 return NVC0_CAP_MAX_PROGRAM_TEMPS;
264 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
265 return 1;
266 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
267 return 0;
268 case PIPE_SHADER_CAP_SUBROUTINES:
269 return 1;
270 case PIPE_SHADER_CAP_INTEGERS:
271 return 1;
272 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
273 return 16; /* would be 32 in linked (OpenGL-style) mode */
274 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
275 return 16; /* XXX not sure if more are really safe */
276 default:
277 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
278 return 0;
279 }
280 }
281
282 static float
283 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
284 {
285 switch (param) {
286 case PIPE_CAPF_MAX_LINE_WIDTH:
287 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
288 return 10.0f;
289 case PIPE_CAPF_MAX_POINT_WIDTH:
290 return 63.0f;
291 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
292 return 63.375f;
293 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
294 return 16.0f;
295 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
296 return 15.0f;
297 case PIPE_CAPF_GUARD_BAND_LEFT:
298 case PIPE_CAPF_GUARD_BAND_TOP:
299 return 0.0f;
300 case PIPE_CAPF_GUARD_BAND_RIGHT:
301 case PIPE_CAPF_GUARD_BAND_BOTTOM:
302 return 0.0f; /* that or infinity */
303 }
304
305 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
306 return 0.0f;
307 }
308
309 static int
310 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
311 enum pipe_compute_cap param, void *data)
312 {
313 uint64_t *data64 = (uint64_t *)data;
314 const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
315
316 switch (param) {
317 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
318 data64[0] = 3;
319 return 8;
320 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
321 data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
322 data64[1] = 65535;
323 data64[2] = 65535;
324 return 24;
325 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
326 data64[0] = 1024;
327 data64[1] = 1024;
328 data64[2] = 64;
329 return 24;
330 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
331 data64[0] = 1024;
332 return 8;
333 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
334 data64[0] = (uint64_t)1 << 40;
335 return 8;
336 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
337 data64[0] = 48 << 10;
338 return 8;
339 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
340 data64[0] = 512 << 10;
341 return 8;
342 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
343 data64[0] = 4096;
344 return 8;
345 default:
346 return 0;
347 }
348 }
349
350 static void
351 nvc0_screen_destroy(struct pipe_screen *pscreen)
352 {
353 struct nvc0_screen *screen = nvc0_screen(pscreen);
354
355 if (!nouveau_drm_screen_unref(&screen->base))
356 return;
357
358 if (screen->base.fence.current) {
359 struct nouveau_fence *current = NULL;
360
361 /* nouveau_fence_wait will create a new current fence, so wait on the
362 * _current_ one, and remove both.
363 */
364 nouveau_fence_ref(screen->base.fence.current, &current);
365 nouveau_fence_wait(current);
366 nouveau_fence_ref(NULL, &current);
367 nouveau_fence_ref(NULL, &screen->base.fence.current);
368 }
369 if (screen->base.pushbuf)
370 screen->base.pushbuf->user_priv = NULL;
371
372 if (screen->blitter)
373 nvc0_blitter_destroy(screen);
374 if (screen->pm.prog) {
375 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
376 nvc0_program_destroy(NULL, screen->pm.prog);
377 }
378
379 nouveau_bo_ref(NULL, &screen->text);
380 nouveau_bo_ref(NULL, &screen->uniform_bo);
381 nouveau_bo_ref(NULL, &screen->tls);
382 nouveau_bo_ref(NULL, &screen->txc);
383 nouveau_bo_ref(NULL, &screen->fence.bo);
384 nouveau_bo_ref(NULL, &screen->poly_cache);
385 nouveau_bo_ref(NULL, &screen->parm);
386
387 nouveau_heap_destroy(&screen->lib_code);
388 nouveau_heap_destroy(&screen->text_heap);
389
390 FREE(screen->tic.entries);
391
392 nouveau_mm_destroy(screen->mm_VRAM_fe0);
393
394 nouveau_object_del(&screen->eng3d);
395 nouveau_object_del(&screen->eng2d);
396 nouveau_object_del(&screen->m2mf);
397 nouveau_object_del(&screen->compute);
398 nouveau_object_del(&screen->nvsw);
399
400 nouveau_screen_fini(&screen->base);
401
402 FREE(screen);
403 }
404
405 static int
406 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
407 unsigned size, const uint32_t *data)
408 {
409 struct nouveau_pushbuf *push = screen->base.pushbuf;
410
411 size /= 4;
412
413 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
414 PUSH_DATA (push, (m - 0x3800) / 8);
415 PUSH_DATA (push, pos);
416 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
417 PUSH_DATA (push, pos);
418 PUSH_DATAp(push, data, size);
419
420 return pos + size;
421 }
422
423 static void
424 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
425 {
426 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
427 PUSH_DATA (push, 0xff);
428 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
429 PUSH_DATA (push, 0xff);
430 PUSH_DATA (push, 0xff);
431 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
432 PUSH_DATA (push, 0xff);
433 PUSH_DATA (push, 0xff);
434 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
435 PUSH_DATA (push, 0x3f);
436
437 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
438 PUSH_DATA (push, (3 << 16) | 3);
439 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
440 PUSH_DATA (push, (2 << 16) | 2);
441 BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
442 PUSH_DATA (push, 1);
443
444 if (obj_class < GM107_3D_CLASS) {
445 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
446 PUSH_DATA (push, 0);
447 }
448 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
449 PUSH_DATA (push, 0x10);
450 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
451 PUSH_DATA (push, 0x10);
452 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
453 PUSH_DATA (push, 0x10);
454 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
455 PUSH_DATA (push, 0x10);
456 PUSH_DATA (push, 0x10);
457 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
458 PUSH_DATA (push, 0x10);
459 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
460 PUSH_DATA (push, 0xe);
461
462 BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
463 PUSH_DATA (push, 1 << 12);
464 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
465 PUSH_DATA (push, 0);
466 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
467 PUSH_DATA (push, 3);
468
469 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
470 PUSH_DATA (push, 0x3fffff);
471 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
472 PUSH_DATA (push, 1);
473 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
474 PUSH_DATA (push, 1);
475
476 if (obj_class < GM107_3D_CLASS) {
477 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
478 PUSH_DATA (push, 3);
479
480 if (obj_class >= NVE4_3D_CLASS) {
481 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
482 PUSH_DATA (push, 1);
483 }
484 }
485
486 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
487 * are supposed to do */
488 }
489
490 static void
491 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
492 {
493 struct nvc0_screen *screen = nvc0_screen(pscreen);
494 struct nouveau_pushbuf *push = screen->base.pushbuf;
495
496 /* we need to do it after possible flush in MARK_RING */
497 *sequence = ++screen->base.fence.sequence;
498
499 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
500 PUSH_DATAh(push, screen->fence.bo->offset);
501 PUSH_DATA (push, screen->fence.bo->offset);
502 PUSH_DATA (push, *sequence);
503 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
504 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
505 }
506
507 static u32
508 nvc0_screen_fence_update(struct pipe_screen *pscreen)
509 {
510 struct nvc0_screen *screen = nvc0_screen(pscreen);
511 return screen->fence.map[0];
512 }
513
514 static int
515 nvc0_screen_init_compute(struct nvc0_screen *screen)
516 {
517 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
518
519 switch (screen->base.device->chipset & ~0xf) {
520 case 0xc0:
521 case 0xd0:
522 /* Using COMPUTE has weird effects on 3D state, we need to
523 * investigate this further before enabling it by default.
524 */
525 if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
526 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
527 return 0;
528 case 0xe0:
529 case 0xf0:
530 case 0x100:
531 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
532 case 0x110:
533 return 0;
534 default:
535 return -1;
536 }
537 }
538
539 boolean
540 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
541 uint32_t lpos, uint32_t lneg, uint32_t cstack)
542 {
543 struct nouveau_bo *bo = NULL;
544 int ret;
545 uint64_t size = (lpos + lneg) * 32 + cstack;
546
547 if (size >= (1 << 20)) {
548 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
549 return FALSE;
550 }
551
552 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
553 size = align(size, 0x8000);
554 size *= screen->mp_count;
555
556 size = align(size, 1 << 17);
557
558 ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
559 NULL, &bo);
560 if (ret) {
561 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
562 return FALSE;
563 }
564 nouveau_bo_ref(NULL, &screen->tls);
565 screen->tls = bo;
566 return TRUE;
567 }
568
569 #define FAIL_SCREEN_INIT(str, err) \
570 do { \
571 NOUVEAU_ERR(str, err); \
572 nvc0_screen_destroy(pscreen); \
573 return NULL; \
574 } while(0)
575
576 struct pipe_screen *
577 nvc0_screen_create(struct nouveau_device *dev)
578 {
579 struct nvc0_screen *screen;
580 struct pipe_screen *pscreen;
581 struct nouveau_object *chan;
582 struct nouveau_pushbuf *push;
583 uint64_t value;
584 uint32_t obj_class;
585 int ret;
586 unsigned i;
587 union nouveau_bo_config mm_config;
588
589 switch (dev->chipset & ~0xf) {
590 case 0xc0:
591 case 0xd0:
592 case 0xe0:
593 case 0xf0:
594 case 0x100:
595 case 0x110:
596 break;
597 default:
598 return NULL;
599 }
600
601 screen = CALLOC_STRUCT(nvc0_screen);
602 if (!screen)
603 return NULL;
604 pscreen = &screen->base.base;
605
606 ret = nouveau_screen_init(&screen->base, dev);
607 if (ret) {
608 nvc0_screen_destroy(pscreen);
609 return NULL;
610 }
611 chan = screen->base.channel;
612 push = screen->base.pushbuf;
613 push->user_priv = screen;
614 push->rsvd_kick = 5;
615
616 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
617 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
618 screen->base.sysmem_bindings |=
619 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
620
621 pscreen->destroy = nvc0_screen_destroy;
622 pscreen->context_create = nvc0_create;
623 pscreen->is_format_supported = nvc0_screen_is_format_supported;
624 pscreen->get_param = nvc0_screen_get_param;
625 pscreen->get_shader_param = nvc0_screen_get_shader_param;
626 pscreen->get_paramf = nvc0_screen_get_paramf;
627 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
628
629 nvc0_screen_init_resource_functions(pscreen);
630
631 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
632 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
633
634 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
635 &screen->fence.bo);
636 if (ret)
637 goto fail;
638 nouveau_bo_map(screen->fence.bo, 0, NULL);
639 screen->fence.map = screen->fence.bo->map;
640 screen->base.fence.emit = nvc0_screen_fence_emit;
641 screen->base.fence.update = nvc0_screen_fence_update;
642
643
644 ret = nouveau_object_new(chan,
645 (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
646 NULL, 0, &screen->nvsw);
647 if (ret)
648 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
649
650
651 switch (dev->chipset & ~0xf) {
652 case 0x110:
653 case 0x100:
654 case 0xf0:
655 obj_class = NVF0_P2MF_CLASS;
656 break;
657 case 0xe0:
658 obj_class = NVE4_P2MF_CLASS;
659 break;
660 default:
661 obj_class = NVC0_M2MF_CLASS;
662 break;
663 }
664 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
665 &screen->m2mf);
666 if (ret)
667 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
668
669 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
670 PUSH_DATA (push, screen->m2mf->oclass);
671 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
672 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
673 PUSH_DATA (push, 0xa0b5);
674 }
675
676 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
677 &screen->eng2d);
678 if (ret)
679 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
680
681 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
682 PUSH_DATA (push, screen->eng2d->oclass);
683 BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
684 PUSH_DATA (push, 0);
685 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
686 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
687 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
688 PUSH_DATA (push, 0);
689 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
690 PUSH_DATA (push, 0);
691 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
692 PUSH_DATA (push, 0x3f);
693 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
694 PUSH_DATA (push, 1);
695 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
696 PUSH_DATA (push, NVC0_2D_COND_MODE_ALWAYS);
697
698 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
699 PUSH_DATAh(push, screen->fence.bo->offset + 16);
700 PUSH_DATA (push, screen->fence.bo->offset + 16);
701
702 switch (dev->chipset & ~0xf) {
703 case 0x110:
704 obj_class = GM107_3D_CLASS;
705 break;
706 case 0x100:
707 case 0xf0:
708 obj_class = NVF0_3D_CLASS;
709 break;
710 case 0xe0:
711 switch (dev->chipset) {
712 case 0xea:
713 obj_class = NVEA_3D_CLASS;
714 break;
715 default:
716 obj_class = NVE4_3D_CLASS;
717 break;
718 }
719 break;
720 case 0xd0:
721 obj_class = NVC8_3D_CLASS;
722 break;
723 case 0xc0:
724 default:
725 switch (dev->chipset) {
726 case 0xc8:
727 obj_class = NVC8_3D_CLASS;
728 break;
729 case 0xc1:
730 obj_class = NVC1_3D_CLASS;
731 break;
732 default:
733 obj_class = NVC0_3D_CLASS;
734 break;
735 }
736 break;
737 }
738 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
739 &screen->eng3d);
740 if (ret)
741 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
742 screen->base.class_3d = obj_class;
743
744 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
745 PUSH_DATA (push, screen->eng3d->oclass);
746
747 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
748 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
749
750 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
751 /* kill shaders after about 1 second (at 100 MHz) */
752 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
753 PUSH_DATA (push, 0x17);
754 }
755
756 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
757 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
758 for (i = 0; i < 8; ++i)
759 PUSH_DATA(push, dev->drm_version >= 0x01000101);
760
761 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
762 PUSH_DATA (push, 1);
763
764 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
765 PUSH_DATA (push, 0);
766 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
767 PUSH_DATA (push, 0);
768 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
769 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
770 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
771 PUSH_DATA (push, 0);
772 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
773 PUSH_DATA (push, 1);
774 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
775 PUSH_DATA (push, 0);
776 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
777 PUSH_DATA (push, 1);
778 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
779 PUSH_DATA (push, 0);
780 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
781 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
782 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
783 } else {
784 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
785 PUSH_DATA (push, 15);
786 }
787 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
788 PUSH_DATA (push, 8); /* 128 */
789 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
790 PUSH_DATA (push, 1);
791 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
792 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
793 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
794 }
795
796 nvc0_magic_3d_init(push, screen->eng3d->oclass);
797
798 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
799 &screen->text);
800 if (ret)
801 goto fail;
802
803 /* XXX: getting a page fault at the end of the code buffer every few
804 * launches, don't use the last 256 bytes to work around them - prefetch ?
805 */
806 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
807
808 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
809 &screen->uniform_bo);
810 if (ret)
811 goto fail;
812
813 PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
814
815 for (i = 0; i < 5; ++i) {
816 /* TIC and TSC entries for each unit (nve4+ only) */
817 /* auxiliary constants (6 user clip planes, base instance id) */
818 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
819 PUSH_DATA (push, 512);
820 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
821 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
822 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
823 PUSH_DATA (push, (15 << 4) | 1);
824 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
825 unsigned j;
826 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
827 PUSH_DATA (push, 0);
828 for (j = 0; j < 8; ++j)
829 PUSH_DATA(push, j);
830 } else {
831 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
832 PUSH_DATA (push, 0x54);
833 }
834 }
835 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
836 PUSH_DATA (push, 0);
837
838 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
839 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
840 PUSH_DATA (push, 256);
841 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
842 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
843 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
844 PUSH_DATA (push, 0);
845 PUSH_DATAf(push, 0.0f);
846 PUSH_DATAf(push, 0.0f);
847 PUSH_DATAf(push, 0.0f);
848 PUSH_DATAf(push, 0.0f);
849 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
850 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
851 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
852
853 if (dev->drm_version >= 0x01000101) {
854 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
855 if (ret) {
856 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
857 goto fail;
858 }
859 } else {
860 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
861 value = (8 << 8) | 4;
862 else
863 value = (16 << 8) | 4;
864 }
865 screen->mp_count = value >> 8;
866 screen->mp_count_compute = screen->mp_count;
867
868 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
869
870 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
871 PUSH_DATAh(push, screen->text->offset);
872 PUSH_DATA (push, screen->text->offset);
873 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
874 PUSH_DATAh(push, screen->tls->offset);
875 PUSH_DATA (push, screen->tls->offset);
876 PUSH_DATA (push, screen->tls->size >> 32);
877 PUSH_DATA (push, screen->tls->size);
878 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
879 PUSH_DATA (push, 0);
880 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
881 PUSH_DATA (push, 0);
882
883 if (screen->eng3d->oclass < GM107_3D_CLASS) {
884 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
885 &screen->poly_cache);
886 if (ret)
887 goto fail;
888
889 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
890 PUSH_DATAh(push, screen->poly_cache->offset);
891 PUSH_DATA (push, screen->poly_cache->offset);
892 PUSH_DATA (push, 3);
893 }
894
895 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
896 &screen->txc);
897 if (ret)
898 goto fail;
899
900 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
901 PUSH_DATAh(push, screen->txc->offset);
902 PUSH_DATA (push, screen->txc->offset);
903 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
904
905 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
906 PUSH_DATAh(push, screen->txc->offset + 65536);
907 PUSH_DATA (push, screen->txc->offset + 65536);
908 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
909
910 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
911 PUSH_DATA (push, 0);
912 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
913 PUSH_DATA (push, 0);
914 PUSH_DATA (push, 0);
915 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
916 PUSH_DATA (push, 0x3f);
917
918 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
919 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
920 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
921 for (i = 0; i < 8 * 2; ++i)
922 PUSH_DATA(push, 0);
923 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
924 PUSH_DATA (push, 0);
925 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
926 PUSH_DATA (push, 0);
927
928 /* neither scissors, viewport nor stencil mask should affect clears */
929 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
930 PUSH_DATA (push, 0);
931
932 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
933 PUSH_DATA (push, 1);
934 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
935 PUSH_DATAf(push, 0.0f);
936 PUSH_DATAf(push, 1.0f);
937 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
938 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
939
940 /* We use scissors instead of exact view volume clipping,
941 * so they're always enabled.
942 */
943 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
944 PUSH_DATA (push, 1);
945 PUSH_DATA (push, 8192 << 16);
946 PUSH_DATA (push, 8192 << 16);
947
948 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
949
950 i = 0;
951 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
952 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
953 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
954 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
955 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
956 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
957 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
958
959 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
960 PUSH_DATA (push, 1);
961 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
962 PUSH_DATA (push, 1);
963 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
964 PUSH_DATA (push, 0x40);
965 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
966 PUSH_DATA (push, 0);
967 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
968 PUSH_DATA (push, 0x30);
969 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
970 PUSH_DATA (push, 3);
971 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
972 PUSH_DATA (push, 0x20);
973 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
974 PUSH_DATA (push, 0x00);
975
976 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
977 PUSH_DATA (push, 0);
978 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
979 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
980
981 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
982
983 if (nvc0_screen_init_compute(screen))
984 goto fail;
985
986 PUSH_KICK (push);
987
988 screen->tic.entries = CALLOC(4096, sizeof(void *));
989 screen->tsc.entries = screen->tic.entries + 2048;
990
991 mm_config.nvc0.tile_mode = 0;
992 mm_config.nvc0.memtype = 0xfe0;
993 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
994
995 if (!nvc0_blitter_create(screen))
996 goto fail;
997
998 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
999
1000 return pscreen;
1001
1002 fail:
1003 nvc0_screen_destroy(pscreen);
1004 return NULL;
1005 }
1006
1007 int
1008 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1009 {
1010 int i = screen->tic.next;
1011
1012 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1013 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1014
1015 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1016
1017 if (screen->tic.entries[i])
1018 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1019
1020 screen->tic.entries[i] = entry;
1021 return i;
1022 }
1023
1024 int
1025 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1026 {
1027 int i = screen->tsc.next;
1028
1029 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1030 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1031
1032 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1033
1034 if (screen->tsc.entries[i])
1035 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1036
1037 screen->tsc.entries[i] = entry;
1038 return i;
1039 }