projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
nv50,nvc0: enable/disable seamless cubemap texturing as requested
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 if (sample_count > 8)
48 return false;
49 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
50 return false;
51
52 if (!util_format_is_supported(format, bindings))
53 return false;
54
55 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
56 if (util_format_get_blocksizebits(format) == 3 * 32)
57 return false;
58
59 /* transfers & shared are always supported */
60 bindings &= ~(PIPE_BIND_TRANSFER_READ |
61 PIPE_BIND_TRANSFER_WRITE |
62 PIPE_BIND_SHARED);
63
64 return (( nvc0_format_table[format].usage |
65 nvc0_vertex_format[format].usage) & bindings) == bindings;
66 }
67
68 static int
69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
70 {
71 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
72 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
73
74 switch (param) {
75 /* non-boolean caps */
76 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
77 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
78 return 15;
79 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
80 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
81 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
82 return 2048;
83 case PIPE_CAP_MIN_TEXEL_OFFSET:
84 return -8;
85 case PIPE_CAP_MAX_TEXEL_OFFSET:
86 return 7;
87 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
88 return -32;
89 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
90 return 31;
91 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
92 return 128 * 1024 * 1024;
93 case PIPE_CAP_GLSL_FEATURE_LEVEL:
94 return 410;
95 case PIPE_CAP_MAX_RENDER_TARGETS:
96 return 8;
97 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
98 return 1;
99 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
100 return 4;
101 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
102 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
103 return 128;
104 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
105 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
106 return 1024;
107 case PIPE_CAP_MAX_VERTEX_STREAMS:
108 return 4;
109 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
110 return 2048;
111 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
112 return 256;
113 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
114 return 1; /* 256 for binding as RT, but that's not possible in GL */
115 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
116 return 16;
117 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
118 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
119 case PIPE_CAP_MAX_VIEWPORTS:
120 return NVC0_MAX_VIEWPORTS;
121 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
122 return 4;
123 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
124 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
125 case PIPE_CAP_ENDIANNESS:
126 return PIPE_ENDIAN_LITTLE;
127 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
128 return 30;
129
130 /* supported caps */
131 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
132 case PIPE_CAP_TEXTURE_SWIZZLE:
133 case PIPE_CAP_TEXTURE_SHADOW_MAP:
134 case PIPE_CAP_NPOT_TEXTURES:
135 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
136 case PIPE_CAP_ANISOTROPIC_FILTER:
137 case PIPE_CAP_SEAMLESS_CUBE_MAP:
138 case PIPE_CAP_CUBE_MAP_ARRAY:
139 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
140 case PIPE_CAP_TEXTURE_MULTISAMPLE:
141 case PIPE_CAP_TWO_SIDED_STENCIL:
142 case PIPE_CAP_DEPTH_CLIP_DISABLE:
143 case PIPE_CAP_POINT_SPRITE:
144 case PIPE_CAP_TGSI_TEXCOORD:
145 case PIPE_CAP_SM3:
146 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
147 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
148 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
149 case PIPE_CAP_QUERY_TIMESTAMP:
150 case PIPE_CAP_QUERY_TIME_ELAPSED:
151 case PIPE_CAP_OCCLUSION_QUERY:
152 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
153 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
154 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
155 case PIPE_CAP_INDEP_BLEND_ENABLE:
156 case PIPE_CAP_INDEP_BLEND_FUNC:
157 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
158 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
159 case PIPE_CAP_PRIMITIVE_RESTART:
160 case PIPE_CAP_TGSI_INSTANCEID:
161 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
162 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
163 case PIPE_CAP_CONDITIONAL_RENDER:
164 case PIPE_CAP_TEXTURE_BARRIER:
165 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
166 case PIPE_CAP_START_INSTANCE:
167 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
168 case PIPE_CAP_DRAW_INDIRECT:
169 case PIPE_CAP_USER_CONSTANT_BUFFERS:
170 case PIPE_CAP_USER_INDEX_BUFFERS:
171 case PIPE_CAP_USER_VERTEX_BUFFERS:
172 case PIPE_CAP_TEXTURE_QUERY_LOD:
173 case PIPE_CAP_SAMPLE_SHADING:
174 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
175 case PIPE_CAP_TEXTURE_GATHER_SM5:
176 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
177 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
178 case PIPE_CAP_SAMPLER_VIEW_TARGET:
179 case PIPE_CAP_CLIP_HALFZ:
180 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
181 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
182 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
183 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
184 case PIPE_CAP_DEPTH_BOUNDS_TEST:
185 case PIPE_CAP_TGSI_TXQS:
186 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
187 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
188 case PIPE_CAP_SHAREABLE_SHADERS:
189 case PIPE_CAP_CLEAR_TEXTURE:
190 case PIPE_CAP_DRAW_PARAMETERS:
191 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
192 case PIPE_CAP_MULTI_DRAW_INDIRECT:
193 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
194 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
195 case PIPE_CAP_QUERY_BUFFER_OBJECT:
196 return 1;
197 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
198 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
199 case PIPE_CAP_COMPUTE:
200 if (debug_get_bool_option("NVF0_COMPUTE", false))
201 return 1;
202 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
203 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
204 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
205
206 /* unsupported caps */
207 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
208 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
209 case PIPE_CAP_SHADER_STENCIL_EXPORT:
210 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
211 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
212 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
213 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
214 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
215 case PIPE_CAP_FAKE_SW_MSAA:
216 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
217 case PIPE_CAP_VERTEXID_NOBASE:
218 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
219 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
220 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
221 case PIPE_CAP_INVALIDATE_BUFFER:
222 case PIPE_CAP_GENERATE_MIPMAP:
223 case PIPE_CAP_STRING_MARKER:
224 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
225 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
226 case PIPE_CAP_QUERY_MEMORY_INFO:
227 return 0;
228
229 case PIPE_CAP_VENDOR_ID:
230 return 0x10de;
231 case PIPE_CAP_DEVICE_ID: {
232 uint64_t device_id;
233 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
234 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
235 return -1;
236 }
237 return device_id;
238 }
239 case PIPE_CAP_ACCELERATED:
240 return 1;
241 case PIPE_CAP_VIDEO_MEMORY:
242 return dev->vram_size >> 20;
243 case PIPE_CAP_UMA:
244 return 0;
245 }
246
247 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
248 return 0;
249 }
250
251 static int
252 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
253 enum pipe_shader_cap param)
254 {
255 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
256
257 switch (shader) {
258 case PIPE_SHADER_VERTEX:
259 case PIPE_SHADER_GEOMETRY:
260 case PIPE_SHADER_FRAGMENT:
261 break;
262 case PIPE_SHADER_TESS_CTRL:
263 case PIPE_SHADER_TESS_EVAL:
264 if (class_3d >= GM107_3D_CLASS)
265 return 0;
266 break;
267 case PIPE_SHADER_COMPUTE:
268 if (!debug_get_bool_option("NVF0_COMPUTE", false))
269 if (class_3d > NVE4_3D_CLASS)
270 return 0;
271 break;
272 default:
273 return 0;
274 }
275
276 switch (param) {
277 case PIPE_SHADER_CAP_PREFERRED_IR:
278 return PIPE_SHADER_IR_TGSI;
279 case PIPE_SHADER_CAP_SUPPORTED_IRS:
280 return 0;
281 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
282 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
283 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
284 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
285 return 16384;
286 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
287 return 16;
288 case PIPE_SHADER_CAP_MAX_INPUTS:
289 if (shader == PIPE_SHADER_VERTEX)
290 return 32;
291 /* NOTE: These only count our slots for GENERIC varyings.
292 * The address space may be larger, but the actual hard limit seems to be
293 * less than what the address space layout permits, so don't add TEXCOORD,
294 * COLOR, etc. here.
295 */
296 if (shader == PIPE_SHADER_FRAGMENT)
297 return 0x1f0 / 16;
298 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
299 * and excludes 0x60 per-patch inputs.
300 */
301 return 0x200 / 16;
302 case PIPE_SHADER_CAP_MAX_OUTPUTS:
303 return 32;
304 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
305 return 65536;
306 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
307 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
308 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
309 return NVC0_MAX_PIPE_CONSTBUFS;
310 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
311 return shader != PIPE_SHADER_FRAGMENT;
312 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
313 return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
314 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
315 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
316 return 1;
317 case PIPE_SHADER_CAP_MAX_PREDS:
318 return 0;
319 case PIPE_SHADER_CAP_MAX_TEMPS:
320 return NVC0_CAP_MAX_PROGRAM_TEMPS;
321 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
322 return 1;
323 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
324 return 0;
325 case PIPE_SHADER_CAP_SUBROUTINES:
326 return 1;
327 case PIPE_SHADER_CAP_INTEGERS:
328 return 1;
329 case PIPE_SHADER_CAP_DOUBLES:
330 return 1;
331 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
332 return 1;
333 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
334 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
335 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
336 return 0;
337 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
338 return NVC0_MAX_BUFFERS;
339 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
340 return 16; /* would be 32 in linked (OpenGL-style) mode */
341 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
342 return 16; /* XXX not sure if more are really safe */
343 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
344 return 32;
345 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
346 return 0;
347 default:
348 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
349 return 0;
350 }
351 }
352
353 static float
354 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
355 {
356 switch (param) {
357 case PIPE_CAPF_MAX_LINE_WIDTH:
358 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
359 return 10.0f;
360 case PIPE_CAPF_MAX_POINT_WIDTH:
361 return 63.0f;
362 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
363 return 63.375f;
364 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
365 return 16.0f;
366 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
367 return 15.0f;
368 case PIPE_CAPF_GUARD_BAND_LEFT:
369 case PIPE_CAPF_GUARD_BAND_TOP:
370 return 0.0f;
371 case PIPE_CAPF_GUARD_BAND_RIGHT:
372 case PIPE_CAPF_GUARD_BAND_BOTTOM:
373 return 0.0f; /* that or infinity */
374 }
375
376 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
377 return 0.0f;
378 }
379
380 static int
381 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
382 enum pipe_compute_cap param, void *data)
383 {
384 struct nvc0_screen *screen = nvc0_screen(pscreen);
385 const uint16_t obj_class = screen->compute->oclass;
386
387 #define RET(x) do { \
388 if (data) \
389 memcpy(data, x, sizeof(x)); \
390 return sizeof(x); \
391 } while (0)
392
393 switch (param) {
394 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
395 RET((uint64_t []) { 3 });
396 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
397 if (obj_class >= NVE4_COMPUTE_CLASS) {
398 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
399 } else {
400 RET(((uint64_t []) { 65535, 65535, 65535 }));
401 }
402 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
403 RET(((uint64_t []) { 1024, 1024, 64 }));
404 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
405 RET((uint64_t []) { 1024 });
406 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
407 RET((uint64_t []) { 1ULL << 40 });
408 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
409 RET((uint64_t []) { 48 << 10 });
410 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
411 RET((uint64_t []) { 512 << 10 });
412 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
413 RET((uint64_t []) { 4096 });
414 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
415 RET((uint32_t []) { 32 });
416 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
417 RET((uint64_t []) { 1ULL << 40 });
418 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
419 RET((uint32_t []) { 0 });
420 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
421 RET((uint32_t []) { screen->mp_count_compute });
422 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
423 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
424 default:
425 return 0;
426 }
427
428 #undef RET
429 }
430
431 static void
432 nvc0_screen_destroy(struct pipe_screen *pscreen)
433 {
434 struct nvc0_screen *screen = nvc0_screen(pscreen);
435
436 if (!nouveau_drm_screen_unref(&screen->base))
437 return;
438
439 if (screen->base.fence.current) {
440 struct nouveau_fence *current = NULL;
441
442 /* nouveau_fence_wait will create a new current fence, so wait on the
443 * _current_ one, and remove both.
444 */
445 nouveau_fence_ref(screen->base.fence.current, &current);
446 nouveau_fence_wait(current, NULL);
447 nouveau_fence_ref(NULL, &current);
448 nouveau_fence_ref(NULL, &screen->base.fence.current);
449 }
450 if (screen->base.pushbuf)
451 screen->base.pushbuf->user_priv = NULL;
452
453 if (screen->blitter)
454 nvc0_blitter_destroy(screen);
455 if (screen->pm.prog) {
456 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
457 nvc0_program_destroy(NULL, screen->pm.prog);
458 FREE(screen->pm.prog);
459 }
460
461 nouveau_bo_ref(NULL, &screen->text);
462 nouveau_bo_ref(NULL, &screen->uniform_bo);
463 nouveau_bo_ref(NULL, &screen->tls);
464 nouveau_bo_ref(NULL, &screen->txc);
465 nouveau_bo_ref(NULL, &screen->fence.bo);
466 nouveau_bo_ref(NULL, &screen->poly_cache);
467 nouveau_bo_ref(NULL, &screen->parm);
468
469 nouveau_heap_destroy(&screen->lib_code);
470 nouveau_heap_destroy(&screen->text_heap);
471
472 FREE(screen->tic.entries);
473
474 nouveau_object_del(&screen->eng3d);
475 nouveau_object_del(&screen->eng2d);
476 nouveau_object_del(&screen->m2mf);
477 nouveau_object_del(&screen->compute);
478 nouveau_object_del(&screen->nvsw);
479
480 nouveau_screen_fini(&screen->base);
481
482 FREE(screen);
483 }
484
485 static int
486 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
487 unsigned size, const uint32_t *data)
488 {
489 struct nouveau_pushbuf *push = screen->base.pushbuf;
490
491 size /= 4;
492
493 assert((pos + size) <= 0x800);
494
495 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
496 PUSH_DATA (push, (m - 0x3800) / 8);
497 PUSH_DATA (push, pos);
498 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
499 PUSH_DATA (push, pos);
500 PUSH_DATAp(push, data, size);
501
502 return pos + size;
503 }
504
505 static void
506 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
507 {
508 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
509 PUSH_DATA (push, 0xff);
510 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
511 PUSH_DATA (push, 0xff);
512 PUSH_DATA (push, 0xff);
513 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
514 PUSH_DATA (push, 0xff);
515 PUSH_DATA (push, 0xff);
516 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
517 PUSH_DATA (push, 0x3f);
518
519 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
520 PUSH_DATA (push, (3 << 16) | 3);
521 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
522 PUSH_DATA (push, (2 << 16) | 2);
523
524 if (obj_class < GM107_3D_CLASS) {
525 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
526 PUSH_DATA (push, 0);
527 }
528 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
529 PUSH_DATA (push, 0x10);
530 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
531 PUSH_DATA (push, 0x10);
532 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
533 PUSH_DATA (push, 0x10);
534 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
535 PUSH_DATA (push, 0x10);
536 PUSH_DATA (push, 0x10);
537 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
538 PUSH_DATA (push, 0x10);
539 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
540 PUSH_DATA (push, 0xe);
541
542 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
543 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
544 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
545 PUSH_DATA (push, 0);
546 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
547 PUSH_DATA (push, 3);
548
549 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
550 PUSH_DATA (push, 0x3fffff);
551 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
552 PUSH_DATA (push, 1);
553 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
554 PUSH_DATA (push, 1);
555
556 if (obj_class < GM107_3D_CLASS) {
557 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
558 PUSH_DATA (push, 3);
559
560 if (obj_class >= NVE4_3D_CLASS) {
561 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
562 PUSH_DATA (push, 1);
563 }
564 }
565
566 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
567 * are supposed to do */
568 }
569
570 static void
571 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
572 {
573 struct nvc0_screen *screen = nvc0_screen(pscreen);
574 struct nouveau_pushbuf *push = screen->base.pushbuf;
575
576 /* we need to do it after possible flush in MARK_RING */
577 *sequence = ++screen->base.fence.sequence;
578
579 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
580 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
581 PUSH_DATAh(push, screen->fence.bo->offset);
582 PUSH_DATA (push, screen->fence.bo->offset);
583 PUSH_DATA (push, *sequence);
584 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
585 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
586 }
587
588 static u32
589 nvc0_screen_fence_update(struct pipe_screen *pscreen)
590 {
591 struct nvc0_screen *screen = nvc0_screen(pscreen);
592 return screen->fence.map[0];
593 }
594
595 static int
596 nvc0_screen_init_compute(struct nvc0_screen *screen)
597 {
598 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
599
600 switch (screen->base.device->chipset & ~0xf) {
601 case 0xc0:
602 case 0xd0:
603 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
604 case 0xe0:
605 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
606 case 0xf0:
607 case 0x100:
608 case 0x110:
609 if (debug_get_bool_option("NVF0_COMPUTE", false))
610 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
611 case 0x120:
612 return 0;
613 default:
614 return -1;
615 }
616 }
617
618 bool
619 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
620 uint32_t lpos, uint32_t lneg, uint32_t cstack)
621 {
622 struct nouveau_bo *bo = NULL;
623 int ret;
624 uint64_t size = (lpos + lneg) * 32 + cstack;
625
626 if (size >= (1 << 20)) {
627 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
628 return false;
629 }
630
631 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
632 size = align(size, 0x8000);
633 size *= screen->mp_count;
634
635 size = align(size, 1 << 17);
636
637 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
638 NULL, &bo);
639 if (ret) {
640 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
641 return false;
642 }
643 nouveau_bo_ref(NULL, &screen->tls);
644 screen->tls = bo;
645 return true;
646 }
647
648 #define FAIL_SCREEN_INIT(str, err) \
649 do { \
650 NOUVEAU_ERR(str, err); \
651 goto fail; \
652 } while(0)
653
654 struct nouveau_screen *
655 nvc0_screen_create(struct nouveau_device *dev)
656 {
657 struct nvc0_screen *screen;
658 struct pipe_screen *pscreen;
659 struct nouveau_object *chan;
660 struct nouveau_pushbuf *push;
661 uint64_t value;
662 uint32_t obj_class;
663 uint32_t flags;
664 int ret;
665 unsigned i;
666
667 switch (dev->chipset & ~0xf) {
668 case 0xc0:
669 case 0xd0:
670 case 0xe0:
671 case 0xf0:
672 case 0x100:
673 case 0x110:
674 case 0x120:
675 break;
676 default:
677 return NULL;
678 }
679
680 screen = CALLOC_STRUCT(nvc0_screen);
681 if (!screen)
682 return NULL;
683 pscreen = &screen->base.base;
684 pscreen->destroy = nvc0_screen_destroy;
685
686 ret = nouveau_screen_init(&screen->base, dev);
687 if (ret) {
688 nvc0_screen_destroy(pscreen);
689 return NULL;
690 }
691 chan = screen->base.channel;
692 push = screen->base.pushbuf;
693 push->user_priv = screen;
694 push->rsvd_kick = 5;
695
696 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
697 PIPE_BIND_SHADER_BUFFER |
698 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
699 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
700 screen->base.sysmem_bindings |=
701 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
702
703 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
704 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
705 screen->base.vidmem_bindings = 0;
706 }
707
708 pscreen->context_create = nvc0_create;
709 pscreen->is_format_supported = nvc0_screen_is_format_supported;
710 pscreen->get_param = nvc0_screen_get_param;
711 pscreen->get_shader_param = nvc0_screen_get_shader_param;
712 pscreen->get_paramf = nvc0_screen_get_paramf;
713 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
714 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
715
716 nvc0_screen_init_resource_functions(pscreen);
717
718 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
719 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
720
721 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
722 if (screen->base.drm->version >= 0x01000202)
723 flags |= NOUVEAU_BO_COHERENT;
724
725 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
726 if (ret)
727 goto fail;
728 nouveau_bo_map(screen->fence.bo, 0, NULL);
729 screen->fence.map = screen->fence.bo->map;
730 screen->base.fence.emit = nvc0_screen_fence_emit;
731 screen->base.fence.update = nvc0_screen_fence_update;
732
733
734 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
735 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
736 if (ret)
737 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
738
739 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
740 PUSH_DATA (push, screen->nvsw->handle);
741
742 switch (dev->chipset & ~0xf) {
743 case 0x120:
744 case 0x110:
745 case 0x100:
746 case 0xf0:
747 obj_class = NVF0_P2MF_CLASS;
748 break;
749 case 0xe0:
750 obj_class = NVE4_P2MF_CLASS;
751 break;
752 default:
753 obj_class = NVC0_M2MF_CLASS;
754 break;
755 }
756 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
757 &screen->m2mf);
758 if (ret)
759 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
760
761 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
762 PUSH_DATA (push, screen->m2mf->oclass);
763 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
764 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
765 PUSH_DATA (push, 0xa0b5);
766 }
767
768 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
769 &screen->eng2d);
770 if (ret)
771 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
772
773 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
774 PUSH_DATA (push, screen->eng2d->oclass);
775 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
776 PUSH_DATA (push, 0);
777 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
778 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
779 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
780 PUSH_DATA (push, 0);
781 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
782 PUSH_DATA (push, 0);
783 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
784 PUSH_DATA (push, 0x3f);
785 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
786 PUSH_DATA (push, 1);
787 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
788 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
789
790 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
791 PUSH_DATAh(push, screen->fence.bo->offset + 16);
792 PUSH_DATA (push, screen->fence.bo->offset + 16);
793
794 switch (dev->chipset & ~0xf) {
795 case 0x120:
796 obj_class = GM200_3D_CLASS;
797 break;
798 case 0x110:
799 obj_class = GM107_3D_CLASS;
800 break;
801 case 0x100:
802 case 0xf0:
803 obj_class = NVF0_3D_CLASS;
804 break;
805 case 0xe0:
806 switch (dev->chipset) {
807 case 0xea:
808 obj_class = NVEA_3D_CLASS;
809 break;
810 default:
811 obj_class = NVE4_3D_CLASS;
812 break;
813 }
814 break;
815 case 0xd0:
816 obj_class = NVC8_3D_CLASS;
817 break;
818 case 0xc0:
819 default:
820 switch (dev->chipset) {
821 case 0xc8:
822 obj_class = NVC8_3D_CLASS;
823 break;
824 case 0xc1:
825 obj_class = NVC1_3D_CLASS;
826 break;
827 default:
828 obj_class = NVC0_3D_CLASS;
829 break;
830 }
831 break;
832 }
833 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
834 &screen->eng3d);
835 if (ret)
836 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
837 screen->base.class_3d = obj_class;
838
839 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
840 PUSH_DATA (push, screen->eng3d->oclass);
841
842 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
843 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
844
845 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
846 /* kill shaders after about 1 second (at 100 MHz) */
847 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
848 PUSH_DATA (push, 0x17);
849 }
850
851 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
852 screen->base.drm->version >= 0x01000101);
853 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
854 for (i = 0; i < 8; ++i)
855 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
856
857 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
858 PUSH_DATA (push, 1);
859
860 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
861 PUSH_DATA (push, 0);
862 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
863 PUSH_DATA (push, 0);
864 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
865 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
866 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
867 PUSH_DATA (push, 0);
868 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
869 PUSH_DATA (push, 1);
870 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
871 PUSH_DATA (push, 1);
872 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
873 PUSH_DATA (push, 1);
874 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
875 PUSH_DATA (push, 0);
876 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
877 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
878 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
879 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
880 } else {
881 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
882 PUSH_DATA (push, 15);
883 }
884 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
885 PUSH_DATA (push, 8); /* 128 */
886 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
887 PUSH_DATA (push, 1);
888 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
889 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
890 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
891 }
892
893 nvc0_magic_3d_init(push, screen->eng3d->oclass);
894
895 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
896 &screen->text);
897 if (ret)
898 goto fail;
899
900 /* XXX: getting a page fault at the end of the code buffer every few
901 * launches, don't use the last 256 bytes to work around them - prefetch ?
902 */
903 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
904
905 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
906 &screen->uniform_bo);
907 if (ret)
908 goto fail;
909
910 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
911
912 for (i = 0; i < 5; ++i) {
913 /* TIC and TSC entries for each unit (nve4+ only) */
914 /* auxiliary constants (6 user clip planes, base instance id) */
915 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
916 PUSH_DATA (push, 1024);
917 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 10));
918 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 10));
919 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
920 PUSH_DATA (push, (15 << 4) | 1);
921 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
922 unsigned j;
923 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
924 PUSH_DATA (push, 0);
925 for (j = 0; j < 8; ++j)
926 PUSH_DATA(push, j);
927 } else {
928 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
929 PUSH_DATA (push, 0x54);
930 }
931 }
932 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
933 PUSH_DATA (push, 0);
934
935 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
936 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
937 PUSH_DATA (push, 256);
938 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
939 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
940 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
941 PUSH_DATA (push, 0);
942 PUSH_DATAf(push, 0.0f);
943 PUSH_DATAf(push, 0.0f);
944 PUSH_DATAf(push, 0.0f);
945 PUSH_DATAf(push, 0.0f);
946 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
947 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
948 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
949
950 if (screen->base.drm->version >= 0x01000101) {
951 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
952 if (ret) {
953 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
954 goto fail;
955 }
956 } else {
957 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
958 value = (8 << 8) | 4;
959 else
960 value = (16 << 8) | 4;
961 }
962 screen->gpc_count = value & 0x000000ff;
963 screen->mp_count = value >> 8;
964 screen->mp_count_compute = screen->mp_count;
965
966 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
967
968 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
969 PUSH_DATAh(push, screen->text->offset);
970 PUSH_DATA (push, screen->text->offset);
971 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
972 PUSH_DATAh(push, screen->tls->offset);
973 PUSH_DATA (push, screen->tls->offset);
974 PUSH_DATA (push, screen->tls->size >> 32);
975 PUSH_DATA (push, screen->tls->size);
976 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
977 PUSH_DATA (push, 0);
978 /* Reduce likelihood of collision with real buffers by placing the hole at
979 * the top of the 4G area. This will have to be dealt with for real
980 * eventually by blocking off that area from the VM.
981 */
982 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
983 PUSH_DATA (push, 0xff << 24);
984
985 if (screen->eng3d->oclass < GM107_3D_CLASS) {
986 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
987 &screen->poly_cache);
988 if (ret)
989 goto fail;
990
991 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
992 PUSH_DATAh(push, screen->poly_cache->offset);
993 PUSH_DATA (push, screen->poly_cache->offset);
994 PUSH_DATA (push, 3);
995 }
996
997 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
998 &screen->txc);
999 if (ret)
1000 goto fail;
1001
1002 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1003 PUSH_DATAh(push, screen->txc->offset);
1004 PUSH_DATA (push, screen->txc->offset);
1005 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1006 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1007 screen->tic.maxwell = true;
1008 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1009 screen->tic.maxwell =
1010 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1011 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1012 }
1013 }
1014
1015 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1016 PUSH_DATAh(push, screen->txc->offset + 65536);
1017 PUSH_DATA (push, screen->txc->offset + 65536);
1018 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1019
1020 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1021 PUSH_DATA (push, 0);
1022 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1023 PUSH_DATA (push, 0);
1024 PUSH_DATA (push, 0);
1025 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1026 PUSH_DATA (push, 0x3f);
1027
1028 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1029 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1030 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1031 for (i = 0; i < 8 * 2; ++i)
1032 PUSH_DATA(push, 0);
1033 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1034 PUSH_DATA (push, 0);
1035 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1036 PUSH_DATA (push, 0);
1037
1038 /* neither scissors, viewport nor stencil mask should affect clears */
1039 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1040 PUSH_DATA (push, 0);
1041
1042 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1043 PUSH_DATA (push, 1);
1044 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1045 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1046 PUSH_DATAf(push, 0.0f);
1047 PUSH_DATAf(push, 1.0f);
1048 }
1049 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1050 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1051
1052 /* We use scissors instead of exact view volume clipping,
1053 * so they're always enabled.
1054 */
1055 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1056 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1057 PUSH_DATA (push, 1);
1058 PUSH_DATA (push, 8192 << 16);
1059 PUSH_DATA (push, 8192 << 16);
1060 }
1061
1062 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1063
1064 i = 0;
1065 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1066 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1067 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1068 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1069 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1070 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1071 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1072 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1073 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1074 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1075 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1076 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1077
1078 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1079 PUSH_DATA (push, 1);
1080 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1081 PUSH_DATA (push, 1);
1082 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1083 PUSH_DATA (push, 0x40);
1084 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1085 PUSH_DATA (push, 0);
1086 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1087 PUSH_DATA (push, 0x30);
1088 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1089 PUSH_DATA (push, 3);
1090 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1091 PUSH_DATA (push, 0x20);
1092 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1093 PUSH_DATA (push, 0x00);
1094 screen->save_state.patch_vertices = 3;
1095
1096 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1097 PUSH_DATA (push, 0);
1098 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1099 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1100
1101 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1102
1103 if (nvc0_screen_init_compute(screen))
1104 goto fail;
1105
1106 PUSH_KICK (push);
1107
1108 screen->tic.entries = CALLOC(4096, sizeof(void *));
1109 screen->tsc.entries = screen->tic.entries + 2048;
1110
1111 if (!nvc0_blitter_create(screen))
1112 goto fail;
1113
1114 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1115
1116 return &screen->base;
1117
1118 fail:
1119 screen->base.base.context_create = NULL;
1120 return &screen->base;
1121 }
1122
1123 int
1124 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1125 {
1126 int i = screen->tic.next;
1127
1128 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1129 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1130
1131 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1132
1133 if (screen->tic.entries[i])
1134 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1135
1136 screen->tic.entries[i] = entry;
1137 return i;
1138 }
1139
1140 int
1141 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1142 {
1143 int i = screen->tsc.next;
1144
1145 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1146 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1147
1148 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1149
1150 if (screen->tsc.entries[i])
1151 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1152
1153 screen->tsc.entries[i] = entry;
1154 return i;
1155 }