2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/format/u_format.h"
27 #include "util/format/u_format_s3tc.h"
28 #include "util/u_screen.h"
29 #include "pipe/p_screen.h"
31 #include "nouveau_vp3_video.h"
33 #include "codegen/nv50_ir_driver.h"
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
41 #include "nv50/g80_texture.xml.h"
44 nvc0_screen_is_format_supported(struct pipe_screen
*pscreen
,
45 enum pipe_format format
,
46 enum pipe_texture_target target
,
47 unsigned sample_count
,
48 unsigned storage_sample_count
,
51 const struct util_format_description
*desc
= util_format_description(format
);
55 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
58 if (MAX2(1, sample_count
) != MAX2(1, storage_sample_count
))
61 /* Short-circuit the rest of the logic -- this is used by the gallium frontend
62 * to determine valid MS levels in a no-attachments scenario.
64 if (format
== PIPE_FORMAT_NONE
&& bindings
& PIPE_BIND_RENDER_TARGET
)
67 if ((bindings
& PIPE_BIND_SAMPLER_VIEW
) && (target
!= PIPE_BUFFER
))
68 if (util_format_get_blocksizebits(format
) == 3 * 32)
71 if (bindings
& PIPE_BIND_LINEAR
)
72 if (util_format_is_depth_or_stencil(format
) ||
73 (target
!= PIPE_TEXTURE_1D
&&
74 target
!= PIPE_TEXTURE_2D
&&
75 target
!= PIPE_TEXTURE_RECT
) ||
79 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A
82 if ((desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
||
83 desc
->layout
== UTIL_FORMAT_LAYOUT_ASTC
) &&
84 nouveau_screen(pscreen
)->device
->chipset
!= 0x12b &&
85 nouveau_screen(pscreen
)->class_3d
!= NVEA_3D_CLASS
)
88 /* shared is always supported */
89 bindings
&= ~(PIPE_BIND_LINEAR
|
92 if (bindings
& PIPE_BIND_SHADER_IMAGE
) {
93 if (format
== PIPE_FORMAT_B8G8R8A8_UNORM
&&
94 nouveau_screen(pscreen
)->class_3d
< NVE4_3D_CLASS
) {
95 /* This should work on Fermi, but for currently unknown reasons it
96 * does not and results in breaking reads from pbos. */
101 return (( nvc0_format_table
[format
].usage
|
102 nvc0_vertex_format
[format
].usage
) & bindings
) == bindings
;
106 nvc0_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
108 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
109 const struct nouveau_screen
*screen
= nouveau_screen(pscreen
);
110 struct nouveau_device
*dev
= screen
->device
;
113 /* non-boolean caps */
114 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
116 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
118 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
120 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
122 case PIPE_CAP_MIN_TEXEL_OFFSET
:
124 case PIPE_CAP_MAX_TEXEL_OFFSET
:
126 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
128 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
130 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
131 return 128 * 1024 * 1024;
132 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
134 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
136 case PIPE_CAP_MAX_RENDER_TARGETS
:
138 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
140 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
141 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS
:
143 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
145 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
146 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
148 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
149 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
151 case PIPE_CAP_MAX_VERTEX_STREAMS
:
153 case PIPE_CAP_MAX_GS_INVOCATIONS
:
155 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
157 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
159 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET
:
161 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
163 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
164 if (class_3d
< GM107_3D_CLASS
)
165 return 256; /* IMAGE bindings require alignment to 256 */
167 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
169 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
170 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
171 case PIPE_CAP_MAX_VIEWPORTS
:
172 return NVC0_MAX_VIEWPORTS
;
173 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
175 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
176 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50
;
177 case PIPE_CAP_ENDIANNESS
:
178 return PIPE_ENDIAN_LITTLE
;
179 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
181 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
182 return NVC0_MAX_WINDOW_RECTANGLES
;
183 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
184 return class_3d
>= GM200_3D_CLASS
? 8 : 0;
185 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
186 return 64 * 1024 * 1024;
187 case PIPE_CAP_MAX_VARYINGS
:
188 /* NOTE: These only count our slots for GENERIC varyings.
189 * The address space may be larger, but the actual hard limit seems to be
190 * less than what the address space layout permits, so don't add TEXCOORD,
194 case PIPE_CAP_MAX_VERTEX_BUFFERS
:
196 case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE
:
197 return 512 * 1024; /* TODO: Investigate tuning this */
200 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
201 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
202 case PIPE_CAP_TEXTURE_SWIZZLE
:
203 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
204 case PIPE_CAP_NPOT_TEXTURES
:
205 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
206 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
207 case PIPE_CAP_ANISOTROPIC_FILTER
:
208 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
209 case PIPE_CAP_CUBE_MAP_ARRAY
:
210 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
211 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
212 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
213 case PIPE_CAP_POINT_SPRITE
:
214 case PIPE_CAP_TGSI_TEXCOORD
:
215 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
216 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
217 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
218 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
219 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
220 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
221 case PIPE_CAP_QUERY_TIMESTAMP
:
222 case PIPE_CAP_QUERY_TIME_ELAPSED
:
223 case PIPE_CAP_OCCLUSION_QUERY
:
224 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
225 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
226 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
227 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
228 case PIPE_CAP_INDEP_BLEND_ENABLE
:
229 case PIPE_CAP_INDEP_BLEND_FUNC
:
230 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
231 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
232 case PIPE_CAP_PRIMITIVE_RESTART
:
233 case PIPE_CAP_TGSI_INSTANCEID
:
234 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
235 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
236 case PIPE_CAP_CONDITIONAL_RENDER
:
237 case PIPE_CAP_TEXTURE_BARRIER
:
238 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
239 case PIPE_CAP_START_INSTANCE
:
240 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
241 case PIPE_CAP_DRAW_INDIRECT
:
242 case PIPE_CAP_USER_VERTEX_BUFFERS
:
243 case PIPE_CAP_TEXTURE_QUERY_LOD
:
244 case PIPE_CAP_SAMPLE_SHADING
:
245 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
246 case PIPE_CAP_TEXTURE_GATHER_SM5
:
247 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
248 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
249 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
250 case PIPE_CAP_CLIP_HALFZ
:
251 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
252 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
253 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
254 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
255 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
256 case PIPE_CAP_TGSI_TXQS
:
257 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
258 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
259 case PIPE_CAP_SHAREABLE_SHADERS
:
260 case PIPE_CAP_CLEAR_TEXTURE
:
261 case PIPE_CAP_DRAW_PARAMETERS
:
262 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
263 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
264 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
265 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
266 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
267 case PIPE_CAP_INVALIDATE_BUFFER
:
268 case PIPE_CAP_STRING_MARKER
:
269 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
270 case PIPE_CAP_CULL_DISTANCE
:
271 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
272 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
273 case PIPE_CAP_TGSI_VOTE
:
274 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
275 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
276 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
277 case PIPE_CAP_DOUBLES
:
279 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
280 case PIPE_CAP_TGSI_CLOCK
:
281 case PIPE_CAP_COMPUTE
:
282 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
283 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
284 case PIPE_CAP_QUERY_SO_OVERFLOW
:
285 case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL
:
286 case PIPE_CAP_TGSI_DIV
:
287 case PIPE_CAP_TGSI_ATOMINC_WRAP
:
288 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION
:
289 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
290 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF
:
291 case PIPE_CAP_FLATSHADE
:
292 case PIPE_CAP_ALPHA_TEST
:
293 case PIPE_CAP_POINT_SIZE_FIXED
:
294 case PIPE_CAP_TWO_SIDED_COLOR
:
295 case PIPE_CAP_CLIP_PLANES
:
296 case PIPE_CAP_TEXTURE_SHADOW_LOD
:
297 case PIPE_CAP_PACKED_STREAM_OUTPUT
:
298 case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES
:
300 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
301 return nouveau_screen(pscreen
)->vram_domain
& NOUVEAU_BO_VRAM
? 1 : 0;
302 case PIPE_CAP_FBFETCH
:
303 return class_3d
>= NVE4_3D_CLASS
? 1 : 0; /* needs testing on fermi */
304 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
305 case PIPE_CAP_TGSI_BALLOT
:
306 return class_3d
>= NVE4_3D_CLASS
;
307 case PIPE_CAP_BINDLESS_TEXTURE
:
308 return class_3d
>= NVE4_3D_CLASS
;
309 case PIPE_CAP_TGSI_ATOMFADD
:
310 return class_3d
< GM107_3D_CLASS
; /* needs additional lowering */
311 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
312 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
313 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
314 case PIPE_CAP_POST_DEPTH_COVERAGE
:
315 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
316 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
317 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
318 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
319 case PIPE_CAP_VIEWPORT_SWIZZLE
:
320 case PIPE_CAP_VIEWPORT_MASK
:
321 return class_3d
>= GM200_3D_CLASS
;
322 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
323 return class_3d
>= GP100_3D_CLASS
;
325 /* caps has to be turned on with nir */
326 case PIPE_CAP_INT64_DIVMOD
:
327 return screen
->prefer_nir
? 1 : 0;
329 /* unsupported caps */
330 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
331 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
332 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
333 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
334 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
335 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
336 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
337 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
338 case PIPE_CAP_FAKE_SW_MSAA
:
339 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
340 case PIPE_CAP_VERTEXID_NOBASE
:
341 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
342 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
343 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL
:
344 case PIPE_CAP_GENERATE_MIPMAP
:
345 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
346 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
347 case PIPE_CAP_QUERY_MEMORY_INFO
:
348 case PIPE_CAP_PCI_GROUP
:
349 case PIPE_CAP_PCI_BUS
:
350 case PIPE_CAP_PCI_DEVICE
:
351 case PIPE_CAP_PCI_FUNCTION
:
352 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
353 case PIPE_CAP_NATIVE_FENCE_FD
:
354 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
355 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
356 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
357 case PIPE_CAP_MEMOBJ
:
358 case PIPE_CAP_LOAD_CONSTBUF
:
359 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
360 case PIPE_CAP_TILE_RASTER_ORDER
:
361 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
362 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
363 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
364 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
365 case PIPE_CAP_FENCE_SIGNAL
:
366 case PIPE_CAP_CONSTBUF0_FLAGS
:
367 case PIPE_CAP_PACKED_UNIFORMS
:
368 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
369 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS
:
370 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS
:
371 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS
:
372 case PIPE_CAP_SURFACE_SAMPLE_COUNT
:
373 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE
:
374 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND
:
375 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS
:
376 case PIPE_CAP_NIR_COMPACT_ARRAYS
:
377 case PIPE_CAP_IMAGE_LOAD_FORMATTED
:
378 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES
:
379 case PIPE_CAP_ATOMIC_FLOAT_MINMAX
:
380 case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE
:
381 case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK
:
382 case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED
:
383 case PIPE_CAP_FBFETCH_COHERENT
:
384 case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS
:
385 case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE
:
386 case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS
: /* could be done */
387 case PIPE_CAP_INTEGER_MULTIPLY_32X16
: /* could be done */
388 case PIPE_CAP_FRONTEND_NOOP
:
389 case PIPE_CAP_GL_SPIRV
:
390 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL
:
391 case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED
:
392 case PIPE_CAP_PSIZ_CLAMPED
:
395 case PIPE_CAP_VENDOR_ID
:
397 case PIPE_CAP_DEVICE_ID
: {
399 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
400 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
405 case PIPE_CAP_ACCELERATED
:
407 case PIPE_CAP_VIDEO_MEMORY
:
408 return dev
->vram_size
>> 20;
413 debug_printf("%s: unhandled cap %d\n", __func__
, param
);
415 /* caps where we want the default value */
416 case PIPE_CAP_DMABUF
:
417 case PIPE_CAP_ESSL_FEATURE_LEVEL
:
418 case PIPE_CAP_THROTTLE
:
419 return u_pipe_screen_get_param_defaults(pscreen
, param
);
424 nvc0_screen_get_shader_param(struct pipe_screen
*pscreen
,
425 enum pipe_shader_type shader
,
426 enum pipe_shader_cap param
)
428 const struct nouveau_screen
*screen
= nouveau_screen(pscreen
);
429 const uint16_t class_3d
= screen
->class_3d
;
432 case PIPE_SHADER_VERTEX
:
433 case PIPE_SHADER_GEOMETRY
:
434 case PIPE_SHADER_FRAGMENT
:
435 case PIPE_SHADER_COMPUTE
:
436 case PIPE_SHADER_TESS_CTRL
:
437 case PIPE_SHADER_TESS_EVAL
:
444 case PIPE_SHADER_CAP_PREFERRED_IR
:
445 return screen
->prefer_nir
? PIPE_SHADER_IR_NIR
: PIPE_SHADER_IR_TGSI
;
446 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
447 uint32_t irs
= 1 << PIPE_SHADER_IR_NIR
|
448 ((class_3d
>= GV100_3D_CLASS
) ? 0 : 1 << PIPE_SHADER_IR_TGSI
);
449 if (screen
->force_enable_cl
)
450 irs
|= 1 << PIPE_SHADER_IR_NIR_SERIALIZED
;
453 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
454 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
455 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
456 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
458 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
460 case PIPE_SHADER_CAP_MAX_INPUTS
:
462 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
464 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
465 return NVC0_MAX_CONSTBUF_SIZE
;
466 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
467 return NVC0_MAX_PIPE_CONSTBUFS
;
468 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
469 return shader
!= PIPE_SHADER_FRAGMENT
;
470 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
471 /* HW doesn't support indirect addressing of fragment program inputs
472 * on Volta. The binary driver generates a function to handle every
473 * possible indirection, and indirectly calls the function to handle
476 if (class_3d
>= GV100_3D_CLASS
)
477 return shader
!= PIPE_SHADER_FRAGMENT
;
479 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
480 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
482 case PIPE_SHADER_CAP_MAX_TEMPS
:
483 return NVC0_CAP_MAX_PROGRAM_TEMPS
;
484 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
486 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
488 case PIPE_SHADER_CAP_SUBROUTINES
:
490 case PIPE_SHADER_CAP_INTEGERS
:
492 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
494 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
496 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
498 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
499 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
500 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
501 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
502 case PIPE_SHADER_CAP_INT64_ATOMICS
:
503 case PIPE_SHADER_CAP_FP16
:
504 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
505 case PIPE_SHADER_CAP_INT16
:
506 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
507 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
509 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
510 return NVC0_MAX_BUFFERS
;
511 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
512 return (class_3d
>= NVE4_3D_CLASS
) ? 32 : 16;
513 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
514 return (class_3d
>= NVE4_3D_CLASS
) ? 32 : 16;
515 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
517 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
518 if (class_3d
>= NVE4_3D_CLASS
)
519 return NVC0_MAX_IMAGES
;
520 if (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
)
521 return NVC0_MAX_IMAGES
;
524 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
530 nvc0_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
532 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
535 case PIPE_CAPF_MAX_LINE_WIDTH
:
536 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
538 case PIPE_CAPF_MAX_POINT_WIDTH
:
540 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
542 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
544 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
546 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
548 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
549 return class_3d
>= GM200_3D_CLASS
? 0.75f
: 0.0f
;
550 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
551 return class_3d
>= GM200_3D_CLASS
? 0.25f
: 0.0f
;
554 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param
);
559 nvc0_screen_get_compute_param(struct pipe_screen
*pscreen
,
560 enum pipe_shader_ir ir_type
,
561 enum pipe_compute_cap param
, void *data
)
563 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
564 const uint16_t obj_class
= screen
->compute
->oclass
;
566 #define RET(x) do { \
568 memcpy(data, x, sizeof(x)); \
573 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
574 RET((uint64_t []) { 3 });
575 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
576 if (obj_class
>= NVE4_COMPUTE_CLASS
) {
577 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
579 RET(((uint64_t []) { 65535, 65535, 65535 }));
581 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
582 RET(((uint64_t []) { 1024, 1024, 64 }));
583 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
584 RET((uint64_t []) { 1024 });
585 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
586 if (obj_class
>= NVE4_COMPUTE_CLASS
) {
587 RET((uint64_t []) { 1024 });
589 RET((uint64_t []) { 512 });
591 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
: /* g[] */
592 RET((uint64_t []) { 1ULL << 40 });
593 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
: /* s[] */
595 case GM200_COMPUTE_CLASS
:
596 RET((uint64_t []) { 96 << 10 });
598 case GM107_COMPUTE_CLASS
:
599 RET((uint64_t []) { 64 << 10 });
602 RET((uint64_t []) { 48 << 10 });
605 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
: /* l[] */
606 RET((uint64_t []) { 512 << 10 });
607 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
: /* c[], arbitrary limit */
608 RET((uint64_t []) { 4096 });
609 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
610 RET((uint32_t []) { 32 });
611 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
612 RET((uint64_t []) { 1ULL << 40 });
613 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
614 RET((uint32_t []) { 0 });
615 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
616 RET((uint32_t []) { screen
->mp_count_compute
});
617 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
618 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
619 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
620 RET((uint32_t []) { 64 });
629 nvc0_screen_get_sample_pixel_grid(struct pipe_screen
*pscreen
,
630 unsigned sample_count
,
631 unsigned *width
, unsigned *height
)
633 switch (sample_count
) {
636 /* this could be 4x4, but the GL state tracker makes it difficult to
637 * create a 1x MSAA texture and smaller grids save CB space */
659 nvc0_screen_destroy(struct pipe_screen
*pscreen
)
661 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
663 if (!nouveau_drm_screen_unref(&screen
->base
))
666 if (screen
->base
.fence
.current
) {
667 struct nouveau_fence
*current
= NULL
;
669 /* nouveau_fence_wait will create a new current fence, so wait on the
670 * _current_ one, and remove both.
672 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
673 nouveau_fence_wait(current
, NULL
);
674 nouveau_fence_ref(NULL
, ¤t
);
675 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
677 if (screen
->base
.pushbuf
)
678 screen
->base
.pushbuf
->user_priv
= NULL
;
681 nvc0_blitter_destroy(screen
);
682 if (screen
->pm
.prog
) {
683 screen
->pm
.prog
->code
= NULL
; /* hardcoded, don't FREE */
684 nvc0_program_destroy(NULL
, screen
->pm
.prog
);
685 FREE(screen
->pm
.prog
);
688 nouveau_bo_ref(NULL
, &screen
->text
);
689 nouveau_bo_ref(NULL
, &screen
->uniform_bo
);
690 nouveau_bo_ref(NULL
, &screen
->tls
);
691 nouveau_bo_ref(NULL
, &screen
->txc
);
692 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
693 nouveau_bo_ref(NULL
, &screen
->poly_cache
);
695 nouveau_heap_destroy(&screen
->lib_code
);
696 nouveau_heap_destroy(&screen
->text_heap
);
698 FREE(screen
->tic
.entries
);
700 nouveau_object_del(&screen
->eng3d
);
701 nouveau_object_del(&screen
->eng2d
);
702 nouveau_object_del(&screen
->m2mf
);
703 nouveau_object_del(&screen
->compute
);
704 nouveau_object_del(&screen
->nvsw
);
706 nouveau_screen_fini(&screen
->base
);
712 nvc0_graph_set_macro(struct nvc0_screen
*screen
, uint32_t m
, unsigned pos
,
713 unsigned size
, const uint32_t *data
)
715 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
719 assert((pos
+ size
) <= 0x800);
721 BEGIN_NVC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_ID
), 2);
722 PUSH_DATA (push
, (m
- 0x3800) / 8);
723 PUSH_DATA (push
, pos
);
724 BEGIN_1IC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS
), size
+ 1);
725 PUSH_DATA (push
, pos
);
726 PUSH_DATAp(push
, data
, size
);
732 nvc0_magic_3d_init(struct nouveau_pushbuf
*push
, uint16_t obj_class
)
734 BEGIN_NVC0(push
, SUBC_3D(0x10cc), 1);
735 PUSH_DATA (push
, 0xff);
736 BEGIN_NVC0(push
, SUBC_3D(0x10e0), 2);
737 PUSH_DATA (push
, 0xff);
738 PUSH_DATA (push
, 0xff);
739 BEGIN_NVC0(push
, SUBC_3D(0x10ec), 2);
740 PUSH_DATA (push
, 0xff);
741 PUSH_DATA (push
, 0xff);
742 if (obj_class
< GV100_3D_CLASS
) {
743 BEGIN_NVC0(push
, SUBC_3D(0x074c), 1);
744 PUSH_DATA (push
, 0x3f);
747 BEGIN_NVC0(push
, SUBC_3D(0x16a8), 1);
748 PUSH_DATA (push
, (3 << 16) | 3);
749 BEGIN_NVC0(push
, SUBC_3D(0x1794), 1);
750 PUSH_DATA (push
, (2 << 16) | 2);
752 if (obj_class
< GM107_3D_CLASS
) {
753 BEGIN_NVC0(push
, SUBC_3D(0x12ac), 1);
756 BEGIN_NVC0(push
, SUBC_3D(0x0218), 1);
757 PUSH_DATA (push
, 0x10);
758 BEGIN_NVC0(push
, SUBC_3D(0x10fc), 1);
759 PUSH_DATA (push
, 0x10);
760 BEGIN_NVC0(push
, SUBC_3D(0x1290), 1);
761 PUSH_DATA (push
, 0x10);
762 BEGIN_NVC0(push
, SUBC_3D(0x12d8), 2);
763 PUSH_DATA (push
, 0x10);
764 PUSH_DATA (push
, 0x10);
765 BEGIN_NVC0(push
, SUBC_3D(0x1140), 1);
766 PUSH_DATA (push
, 0x10);
767 BEGIN_NVC0(push
, SUBC_3D(0x1610), 1);
768 PUSH_DATA (push
, 0xe);
770 BEGIN_NVC0(push
, NVC0_3D(VERTEX_ID_GEN_MODE
), 1);
771 PUSH_DATA (push
, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START
);
772 BEGIN_NVC0(push
, SUBC_3D(0x030c), 1);
774 BEGIN_NVC0(push
, SUBC_3D(0x0300), 1);
777 if (obj_class
< GV100_3D_CLASS
) {
778 BEGIN_NVC0(push
, SUBC_3D(0x02d0), 1);
779 PUSH_DATA (push
, 0x3fffff);
781 BEGIN_NVC0(push
, SUBC_3D(0x0fdc), 1);
783 BEGIN_NVC0(push
, SUBC_3D(0x19c0), 1);
786 if (obj_class
< GM107_3D_CLASS
) {
787 BEGIN_NVC0(push
, SUBC_3D(0x075c), 1);
790 if (obj_class
>= NVE4_3D_CLASS
) {
791 BEGIN_NVC0(push
, SUBC_3D(0x07fc), 1);
796 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
797 * are supposed to do */
801 nvc0_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
803 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
804 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
806 /* we need to do it after possible flush in MARK_RING */
807 *sequence
= ++screen
->base
.fence
.sequence
;
809 assert(PUSH_AVAIL(push
) + push
->rsvd_kick
>= 5);
810 PUSH_DATA (push
, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH
), 4));
811 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
812 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
813 PUSH_DATA (push
, *sequence
);
814 PUSH_DATA (push
, NVC0_3D_QUERY_GET_FENCE
| NVC0_3D_QUERY_GET_SHORT
|
815 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT
));
819 nvc0_screen_fence_update(struct pipe_screen
*pscreen
)
821 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
822 return screen
->fence
.map
[0];
826 nvc0_screen_init_compute(struct nvc0_screen
*screen
)
828 screen
->base
.base
.get_compute_param
= nvc0_screen_get_compute_param
;
830 switch (screen
->base
.device
->chipset
& ~0xf) {
833 return nvc0_screen_compute_setup(screen
, screen
->base
.pushbuf
);
841 return nve4_screen_compute_setup(screen
, screen
->base
.pushbuf
);
848 nvc0_screen_resize_tls_area(struct nvc0_screen
*screen
,
849 uint32_t lpos
, uint32_t lneg
, uint32_t cstack
)
851 struct nouveau_bo
*bo
= NULL
;
853 uint64_t size
= (lpos
+ lneg
) * 32 + cstack
;
855 if (size
>= (1 << 20)) {
856 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64
"\n", size
);
860 size
*= (screen
->base
.device
->chipset
>= 0xe0) ? 64 : 48; /* max warps */
861 size
= align(size
, 0x8000);
862 size
*= screen
->mp_count
;
864 size
= align(size
, 1 << 17);
866 ret
= nouveau_bo_new(screen
->base
.device
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 17, size
,
871 /* Make sure that the pushbuf has acquired a reference to the old tls
872 * segment, as it may have commands that will reference it.
875 PUSH_REFN(screen
->base
.pushbuf
, screen
->tls
,
876 NV_VRAM_DOMAIN(&screen
->base
) | NOUVEAU_BO_RDWR
);
877 nouveau_bo_ref(NULL
, &screen
->tls
);
883 nvc0_screen_resize_text_area(struct nvc0_screen
*screen
, uint64_t size
)
885 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
886 struct nouveau_bo
*bo
;
889 ret
= nouveau_bo_new(screen
->base
.device
, NV_VRAM_DOMAIN(&screen
->base
),
890 1 << 17, size
, NULL
, &bo
);
894 /* Make sure that the pushbuf has acquired a reference to the old text
895 * segment, as it may have commands that will reference it.
898 PUSH_REFN(push
, screen
->text
,
899 NV_VRAM_DOMAIN(&screen
->base
) | NOUVEAU_BO_RD
);
900 nouveau_bo_ref(NULL
, &screen
->text
);
903 nouveau_heap_destroy(&screen
->lib_code
);
904 nouveau_heap_destroy(&screen
->text_heap
);
906 /* XXX: getting a page fault at the end of the code buffer every few
907 * launches, don't use the last 256 bytes to work around them - prefetch ?
909 nouveau_heap_init(&screen
->text_heap
, 0, size
- 0x100);
911 /* update the code segment setup */
912 if (screen
->eng3d
->oclass
< GV100_3D_CLASS
) {
913 BEGIN_NVC0(push
, NVC0_3D(CODE_ADDRESS_HIGH
), 2);
914 PUSH_DATAh(push
, screen
->text
->offset
);
915 PUSH_DATA (push
, screen
->text
->offset
);
916 if (screen
->compute
) {
917 BEGIN_NVC0(push
, NVC0_CP(CODE_ADDRESS_HIGH
), 2);
918 PUSH_DATAh(push
, screen
->text
->offset
);
919 PUSH_DATA (push
, screen
->text
->offset
);
927 nvc0_screen_bind_cb_3d(struct nvc0_screen
*screen
, bool *can_serialize
,
928 int stage
, int index
, int size
, uint64_t addr
)
932 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
934 if (screen
->base
.class_3d
>= GM107_3D_CLASS
) {
935 struct nvc0_cb_binding
*binding
= &screen
->cb_bindings
[stage
][index
];
937 // TODO: Better figure out the conditions in which this is needed
938 bool serialize
= binding
->addr
== addr
&& binding
->size
!= size
;
940 serialize
= serialize
&& *can_serialize
;
942 IMMED_NVC0(push
, NVC0_3D(SERIALIZE
), 0);
944 *can_serialize
= false;
947 binding
->addr
= addr
;
948 binding
->size
= size
;
952 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
953 PUSH_DATA (push
, size
);
954 PUSH_DATAh(push
, addr
);
955 PUSH_DATA (push
, addr
);
957 IMMED_NVC0(push
, NVC0_3D(CB_BIND(stage
)), (index
<< 4) | (size
>= 0));
961 nvc0_screen_get_compiler_options(struct pipe_screen
*pscreen
,
962 enum pipe_shader_ir ir
,
963 enum pipe_shader_type shader
)
965 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
966 if (ir
== PIPE_SHADER_IR_NIR
)
967 return nv50_ir_nir_shader_compiler_options(screen
->base
.device
->chipset
);
971 #define FAIL_SCREEN_INIT(str, err) \
973 NOUVEAU_ERR(str, err); \
977 struct nouveau_screen
*
978 nvc0_screen_create(struct nouveau_device
*dev
)
980 struct nvc0_screen
*screen
;
981 struct pipe_screen
*pscreen
;
982 struct nouveau_object
*chan
;
983 struct nouveau_pushbuf
*push
;
990 switch (dev
->chipset
& ~0xf) {
1005 screen
= CALLOC_STRUCT(nvc0_screen
);
1008 pscreen
= &screen
->base
.base
;
1009 pscreen
->destroy
= nvc0_screen_destroy
;
1011 ret
= nouveau_screen_init(&screen
->base
, dev
);
1013 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret
);
1014 chan
= screen
->base
.channel
;
1015 push
= screen
->base
.pushbuf
;
1016 push
->user_priv
= screen
;
1017 push
->rsvd_kick
= 5;
1019 /* TODO: could this be higher on Kepler+? how does reclocking vs no
1020 * reclocking affect performance?
1021 * TODO: could this be higher on Fermi?
1023 if (dev
->chipset
>= 0xe0)
1024 screen
->base
.transfer_pushbuf_threshold
= 1024;
1026 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
1027 PIPE_BIND_SHADER_BUFFER
|
1028 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
|
1029 PIPE_BIND_COMMAND_ARGS_BUFFER
| PIPE_BIND_QUERY_BUFFER
;
1030 screen
->base
.sysmem_bindings
|=
1031 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
1033 if (screen
->base
.vram_domain
& NOUVEAU_BO_GART
) {
1034 screen
->base
.sysmem_bindings
|= screen
->base
.vidmem_bindings
;
1035 screen
->base
.vidmem_bindings
= 0;
1038 pscreen
->context_create
= nvc0_create
;
1039 pscreen
->is_format_supported
= nvc0_screen_is_format_supported
;
1040 pscreen
->get_param
= nvc0_screen_get_param
;
1041 pscreen
->get_shader_param
= nvc0_screen_get_shader_param
;
1042 pscreen
->get_paramf
= nvc0_screen_get_paramf
;
1043 pscreen
->get_sample_pixel_grid
= nvc0_screen_get_sample_pixel_grid
;
1044 pscreen
->get_driver_query_info
= nvc0_screen_get_driver_query_info
;
1045 pscreen
->get_driver_query_group_info
= nvc0_screen_get_driver_query_group_info
;
1047 pscreen
->get_compiler_options
= nvc0_screen_get_compiler_options
;
1049 nvc0_screen_init_resource_functions(pscreen
);
1051 screen
->base
.base
.get_video_param
= nouveau_vp3_screen_get_video_param
;
1052 screen
->base
.base
.is_video_format_supported
= nouveau_vp3_screen_video_supported
;
1054 flags
= NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
;
1055 if (screen
->base
.drm
->version
>= 0x01000202)
1056 flags
|= NOUVEAU_BO_COHERENT
;
1058 ret
= nouveau_bo_new(dev
, flags
, 0, 4096, NULL
, &screen
->fence
.bo
);
1060 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret
);
1061 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
1062 screen
->fence
.map
= screen
->fence
.bo
->map
;
1063 screen
->base
.fence
.emit
= nvc0_screen_fence_emit
;
1064 screen
->base
.fence
.update
= nvc0_screen_fence_update
;
1066 if (dev
->chipset
< 0x140) {
1067 ret
= nouveau_object_new(chan
, (dev
->chipset
< 0xe0) ? 0x1f906e : 0x906e,
1068 NVIF_CLASS_SW_GF100
, NULL
, 0, &screen
->nvsw
);
1070 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret
);
1072 BEGIN_NVC0(push
, SUBC_SW(NV01_SUBCHAN_OBJECT
), 1);
1073 PUSH_DATA (push
, screen
->nvsw
->handle
);
1076 switch (dev
->chipset
& ~0xf) {
1083 obj_class
= NVF0_P2MF_CLASS
;
1086 obj_class
= NVE4_P2MF_CLASS
;
1089 obj_class
= NVC0_M2MF_CLASS
;
1092 ret
= nouveau_object_new(chan
, 0xbeef323f, obj_class
, NULL
, 0,
1095 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret
);
1097 BEGIN_NVC0(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
1098 PUSH_DATA (push
, screen
->m2mf
->oclass
);
1099 if (screen
->m2mf
->oclass
== NVE4_P2MF_CLASS
) {
1100 BEGIN_NVC0(push
, SUBC_COPY(NV01_SUBCHAN_OBJECT
), 1);
1101 PUSH_DATA (push
, 0xa0b5);
1104 ret
= nouveau_object_new(chan
, 0xbeef902d, NVC0_2D_CLASS
, NULL
, 0,
1107 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret
);
1109 BEGIN_NVC0(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
1110 PUSH_DATA (push
, screen
->eng2d
->oclass
);
1111 BEGIN_NVC0(push
, SUBC_2D(NVC0_2D_SINGLE_GPC
), 1);
1112 PUSH_DATA (push
, 0);
1113 BEGIN_NVC0(push
, NVC0_2D(OPERATION
), 1);
1114 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY
);
1115 BEGIN_NVC0(push
, NVC0_2D(CLIP_ENABLE
), 1);
1116 PUSH_DATA (push
, 0);
1117 BEGIN_NVC0(push
, NVC0_2D(COLOR_KEY_ENABLE
), 1);
1118 PUSH_DATA (push
, 0);
1119 BEGIN_NVC0(push
, SUBC_2D(0x0884), 1);
1120 PUSH_DATA (push
, 0x3f);
1121 BEGIN_NVC0(push
, SUBC_2D(0x0888), 1);
1122 PUSH_DATA (push
, 1);
1123 BEGIN_NVC0(push
, NVC0_2D(COND_MODE
), 1);
1124 PUSH_DATA (push
, NV50_2D_COND_MODE_ALWAYS
);
1126 BEGIN_NVC0(push
, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH
), 2);
1127 PUSH_DATAh(push
, screen
->fence
.bo
->offset
+ 16);
1128 PUSH_DATA (push
, screen
->fence
.bo
->offset
+ 16);
1130 switch (dev
->chipset
& ~0xf) {
1132 obj_class
= GV100_3D_CLASS
;
1135 switch (dev
->chipset
) {
1138 obj_class
= GP100_3D_CLASS
;
1141 obj_class
= GP102_3D_CLASS
;
1146 obj_class
= GM200_3D_CLASS
;
1149 obj_class
= GM107_3D_CLASS
;
1153 obj_class
= NVF0_3D_CLASS
;
1156 switch (dev
->chipset
) {
1158 obj_class
= NVEA_3D_CLASS
;
1161 obj_class
= NVE4_3D_CLASS
;
1166 obj_class
= NVC8_3D_CLASS
;
1170 switch (dev
->chipset
) {
1172 obj_class
= NVC8_3D_CLASS
;
1175 obj_class
= NVC1_3D_CLASS
;
1178 obj_class
= NVC0_3D_CLASS
;
1183 ret
= nouveau_object_new(chan
, 0xbeef003d, obj_class
, NULL
, 0,
1186 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret
);
1187 screen
->base
.class_3d
= obj_class
;
1189 BEGIN_NVC0(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
1190 PUSH_DATA (push
, screen
->eng3d
->oclass
);
1192 BEGIN_NVC0(push
, NVC0_3D(COND_MODE
), 1);
1193 PUSH_DATA (push
, NVC0_3D_COND_MODE_ALWAYS
);
1195 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1196 /* kill shaders after about 1 second (at 100 MHz) */
1197 BEGIN_NVC0(push
, NVC0_3D(WATCHDOG_TIMER
), 1);
1198 PUSH_DATA (push
, 0x17);
1201 IMMED_NVC0(push
, NVC0_3D(ZETA_COMP_ENABLE
),
1202 screen
->base
.drm
->version
>= 0x01000101);
1203 BEGIN_NVC0(push
, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1204 for (i
= 0; i
< 8; ++i
)
1205 PUSH_DATA(push
, screen
->base
.drm
->version
>= 0x01000101);
1207 BEGIN_NVC0(push
, NVC0_3D(RT_CONTROL
), 1);
1208 PUSH_DATA (push
, 1);
1210 BEGIN_NVC0(push
, NVC0_3D(CSAA_ENABLE
), 1);
1211 PUSH_DATA (push
, 0);
1212 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_ENABLE
), 1);
1213 PUSH_DATA (push
, 0);
1214 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_MODE
), 1);
1215 PUSH_DATA (push
, NVC0_3D_MULTISAMPLE_MODE_MS1
);
1216 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_CTRL
), 1);
1217 PUSH_DATA (push
, 0);
1218 BEGIN_NVC0(push
, NVC0_3D(LINE_WIDTH_SEPARATE
), 1);
1219 PUSH_DATA (push
, 1);
1220 BEGIN_NVC0(push
, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS
), 1);
1221 PUSH_DATA (push
, 1);
1222 BEGIN_NVC0(push
, NVC0_3D(BLEND_SEPARATE_ALPHA
), 1);
1223 PUSH_DATA (push
, 1);
1224 BEGIN_NVC0(push
, NVC0_3D(BLEND_ENABLE_COMMON
), 1);
1225 PUSH_DATA (push
, 0);
1226 BEGIN_NVC0(push
, NVC0_3D(SHADE_MODEL
), 1);
1227 PUSH_DATA (push
, NVC0_3D_SHADE_MODEL_SMOOTH
);
1228 if (screen
->eng3d
->oclass
< NVE4_3D_CLASS
) {
1229 IMMED_NVC0(push
, NVC0_3D(TEX_MISC
), 0);
1231 BEGIN_NVC0(push
, NVE4_3D(TEX_CB_INDEX
), 1);
1232 PUSH_DATA (push
, 15);
1234 BEGIN_NVC0(push
, NVC0_3D(CALL_LIMIT_LOG
), 1);
1235 PUSH_DATA (push
, 8); /* 128 */
1236 BEGIN_NVC0(push
, NVC0_3D(ZCULL_STATCTRS_ENABLE
), 1);
1237 PUSH_DATA (push
, 1);
1238 if (screen
->eng3d
->oclass
>= NVC1_3D_CLASS
) {
1239 BEGIN_NVC0(push
, NVC0_3D(CACHE_SPLIT
), 1);
1240 PUSH_DATA (push
, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1
);
1243 nvc0_magic_3d_init(push
, screen
->eng3d
->oclass
);
1245 ret
= nvc0_screen_resize_text_area(screen
, 1 << 19);
1247 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret
);
1249 /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1250 ret
= nouveau_bo_new(dev
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 12, 13 << 16, NULL
,
1251 &screen
->uniform_bo
);
1253 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret
);
1255 PUSH_REFN (push
, screen
->uniform_bo
, NV_VRAM_DOMAIN(&screen
->base
) | NOUVEAU_BO_WR
);
1257 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1258 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
1259 PUSH_DATA (push
, 256);
1260 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_RUNOUT_INFO
);
1261 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_RUNOUT_INFO
);
1262 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 5);
1263 PUSH_DATA (push
, 0);
1264 PUSH_DATAf(push
, 0.0f
);
1265 PUSH_DATAf(push
, 0.0f
);
1266 PUSH_DATAf(push
, 0.0f
);
1267 PUSH_DATAf(push
, 0.0f
);
1268 BEGIN_NVC0(push
, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH
), 2);
1269 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_RUNOUT_INFO
);
1270 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_RUNOUT_INFO
);
1272 if (screen
->base
.drm
->version
>= 0x01000101) {
1273 ret
= nouveau_getparam(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
1275 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret
);
1277 if (dev
->chipset
>= 0xe0 && dev
->chipset
< 0xf0)
1278 value
= (8 << 8) | 4;
1280 value
= (16 << 8) | 4;
1282 screen
->gpc_count
= value
& 0x000000ff;
1283 screen
->mp_count
= value
>> 8;
1284 screen
->mp_count_compute
= screen
->mp_count
;
1286 ret
= nvc0_screen_resize_tls_area(screen
, 128 * 16, 0, 0x200);
1288 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret
);
1290 BEGIN_NVC0(push
, NVC0_3D(TEMP_ADDRESS_HIGH
), 4);
1291 PUSH_DATAh(push
, screen
->tls
->offset
);
1292 PUSH_DATA (push
, screen
->tls
->offset
);
1293 PUSH_DATA (push
, screen
->tls
->size
>> 32);
1294 PUSH_DATA (push
, screen
->tls
->size
);
1295 BEGIN_NVC0(push
, NVC0_3D(WARP_TEMP_ALLOC
), 1);
1296 PUSH_DATA (push
, 0);
1297 /* Reduce likelihood of collision with real buffers by placing the hole at
1298 * the top of the 4G area. This will have to be dealt with for real
1299 * eventually by blocking off that area from the VM.
1301 BEGIN_NVC0(push
, NVC0_3D(LOCAL_BASE
), 1);
1302 PUSH_DATA (push
, 0xff << 24);
1304 if (screen
->eng3d
->oclass
< GM107_3D_CLASS
) {
1305 ret
= nouveau_bo_new(dev
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 17, 1 << 20, NULL
,
1306 &screen
->poly_cache
);
1308 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret
);
1310 BEGIN_NVC0(push
, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH
), 3);
1311 PUSH_DATAh(push
, screen
->poly_cache
->offset
);
1312 PUSH_DATA (push
, screen
->poly_cache
->offset
);
1313 PUSH_DATA (push
, 3);
1316 ret
= nouveau_bo_new(dev
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 17, 1 << 17, NULL
,
1319 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret
);
1321 BEGIN_NVC0(push
, NVC0_3D(TIC_ADDRESS_HIGH
), 3);
1322 PUSH_DATAh(push
, screen
->txc
->offset
);
1323 PUSH_DATA (push
, screen
->txc
->offset
);
1324 PUSH_DATA (push
, NVC0_TIC_MAX_ENTRIES
- 1);
1325 if (screen
->eng3d
->oclass
>= GM107_3D_CLASS
) {
1326 screen
->tic
.maxwell
= true;
1327 if (screen
->eng3d
->oclass
== GM107_3D_CLASS
) {
1328 screen
->tic
.maxwell
=
1329 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1330 IMMED_NVC0(push
, SUBC_3D(0x0f10), screen
->tic
.maxwell
);
1334 BEGIN_NVC0(push
, NVC0_3D(TSC_ADDRESS_HIGH
), 3);
1335 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
1336 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
1337 PUSH_DATA (push
, NVC0_TSC_MAX_ENTRIES
- 1);
1339 BEGIN_NVC0(push
, NVC0_3D(SCREEN_Y_CONTROL
), 1);
1340 PUSH_DATA (push
, 0);
1341 BEGIN_NVC0(push
, NVC0_3D(WINDOW_OFFSET_X
), 2);
1342 PUSH_DATA (push
, 0);
1343 PUSH_DATA (push
, 0);
1344 BEGIN_NVC0(push
, NVC0_3D(ZCULL_REGION
), 1); /* deactivate ZCULL */
1345 PUSH_DATA (push
, 0x3f);
1347 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_MODE
), 1);
1348 PUSH_DATA (push
, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
1349 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1350 for (i
= 0; i
< 8 * 2; ++i
)
1352 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_EN
), 1);
1353 PUSH_DATA (push
, 0);
1354 BEGIN_NVC0(push
, NVC0_3D(CLIPID_ENABLE
), 1);
1355 PUSH_DATA (push
, 0);
1357 /* neither scissors, viewport nor stencil mask should affect clears */
1358 BEGIN_NVC0(push
, NVC0_3D(CLEAR_FLAGS
), 1);
1359 PUSH_DATA (push
, 0);
1361 BEGIN_NVC0(push
, NVC0_3D(VIEWPORT_TRANSFORM_EN
), 1);
1362 PUSH_DATA (push
, 1);
1363 for (i
= 0; i
< NVC0_MAX_VIEWPORTS
; i
++) {
1364 BEGIN_NVC0(push
, NVC0_3D(DEPTH_RANGE_NEAR(i
)), 2);
1365 PUSH_DATAf(push
, 0.0f
);
1366 PUSH_DATAf(push
, 1.0f
);
1368 BEGIN_NVC0(push
, NVC0_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
1369 PUSH_DATA (push
, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
);
1371 /* We use scissors instead of exact view volume clipping,
1372 * so they're always enabled.
1374 for (i
= 0; i
< NVC0_MAX_VIEWPORTS
; i
++) {
1375 BEGIN_NVC0(push
, NVC0_3D(SCISSOR_ENABLE(i
)), 3);
1376 PUSH_DATA (push
, 1);
1377 PUSH_DATA (push
, 16384 << 16);
1378 PUSH_DATA (push
, 16384 << 16);
1381 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1384 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE
, mme9097_per_instance_bf
);
1385 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES
, mme9097_blend_enables
);
1386 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT
, mme9097_vertex_array_select
);
1387 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT
, mme9097_tep_select
);
1388 MK_MACRO(NVC0_3D_MACRO_GP_SELECT
, mme9097_gp_select
);
1389 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT
, mme9097_poly_mode_front
);
1390 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK
, mme9097_poly_mode_back
);
1391 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT
, mme9097_draw_arrays_indirect
);
1392 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT
, mme9097_draw_elts_indirect
);
1393 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT
, mme9097_draw_arrays_indirect_count
);
1394 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT
, mme9097_draw_elts_indirect_count
);
1395 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE
, mme9097_query_buffer_write
);
1396 MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE
, mme9097_conservative_raster_state
);
1397 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER
, mme9097_compute_counter
);
1398 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY
, mme9097_compute_counter_to_query
);
1399 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT
, mme90c0_launch_grid_indirect
);
1401 BEGIN_NVC0(push
, NVC0_3D(RASTERIZE_ENABLE
), 1);
1402 PUSH_DATA (push
, 1);
1403 BEGIN_NVC0(push
, NVC0_3D(RT_SEPARATE_FRAG_DATA
), 1);
1404 PUSH_DATA (push
, 1);
1405 BEGIN_NVC0(push
, NVC0_3D(MACRO_GP_SELECT
), 1);
1406 PUSH_DATA (push
, 0x40);
1407 BEGIN_NVC0(push
, NVC0_3D(LAYER
), 1);
1408 PUSH_DATA (push
, 0);
1409 BEGIN_NVC0(push
, NVC0_3D(MACRO_TEP_SELECT
), 1);
1410 PUSH_DATA (push
, 0x30);
1411 BEGIN_NVC0(push
, NVC0_3D(PATCH_VERTICES
), 1);
1412 PUSH_DATA (push
, 3);
1413 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(2)), 1);
1414 PUSH_DATA (push
, 0x20);
1415 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(0)), 1);
1416 PUSH_DATA (push
, 0x00);
1417 screen
->save_state
.patch_vertices
= 3;
1419 BEGIN_NVC0(push
, NVC0_3D(POINT_COORD_REPLACE
), 1);
1420 PUSH_DATA (push
, 0);
1421 BEGIN_NVC0(push
, NVC0_3D(POINT_RASTER_RULES
), 1);
1422 PUSH_DATA (push
, NVC0_3D_POINT_RASTER_RULES_OGL
);
1424 IMMED_NVC0(push
, NVC0_3D(EDGEFLAG
), 1);
1426 if (nvc0_screen_init_compute(screen
))
1429 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1430 for (i
= 0; i
< 5; ++i
) {
1432 for (j
= 0; j
< 16; j
++)
1433 screen
->cb_bindings
[i
][j
].size
= -1;
1435 /* TIC and TSC entries for each unit (nve4+ only) */
1436 /* auxiliary constants (6 user clip planes, base instance id) */
1437 nvc0_screen_bind_cb_3d(screen
, NULL
, i
, 15, NVC0_CB_AUX_SIZE
,
1438 screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(i
));
1439 if (screen
->eng3d
->oclass
>= NVE4_3D_CLASS
) {
1441 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 9);
1442 PUSH_DATA (push
, NVC0_CB_AUX_UNK_INFO
);
1443 for (j
= 0; j
< 8; ++j
)
1446 BEGIN_NVC0(push
, NVC0_3D(TEX_LIMITS(i
)), 1);
1447 PUSH_DATA (push
, 0x54);
1450 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1451 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 1 + 2 * 8);
1452 PUSH_DATA (push
, NVC0_CB_AUX_MS_INFO
);
1453 PUSH_DATA (push
, 0); /* 0 */
1454 PUSH_DATA (push
, 0);
1455 PUSH_DATA (push
, 1); /* 1 */
1456 PUSH_DATA (push
, 0);
1457 PUSH_DATA (push
, 0); /* 2 */
1458 PUSH_DATA (push
, 1);
1459 PUSH_DATA (push
, 1); /* 3 */
1460 PUSH_DATA (push
, 1);
1461 PUSH_DATA (push
, 2); /* 4 */
1462 PUSH_DATA (push
, 0);
1463 PUSH_DATA (push
, 3); /* 5 */
1464 PUSH_DATA (push
, 0);
1465 PUSH_DATA (push
, 2); /* 6 */
1466 PUSH_DATA (push
, 1);
1467 PUSH_DATA (push
, 3); /* 7 */
1468 PUSH_DATA (push
, 1);
1470 BEGIN_NVC0(push
, NVC0_3D(LINKED_TSC
), 1);
1471 PUSH_DATA (push
, 0);
1475 screen
->tic
.entries
= CALLOC(
1476 NVC0_TIC_MAX_ENTRIES
+ NVC0_TSC_MAX_ENTRIES
+ NVE4_IMG_MAX_HANDLES
,
1478 screen
->tsc
.entries
= screen
->tic
.entries
+ NVC0_TIC_MAX_ENTRIES
;
1479 screen
->img
.entries
= (void *)(screen
->tsc
.entries
+ NVC0_TSC_MAX_ENTRIES
);
1481 if (!nvc0_blitter_create(screen
))
1484 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
);
1486 return &screen
->base
;
1489 screen
->base
.base
.context_create
= NULL
;
1490 return &screen
->base
;
1494 nvc0_screen_tic_alloc(struct nvc0_screen
*screen
, void *entry
)
1496 int i
= screen
->tic
.next
;
1498 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
1499 i
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
1501 screen
->tic
.next
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
1503 if (screen
->tic
.entries
[i
])
1504 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
1506 screen
->tic
.entries
[i
] = entry
;
1511 nvc0_screen_tsc_alloc(struct nvc0_screen
*screen
, void *entry
)
1513 int i
= screen
->tsc
.next
;
1515 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
1516 i
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
1518 screen
->tsc
.next
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
1520 if (screen
->tsc
.entries
[i
])
1521 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
1523 screen
->tsc
.entries
[i
] = entry
;