2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <nouveau_drm.h>
25 #include "util/u_format.h"
26 #include "util/u_format_s3tc.h"
27 #include "pipe/p_screen.h"
29 #include "vl/vl_decoder.h"
30 #include "vl/vl_video_buffer.h"
32 #include "nouveau_vp3_video.h"
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_screen.h"
37 #include "nvc0/mme/com9097.mme.h"
40 nvc0_screen_is_format_supported(struct pipe_screen
*pscreen
,
41 enum pipe_format format
,
42 enum pipe_texture_target target
,
43 unsigned sample_count
,
48 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
51 if (!util_format_is_supported(format
, bindings
))
54 if ((bindings
& PIPE_BIND_SAMPLER_VIEW
) && (target
!= PIPE_BUFFER
))
55 if (util_format_get_blocksizebits(format
) == 3 * 32)
58 /* transfers & shared are always supported */
59 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
60 PIPE_BIND_TRANSFER_WRITE
|
63 return (nvc0_format_table
[format
].usage
& bindings
) == bindings
;
67 nvc0_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
69 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
70 struct nouveau_device
*dev
= nouveau_screen(pscreen
)->device
;
73 /* non-boolean caps */
74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
78 return (class_3d
>= NVE4_3D_CLASS
) ? 13 : 12;
79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
81 case PIPE_CAP_MIN_TEXEL_OFFSET
:
83 case PIPE_CAP_MAX_TEXEL_OFFSET
:
85 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
87 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
89 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
90 return 128 * 1024 * 1024;
91 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
93 case PIPE_CAP_MAX_RENDER_TARGETS
:
95 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
97 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
99 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
100 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
102 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
103 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
105 case PIPE_CAP_MAX_VERTEX_STREAMS
:
107 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
109 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
111 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
112 return 1; /* 256 for binding as RT, but that's not possible in GL */
113 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
114 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
115 case PIPE_CAP_MAX_VIEWPORTS
:
116 return NVC0_MAX_VIEWPORTS
;
117 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
119 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
120 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50
;
121 case PIPE_CAP_ENDIANNESS
:
122 return PIPE_ENDIAN_LITTLE
;
123 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
127 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
128 case PIPE_CAP_TEXTURE_SWIZZLE
:
129 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
130 case PIPE_CAP_NPOT_TEXTURES
:
131 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
132 case PIPE_CAP_ANISOTROPIC_FILTER
:
133 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
134 case PIPE_CAP_CUBE_MAP_ARRAY
:
135 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
136 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
137 case PIPE_CAP_TWO_SIDED_STENCIL
:
138 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
139 case PIPE_CAP_POINT_SPRITE
:
140 case PIPE_CAP_TGSI_TEXCOORD
:
142 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
143 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
144 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
145 case PIPE_CAP_QUERY_TIMESTAMP
:
146 case PIPE_CAP_QUERY_TIME_ELAPSED
:
147 case PIPE_CAP_OCCLUSION_QUERY
:
148 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
149 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
150 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
151 case PIPE_CAP_INDEP_BLEND_ENABLE
:
152 case PIPE_CAP_INDEP_BLEND_FUNC
:
153 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
154 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
155 case PIPE_CAP_PRIMITIVE_RESTART
:
156 case PIPE_CAP_TGSI_INSTANCEID
:
157 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
158 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
159 case PIPE_CAP_CONDITIONAL_RENDER
:
160 case PIPE_CAP_TEXTURE_BARRIER
:
161 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
162 case PIPE_CAP_START_INSTANCE
:
163 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
164 case PIPE_CAP_DRAW_INDIRECT
:
165 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
166 case PIPE_CAP_USER_INDEX_BUFFERS
:
167 case PIPE_CAP_USER_VERTEX_BUFFERS
:
168 case PIPE_CAP_TEXTURE_QUERY_LOD
:
169 case PIPE_CAP_SAMPLE_SHADING
:
170 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
171 case PIPE_CAP_TEXTURE_GATHER_SM5
:
172 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
173 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
174 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
175 case PIPE_CAP_CLIP_HALFZ
:
176 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
177 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
178 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
179 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
180 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
181 case PIPE_CAP_TGSI_TXQS
:
182 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
183 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
184 case PIPE_CAP_SHAREABLE_SHADERS
:
185 case PIPE_CAP_CLEAR_TEXTURE
:
187 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
188 return (class_3d
>= NVE4_3D_CLASS
) ? 1 : 0;
189 case PIPE_CAP_COMPUTE
:
190 return (class_3d
<= NVE4_3D_CLASS
) ? 1 : 0;
191 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
192 return nouveau_screen(pscreen
)->vram_domain
& NOUVEAU_BO_VRAM
? 1 : 0;
194 /* unsupported caps */
195 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
196 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
197 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
198 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
199 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
200 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
201 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
202 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
203 case PIPE_CAP_FAKE_SW_MSAA
:
204 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
205 case PIPE_CAP_VERTEXID_NOBASE
:
206 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
207 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
210 case PIPE_CAP_VENDOR_ID
:
212 case PIPE_CAP_DEVICE_ID
: {
214 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
215 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
220 case PIPE_CAP_ACCELERATED
:
222 case PIPE_CAP_VIDEO_MEMORY
:
223 return dev
->vram_size
>> 20;
228 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
233 nvc0_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
234 enum pipe_shader_cap param
)
236 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
239 case PIPE_SHADER_VERTEX
:
240 case PIPE_SHADER_GEOMETRY
:
241 case PIPE_SHADER_FRAGMENT
:
243 case PIPE_SHADER_TESS_CTRL
:
244 case PIPE_SHADER_TESS_EVAL
:
245 if (class_3d
>= GM107_3D_CLASS
)
248 case PIPE_SHADER_COMPUTE
:
249 if (class_3d
> NVE4_3D_CLASS
)
257 case PIPE_SHADER_CAP_PREFERRED_IR
:
258 return PIPE_SHADER_IR_TGSI
;
259 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
260 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
261 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
262 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
264 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
266 case PIPE_SHADER_CAP_MAX_INPUTS
:
267 if (shader
== PIPE_SHADER_VERTEX
)
269 /* NOTE: These only count our slots for GENERIC varyings.
270 * The address space may be larger, but the actual hard limit seems to be
271 * less than what the address space layout permits, so don't add TEXCOORD,
274 if (shader
== PIPE_SHADER_FRAGMENT
)
276 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
277 * and excludes 0x60 per-patch inputs.
280 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
282 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
284 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
285 if (shader
== PIPE_SHADER_COMPUTE
&& class_3d
>= NVE4_3D_CLASS
)
286 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE
;
287 return NVC0_MAX_PIPE_CONSTBUFS
;
288 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
289 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
290 return shader
!= PIPE_SHADER_FRAGMENT
;
291 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
292 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
294 case PIPE_SHADER_CAP_MAX_PREDS
:
296 case PIPE_SHADER_CAP_MAX_TEMPS
:
297 return NVC0_CAP_MAX_PROGRAM_TEMPS
;
298 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
300 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
302 case PIPE_SHADER_CAP_SUBROUTINES
:
304 case PIPE_SHADER_CAP_INTEGERS
:
306 case PIPE_SHADER_CAP_DOUBLES
:
308 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
310 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
311 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
312 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
314 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
315 return 16; /* would be 32 in linked (OpenGL-style) mode */
316 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
317 return 16; /* XXX not sure if more are really safe */
318 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
321 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
327 nvc0_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
330 case PIPE_CAPF_MAX_LINE_WIDTH
:
331 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
333 case PIPE_CAPF_MAX_POINT_WIDTH
:
335 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
337 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
339 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
341 case PIPE_CAPF_GUARD_BAND_LEFT
:
342 case PIPE_CAPF_GUARD_BAND_TOP
:
344 case PIPE_CAPF_GUARD_BAND_RIGHT
:
345 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
346 return 0.0f
; /* that or infinity */
349 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param
);
354 nvc0_screen_get_compute_param(struct pipe_screen
*pscreen
,
355 enum pipe_compute_cap param
, void *data
)
357 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
358 const uint16_t obj_class
= screen
->compute
->oclass
;
360 #define RET(x) do { \
362 memcpy(data, x, sizeof(x)); \
367 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
368 RET((uint64_t []) { 3 });
369 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
370 if (obj_class
>= NVE4_COMPUTE_CLASS
) {
371 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
373 RET(((uint64_t []) { 65535, 65535, 65535 }));
375 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
376 RET(((uint64_t []) { 1024, 1024, 64 }));
377 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
378 RET((uint64_t []) { 1024 });
379 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
: /* g[] */
380 RET((uint64_t []) { 1ULL << 40 });
381 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
: /* s[] */
382 RET((uint64_t []) { 48 << 10 });
383 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
: /* l[] */
384 RET((uint64_t []) { 512 << 10 });
385 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
: /* c[], arbitrary limit */
386 RET((uint64_t []) { 4096 });
387 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
388 RET((uint32_t []) { 32 });
389 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
390 RET((uint64_t []) { 1ULL << 40 });
391 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
392 RET((uint32_t []) { 0 });
393 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
394 RET((uint32_t []) { screen
->mp_count_compute
});
395 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
396 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
405 nvc0_screen_destroy(struct pipe_screen
*pscreen
)
407 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
409 if (!nouveau_drm_screen_unref(&screen
->base
))
412 if (screen
->base
.fence
.current
) {
413 struct nouveau_fence
*current
= NULL
;
415 /* nouveau_fence_wait will create a new current fence, so wait on the
416 * _current_ one, and remove both.
418 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
419 nouveau_fence_wait(current
, NULL
);
420 nouveau_fence_ref(NULL
, ¤t
);
421 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
423 if (screen
->base
.pushbuf
)
424 screen
->base
.pushbuf
->user_priv
= NULL
;
427 nvc0_blitter_destroy(screen
);
428 if (screen
->pm
.prog
) {
429 screen
->pm
.prog
->code
= NULL
; /* hardcoded, don't FREE */
430 nvc0_program_destroy(NULL
, screen
->pm
.prog
);
431 FREE(screen
->pm
.prog
);
434 nouveau_bo_ref(NULL
, &screen
->text
);
435 nouveau_bo_ref(NULL
, &screen
->uniform_bo
);
436 nouveau_bo_ref(NULL
, &screen
->tls
);
437 nouveau_bo_ref(NULL
, &screen
->txc
);
438 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
439 nouveau_bo_ref(NULL
, &screen
->poly_cache
);
440 nouveau_bo_ref(NULL
, &screen
->parm
);
442 nouveau_heap_destroy(&screen
->lib_code
);
443 nouveau_heap_destroy(&screen
->text_heap
);
445 FREE(screen
->tic
.entries
);
447 nouveau_object_del(&screen
->eng3d
);
448 nouveau_object_del(&screen
->eng2d
);
449 nouveau_object_del(&screen
->m2mf
);
450 nouveau_object_del(&screen
->compute
);
451 nouveau_object_del(&screen
->nvsw
);
453 nouveau_screen_fini(&screen
->base
);
459 nvc0_graph_set_macro(struct nvc0_screen
*screen
, uint32_t m
, unsigned pos
,
460 unsigned size
, const uint32_t *data
)
462 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
466 assert((pos
+ size
) <= 0x800);
468 BEGIN_NVC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_ID
), 2);
469 PUSH_DATA (push
, (m
- 0x3800) / 8);
470 PUSH_DATA (push
, pos
);
471 BEGIN_1IC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS
), size
+ 1);
472 PUSH_DATA (push
, pos
);
473 PUSH_DATAp(push
, data
, size
);
479 nvc0_magic_3d_init(struct nouveau_pushbuf
*push
, uint16_t obj_class
)
481 BEGIN_NVC0(push
, SUBC_3D(0x10cc), 1);
482 PUSH_DATA (push
, 0xff);
483 BEGIN_NVC0(push
, SUBC_3D(0x10e0), 2);
484 PUSH_DATA (push
, 0xff);
485 PUSH_DATA (push
, 0xff);
486 BEGIN_NVC0(push
, SUBC_3D(0x10ec), 2);
487 PUSH_DATA (push
, 0xff);
488 PUSH_DATA (push
, 0xff);
489 BEGIN_NVC0(push
, SUBC_3D(0x074c), 1);
490 PUSH_DATA (push
, 0x3f);
492 BEGIN_NVC0(push
, SUBC_3D(0x16a8), 1);
493 PUSH_DATA (push
, (3 << 16) | 3);
494 BEGIN_NVC0(push
, SUBC_3D(0x1794), 1);
495 PUSH_DATA (push
, (2 << 16) | 2);
497 if (obj_class
< GM107_3D_CLASS
) {
498 BEGIN_NVC0(push
, SUBC_3D(0x12ac), 1);
501 BEGIN_NVC0(push
, SUBC_3D(0x0218), 1);
502 PUSH_DATA (push
, 0x10);
503 BEGIN_NVC0(push
, SUBC_3D(0x10fc), 1);
504 PUSH_DATA (push
, 0x10);
505 BEGIN_NVC0(push
, SUBC_3D(0x1290), 1);
506 PUSH_DATA (push
, 0x10);
507 BEGIN_NVC0(push
, SUBC_3D(0x12d8), 2);
508 PUSH_DATA (push
, 0x10);
509 PUSH_DATA (push
, 0x10);
510 BEGIN_NVC0(push
, SUBC_3D(0x1140), 1);
511 PUSH_DATA (push
, 0x10);
512 BEGIN_NVC0(push
, SUBC_3D(0x1610), 1);
513 PUSH_DATA (push
, 0xe);
515 BEGIN_NVC0(push
, NVC0_3D(VERTEX_ID_GEN_MODE
), 1);
516 PUSH_DATA (push
, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START
);
517 BEGIN_NVC0(push
, SUBC_3D(0x030c), 1);
519 BEGIN_NVC0(push
, SUBC_3D(0x0300), 1);
522 BEGIN_NVC0(push
, SUBC_3D(0x02d0), 1);
523 PUSH_DATA (push
, 0x3fffff);
524 BEGIN_NVC0(push
, SUBC_3D(0x0fdc), 1);
526 BEGIN_NVC0(push
, SUBC_3D(0x19c0), 1);
529 if (obj_class
< GM107_3D_CLASS
) {
530 BEGIN_NVC0(push
, SUBC_3D(0x075c), 1);
533 if (obj_class
>= NVE4_3D_CLASS
) {
534 BEGIN_NVC0(push
, SUBC_3D(0x07fc), 1);
539 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
540 * are supposed to do */
544 nvc0_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
546 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
547 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
549 /* we need to do it after possible flush in MARK_RING */
550 *sequence
= ++screen
->base
.fence
.sequence
;
552 assert(PUSH_AVAIL(push
) + push
->rsvd_kick
>= 5);
553 PUSH_DATA (push
, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH
), 4));
554 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
555 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
556 PUSH_DATA (push
, *sequence
);
557 PUSH_DATA (push
, NVC0_3D_QUERY_GET_FENCE
| NVC0_3D_QUERY_GET_SHORT
|
558 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT
));
562 nvc0_screen_fence_update(struct pipe_screen
*pscreen
)
564 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
565 return screen
->fence
.map
[0];
569 nvc0_screen_init_compute(struct nvc0_screen
*screen
)
571 screen
->base
.base
.get_compute_param
= nvc0_screen_get_compute_param
;
573 switch (screen
->base
.device
->chipset
& ~0xf) {
576 return nvc0_screen_compute_setup(screen
, screen
->base
.pushbuf
);
578 return nve4_screen_compute_setup(screen
, screen
->base
.pushbuf
);
589 nvc0_screen_resize_tls_area(struct nvc0_screen
*screen
,
590 uint32_t lpos
, uint32_t lneg
, uint32_t cstack
)
592 struct nouveau_bo
*bo
= NULL
;
594 uint64_t size
= (lpos
+ lneg
) * 32 + cstack
;
596 if (size
>= (1 << 20)) {
597 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64
"\n", size
);
601 size
*= (screen
->base
.device
->chipset
>= 0xe0) ? 64 : 48; /* max warps */
602 size
= align(size
, 0x8000);
603 size
*= screen
->mp_count
;
605 size
= align(size
, 1 << 17);
607 ret
= nouveau_bo_new(screen
->base
.device
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 17, size
,
610 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64
"\n", size
);
613 nouveau_bo_ref(NULL
, &screen
->tls
);
618 #define FAIL_SCREEN_INIT(str, err) \
620 NOUVEAU_ERR(str, err); \
624 struct nouveau_screen
*
625 nvc0_screen_create(struct nouveau_device
*dev
)
627 struct nvc0_screen
*screen
;
628 struct pipe_screen
*pscreen
;
629 struct nouveau_object
*chan
;
630 struct nouveau_pushbuf
*push
;
637 switch (dev
->chipset
& ~0xf) {
649 screen
= CALLOC_STRUCT(nvc0_screen
);
652 pscreen
= &screen
->base
.base
;
653 pscreen
->destroy
= nvc0_screen_destroy
;
655 ret
= nouveau_screen_init(&screen
->base
, dev
);
657 nvc0_screen_destroy(pscreen
);
660 chan
= screen
->base
.channel
;
661 push
= screen
->base
.pushbuf
;
662 push
->user_priv
= screen
;
665 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
666 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
|
667 PIPE_BIND_COMMAND_ARGS_BUFFER
;
668 screen
->base
.sysmem_bindings
|=
669 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
671 if (screen
->base
.vram_domain
& NOUVEAU_BO_GART
) {
672 screen
->base
.sysmem_bindings
|= screen
->base
.vidmem_bindings
;
673 screen
->base
.vidmem_bindings
= 0;
676 pscreen
->context_create
= nvc0_create
;
677 pscreen
->is_format_supported
= nvc0_screen_is_format_supported
;
678 pscreen
->get_param
= nvc0_screen_get_param
;
679 pscreen
->get_shader_param
= nvc0_screen_get_shader_param
;
680 pscreen
->get_paramf
= nvc0_screen_get_paramf
;
681 pscreen
->get_driver_query_info
= nvc0_screen_get_driver_query_info
;
682 pscreen
->get_driver_query_group_info
= nvc0_screen_get_driver_query_group_info
;
684 nvc0_screen_init_resource_functions(pscreen
);
686 screen
->base
.base
.get_video_param
= nouveau_vp3_screen_get_video_param
;
687 screen
->base
.base
.is_video_format_supported
= nouveau_vp3_screen_video_supported
;
689 flags
= NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
;
690 if (screen
->base
.drm
->version
>= 0x01000202)
691 flags
|= NOUVEAU_BO_COHERENT
;
693 ret
= nouveau_bo_new(dev
, flags
, 0, 4096, NULL
, &screen
->fence
.bo
);
696 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
697 screen
->fence
.map
= screen
->fence
.bo
->map
;
698 screen
->base
.fence
.emit
= nvc0_screen_fence_emit
;
699 screen
->base
.fence
.update
= nvc0_screen_fence_update
;
702 ret
= nouveau_object_new(chan
,
703 (dev
->chipset
< 0xe0) ? 0x1f906e : 0x906e, 0x906e,
704 NULL
, 0, &screen
->nvsw
);
706 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret
);
709 switch (dev
->chipset
& ~0xf) {
713 obj_class
= NVF0_P2MF_CLASS
;
716 obj_class
= NVE4_P2MF_CLASS
;
719 obj_class
= NVC0_M2MF_CLASS
;
722 ret
= nouveau_object_new(chan
, 0xbeef323f, obj_class
, NULL
, 0,
725 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret
);
727 BEGIN_NVC0(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
728 PUSH_DATA (push
, screen
->m2mf
->oclass
);
729 if (screen
->m2mf
->oclass
== NVE4_P2MF_CLASS
) {
730 BEGIN_NVC0(push
, SUBC_COPY(NV01_SUBCHAN_OBJECT
), 1);
731 PUSH_DATA (push
, 0xa0b5);
734 ret
= nouveau_object_new(chan
, 0xbeef902d, NVC0_2D_CLASS
, NULL
, 0,
737 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret
);
739 BEGIN_NVC0(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
740 PUSH_DATA (push
, screen
->eng2d
->oclass
);
741 BEGIN_NVC0(push
, SUBC_2D(NVC0_2D_SINGLE_GPC
), 1);
743 BEGIN_NVC0(push
, NVC0_2D(OPERATION
), 1);
744 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY
);
745 BEGIN_NVC0(push
, NVC0_2D(CLIP_ENABLE
), 1);
747 BEGIN_NVC0(push
, NVC0_2D(COLOR_KEY_ENABLE
), 1);
749 BEGIN_NVC0(push
, SUBC_2D(0x0884), 1);
750 PUSH_DATA (push
, 0x3f);
751 BEGIN_NVC0(push
, SUBC_2D(0x0888), 1);
753 BEGIN_NVC0(push
, NVC0_2D(COND_MODE
), 1);
754 PUSH_DATA (push
, NV50_2D_COND_MODE_ALWAYS
);
756 BEGIN_NVC0(push
, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH
), 2);
757 PUSH_DATAh(push
, screen
->fence
.bo
->offset
+ 16);
758 PUSH_DATA (push
, screen
->fence
.bo
->offset
+ 16);
760 switch (dev
->chipset
& ~0xf) {
762 obj_class
= GM107_3D_CLASS
;
766 obj_class
= NVF0_3D_CLASS
;
769 switch (dev
->chipset
) {
771 obj_class
= NVEA_3D_CLASS
;
774 obj_class
= NVE4_3D_CLASS
;
779 obj_class
= NVC8_3D_CLASS
;
783 switch (dev
->chipset
) {
785 obj_class
= NVC8_3D_CLASS
;
788 obj_class
= NVC1_3D_CLASS
;
791 obj_class
= NVC0_3D_CLASS
;
796 ret
= nouveau_object_new(chan
, 0xbeef003d, obj_class
, NULL
, 0,
799 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret
);
800 screen
->base
.class_3d
= obj_class
;
802 BEGIN_NVC0(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
803 PUSH_DATA (push
, screen
->eng3d
->oclass
);
805 BEGIN_NVC0(push
, NVC0_3D(COND_MODE
), 1);
806 PUSH_DATA (push
, NVC0_3D_COND_MODE_ALWAYS
);
808 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
809 /* kill shaders after about 1 second (at 100 MHz) */
810 BEGIN_NVC0(push
, NVC0_3D(WATCHDOG_TIMER
), 1);
811 PUSH_DATA (push
, 0x17);
814 IMMED_NVC0(push
, NVC0_3D(ZETA_COMP_ENABLE
),
815 screen
->base
.drm
->version
>= 0x01000101);
816 BEGIN_NVC0(push
, NVC0_3D(RT_COMP_ENABLE(0)), 8);
817 for (i
= 0; i
< 8; ++i
)
818 PUSH_DATA(push
, screen
->base
.drm
->version
>= 0x01000101);
820 BEGIN_NVC0(push
, NVC0_3D(RT_CONTROL
), 1);
823 BEGIN_NVC0(push
, NVC0_3D(CSAA_ENABLE
), 1);
825 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_ENABLE
), 1);
827 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_MODE
), 1);
828 PUSH_DATA (push
, NVC0_3D_MULTISAMPLE_MODE_MS1
);
829 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_CTRL
), 1);
831 BEGIN_NVC0(push
, NVC0_3D(LINE_WIDTH_SEPARATE
), 1);
833 BEGIN_NVC0(push
, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS
), 1);
835 BEGIN_NVC0(push
, NVC0_3D(BLEND_SEPARATE_ALPHA
), 1);
837 BEGIN_NVC0(push
, NVC0_3D(BLEND_ENABLE_COMMON
), 1);
839 BEGIN_NVC0(push
, NVC0_3D(SHADE_MODEL
), 1);
840 PUSH_DATA (push
, NVC0_3D_SHADE_MODEL_SMOOTH
);
841 if (screen
->eng3d
->oclass
< NVE4_3D_CLASS
) {
842 BEGIN_NVC0(push
, NVC0_3D(TEX_MISC
), 1);
843 PUSH_DATA (push
, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP
);
845 BEGIN_NVC0(push
, NVE4_3D(TEX_CB_INDEX
), 1);
846 PUSH_DATA (push
, 15);
848 BEGIN_NVC0(push
, NVC0_3D(CALL_LIMIT_LOG
), 1);
849 PUSH_DATA (push
, 8); /* 128 */
850 BEGIN_NVC0(push
, NVC0_3D(ZCULL_STATCTRS_ENABLE
), 1);
852 if (screen
->eng3d
->oclass
>= NVC1_3D_CLASS
) {
853 BEGIN_NVC0(push
, NVC0_3D(CACHE_SPLIT
), 1);
854 PUSH_DATA (push
, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1
);
857 nvc0_magic_3d_init(push
, screen
->eng3d
->oclass
);
859 ret
= nouveau_bo_new(dev
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 17, 1 << 20, NULL
,
864 /* XXX: getting a page fault at the end of the code buffer every few
865 * launches, don't use the last 256 bytes to work around them - prefetch ?
867 nouveau_heap_init(&screen
->text_heap
, 0, (1 << 20) - 0x100);
869 ret
= nouveau_bo_new(dev
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 12, 6 << 16, NULL
,
870 &screen
->uniform_bo
);
874 PUSH_REFN (push
, screen
->uniform_bo
, NV_VRAM_DOMAIN(&screen
->base
) | NOUVEAU_BO_WR
);
876 for (i
= 0; i
< 5; ++i
) {
877 /* TIC and TSC entries for each unit (nve4+ only) */
878 /* auxiliary constants (6 user clip planes, base instance id) */
879 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
880 PUSH_DATA (push
, 512);
881 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (i
<< 9));
882 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (i
<< 9));
883 BEGIN_NVC0(push
, NVC0_3D(CB_BIND(i
)), 1);
884 PUSH_DATA (push
, (15 << 4) | 1);
885 if (screen
->eng3d
->oclass
>= NVE4_3D_CLASS
) {
887 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 9);
889 for (j
= 0; j
< 8; ++j
)
892 BEGIN_NVC0(push
, NVC0_3D(TEX_LIMITS(i
)), 1);
893 PUSH_DATA (push
, 0x54);
896 BEGIN_NVC0(push
, NVC0_3D(LINKED_TSC
), 1);
899 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
900 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
901 PUSH_DATA (push
, 256);
902 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
903 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
904 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 5);
906 PUSH_DATAf(push
, 0.0f
);
907 PUSH_DATAf(push
, 0.0f
);
908 PUSH_DATAf(push
, 0.0f
);
909 PUSH_DATAf(push
, 0.0f
);
910 BEGIN_NVC0(push
, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH
), 2);
911 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
912 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
914 if (screen
->base
.drm
->version
>= 0x01000101) {
915 ret
= nouveau_getparam(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
917 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
921 if (dev
->chipset
>= 0xe0 && dev
->chipset
< 0xf0)
922 value
= (8 << 8) | 4;
924 value
= (16 << 8) | 4;
926 screen
->gpc_count
= value
& 0x000000ff;
927 screen
->mp_count
= value
>> 8;
928 screen
->mp_count_compute
= screen
->mp_count
;
930 nvc0_screen_resize_tls_area(screen
, 128 * 16, 0, 0x200);
932 BEGIN_NVC0(push
, NVC0_3D(CODE_ADDRESS_HIGH
), 2);
933 PUSH_DATAh(push
, screen
->text
->offset
);
934 PUSH_DATA (push
, screen
->text
->offset
);
935 BEGIN_NVC0(push
, NVC0_3D(TEMP_ADDRESS_HIGH
), 4);
936 PUSH_DATAh(push
, screen
->tls
->offset
);
937 PUSH_DATA (push
, screen
->tls
->offset
);
938 PUSH_DATA (push
, screen
->tls
->size
>> 32);
939 PUSH_DATA (push
, screen
->tls
->size
);
940 BEGIN_NVC0(push
, NVC0_3D(WARP_TEMP_ALLOC
), 1);
942 BEGIN_NVC0(push
, NVC0_3D(LOCAL_BASE
), 1);
945 if (screen
->eng3d
->oclass
< GM107_3D_CLASS
) {
946 ret
= nouveau_bo_new(dev
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 17, 1 << 20, NULL
,
947 &screen
->poly_cache
);
951 BEGIN_NVC0(push
, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH
), 3);
952 PUSH_DATAh(push
, screen
->poly_cache
->offset
);
953 PUSH_DATA (push
, screen
->poly_cache
->offset
);
957 ret
= nouveau_bo_new(dev
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 17, 1 << 17, NULL
,
962 BEGIN_NVC0(push
, NVC0_3D(TIC_ADDRESS_HIGH
), 3);
963 PUSH_DATAh(push
, screen
->txc
->offset
);
964 PUSH_DATA (push
, screen
->txc
->offset
);
965 PUSH_DATA (push
, NVC0_TIC_MAX_ENTRIES
- 1);
967 BEGIN_NVC0(push
, NVC0_3D(TSC_ADDRESS_HIGH
), 3);
968 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
969 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
970 PUSH_DATA (push
, NVC0_TSC_MAX_ENTRIES
- 1);
972 BEGIN_NVC0(push
, NVC0_3D(SCREEN_Y_CONTROL
), 1);
974 BEGIN_NVC0(push
, NVC0_3D(WINDOW_OFFSET_X
), 2);
977 BEGIN_NVC0(push
, NVC0_3D(ZCULL_REGION
), 1); /* deactivate ZCULL */
978 PUSH_DATA (push
, 0x3f);
980 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_MODE
), 1);
981 PUSH_DATA (push
, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
982 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
983 for (i
= 0; i
< 8 * 2; ++i
)
985 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_EN
), 1);
987 BEGIN_NVC0(push
, NVC0_3D(CLIPID_ENABLE
), 1);
990 /* neither scissors, viewport nor stencil mask should affect clears */
991 BEGIN_NVC0(push
, NVC0_3D(CLEAR_FLAGS
), 1);
994 BEGIN_NVC0(push
, NVC0_3D(VIEWPORT_TRANSFORM_EN
), 1);
996 for (i
= 0; i
< NVC0_MAX_VIEWPORTS
; i
++) {
997 BEGIN_NVC0(push
, NVC0_3D(DEPTH_RANGE_NEAR(i
)), 2);
998 PUSH_DATAf(push
, 0.0f
);
999 PUSH_DATAf(push
, 1.0f
);
1001 BEGIN_NVC0(push
, NVC0_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
1002 PUSH_DATA (push
, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
);
1004 /* We use scissors instead of exact view volume clipping,
1005 * so they're always enabled.
1007 for (i
= 0; i
< NVC0_MAX_VIEWPORTS
; i
++) {
1008 BEGIN_NVC0(push
, NVC0_3D(SCISSOR_ENABLE(i
)), 3);
1009 PUSH_DATA (push
, 1);
1010 PUSH_DATA (push
, 8192 << 16);
1011 PUSH_DATA (push
, 8192 << 16);
1014 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1017 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE
, mme9097_per_instance_bf
);
1018 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES
, mme9097_blend_enables
);
1019 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT
, mme9097_vertex_array_select
);
1020 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT
, mme9097_tep_select
);
1021 MK_MACRO(NVC0_3D_MACRO_GP_SELECT
, mme9097_gp_select
);
1022 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT
, mme9097_poly_mode_front
);
1023 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK
, mme9097_poly_mode_back
);
1024 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT
, mme9097_draw_arrays_indirect
);
1025 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT
, mme9097_draw_elts_indirect
);
1027 BEGIN_NVC0(push
, NVC0_3D(RASTERIZE_ENABLE
), 1);
1028 PUSH_DATA (push
, 1);
1029 BEGIN_NVC0(push
, NVC0_3D(RT_SEPARATE_FRAG_DATA
), 1);
1030 PUSH_DATA (push
, 1);
1031 BEGIN_NVC0(push
, NVC0_3D(MACRO_GP_SELECT
), 1);
1032 PUSH_DATA (push
, 0x40);
1033 BEGIN_NVC0(push
, NVC0_3D(LAYER
), 1);
1034 PUSH_DATA (push
, 0);
1035 BEGIN_NVC0(push
, NVC0_3D(MACRO_TEP_SELECT
), 1);
1036 PUSH_DATA (push
, 0x30);
1037 BEGIN_NVC0(push
, NVC0_3D(PATCH_VERTICES
), 1);
1038 PUSH_DATA (push
, 3);
1039 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(2)), 1);
1040 PUSH_DATA (push
, 0x20);
1041 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(0)), 1);
1042 PUSH_DATA (push
, 0x00);
1043 screen
->save_state
.patch_vertices
= 3;
1045 BEGIN_NVC0(push
, NVC0_3D(POINT_COORD_REPLACE
), 1);
1046 PUSH_DATA (push
, 0);
1047 BEGIN_NVC0(push
, NVC0_3D(POINT_RASTER_RULES
), 1);
1048 PUSH_DATA (push
, NVC0_3D_POINT_RASTER_RULES_OGL
);
1050 IMMED_NVC0(push
, NVC0_3D(EDGEFLAG
), 1);
1052 if (nvc0_screen_init_compute(screen
))
1057 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
1058 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
1060 if (!nvc0_blitter_create(screen
))
1063 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, false);
1065 return &screen
->base
;
1068 screen
->base
.base
.context_create
= NULL
;
1069 return &screen
->base
;
1073 nvc0_screen_tic_alloc(struct nvc0_screen
*screen
, void *entry
)
1075 int i
= screen
->tic
.next
;
1077 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
1078 i
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
1080 screen
->tic
.next
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
1082 if (screen
->tic
.entries
[i
])
1083 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
1085 screen
->tic
.entries
[i
] = entry
;
1090 nvc0_screen_tsc_alloc(struct nvc0_screen
*screen
, void *entry
)
1092 int i
= screen
->tsc
.next
;
1094 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
1095 i
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
1097 screen
->tsc
.next
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
1099 if (screen
->tsc
.entries
[i
])
1100 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
1102 screen
->tsc
.entries
[i
] = entry
;