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gallium: add caps for POSITION and FACE system values
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 if (sample_count > 8)
48 return false;
49 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
50 return false;
51
52 if (!util_format_is_supported(format, bindings))
53 return false;
54
55 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
56 if (util_format_get_blocksizebits(format) == 3 * 32)
57 return false;
58
59 /* transfers & shared are always supported */
60 bindings &= ~(PIPE_BIND_TRANSFER_READ |
61 PIPE_BIND_TRANSFER_WRITE |
62 PIPE_BIND_SHARED);
63
64 return (nvc0_format_table[format].usage & bindings) == bindings;
65 }
66
67 static int
68 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
69 {
70 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
71 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
72
73 switch (param) {
74 /* non-boolean caps */
75 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
76 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
77 return 15;
78 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
79 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
80 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
81 return 2048;
82 case PIPE_CAP_MIN_TEXEL_OFFSET:
83 return -8;
84 case PIPE_CAP_MAX_TEXEL_OFFSET:
85 return 7;
86 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
87 return -32;
88 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
89 return 31;
90 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
91 return 128 * 1024 * 1024;
92 case PIPE_CAP_GLSL_FEATURE_LEVEL:
93 return 410;
94 case PIPE_CAP_MAX_RENDER_TARGETS:
95 return 8;
96 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
97 return 1;
98 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
99 return 4;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
101 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
102 return 128;
103 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
104 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
105 return 1024;
106 case PIPE_CAP_MAX_VERTEX_STREAMS:
107 return 4;
108 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
109 return 2048;
110 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
111 return 256;
112 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
113 return 1; /* 256 for binding as RT, but that's not possible in GL */
114 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
115 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
116 case PIPE_CAP_MAX_VIEWPORTS:
117 return NVC0_MAX_VIEWPORTS;
118 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
119 return 4;
120 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
121 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
122 case PIPE_CAP_ENDIANNESS:
123 return PIPE_ENDIAN_LITTLE;
124 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
125 return 30;
126
127 /* supported caps */
128 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
129 case PIPE_CAP_TEXTURE_SWIZZLE:
130 case PIPE_CAP_TEXTURE_SHADOW_MAP:
131 case PIPE_CAP_NPOT_TEXTURES:
132 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
133 case PIPE_CAP_ANISOTROPIC_FILTER:
134 case PIPE_CAP_SEAMLESS_CUBE_MAP:
135 case PIPE_CAP_CUBE_MAP_ARRAY:
136 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
137 case PIPE_CAP_TEXTURE_MULTISAMPLE:
138 case PIPE_CAP_TWO_SIDED_STENCIL:
139 case PIPE_CAP_DEPTH_CLIP_DISABLE:
140 case PIPE_CAP_POINT_SPRITE:
141 case PIPE_CAP_TGSI_TEXCOORD:
142 case PIPE_CAP_SM3:
143 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
144 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
145 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
146 case PIPE_CAP_QUERY_TIMESTAMP:
147 case PIPE_CAP_QUERY_TIME_ELAPSED:
148 case PIPE_CAP_OCCLUSION_QUERY:
149 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
150 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
151 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
152 case PIPE_CAP_INDEP_BLEND_ENABLE:
153 case PIPE_CAP_INDEP_BLEND_FUNC:
154 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
155 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
156 case PIPE_CAP_PRIMITIVE_RESTART:
157 case PIPE_CAP_TGSI_INSTANCEID:
158 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
159 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
160 case PIPE_CAP_CONDITIONAL_RENDER:
161 case PIPE_CAP_TEXTURE_BARRIER:
162 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
163 case PIPE_CAP_START_INSTANCE:
164 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
165 case PIPE_CAP_DRAW_INDIRECT:
166 case PIPE_CAP_USER_CONSTANT_BUFFERS:
167 case PIPE_CAP_USER_INDEX_BUFFERS:
168 case PIPE_CAP_USER_VERTEX_BUFFERS:
169 case PIPE_CAP_TEXTURE_QUERY_LOD:
170 case PIPE_CAP_SAMPLE_SHADING:
171 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
172 case PIPE_CAP_TEXTURE_GATHER_SM5:
173 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
174 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
175 case PIPE_CAP_SAMPLER_VIEW_TARGET:
176 case PIPE_CAP_CLIP_HALFZ:
177 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
178 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
179 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
180 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
181 case PIPE_CAP_DEPTH_BOUNDS_TEST:
182 case PIPE_CAP_TGSI_TXQS:
183 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
184 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
185 case PIPE_CAP_SHAREABLE_SHADERS:
186 case PIPE_CAP_CLEAR_TEXTURE:
187 case PIPE_CAP_DRAW_PARAMETERS:
188 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
189 case PIPE_CAP_MULTI_DRAW_INDIRECT:
190 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
191 return 1;
192 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
193 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
194 case PIPE_CAP_COMPUTE:
195 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
196 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
197 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
198
199 /* unsupported caps */
200 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
201 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
202 case PIPE_CAP_SHADER_STENCIL_EXPORT:
203 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
204 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
205 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
206 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
207 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
208 case PIPE_CAP_FAKE_SW_MSAA:
209 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
210 case PIPE_CAP_VERTEXID_NOBASE:
211 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
212 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
213 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
214 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
215 return 0;
216
217 case PIPE_CAP_VENDOR_ID:
218 return 0x10de;
219 case PIPE_CAP_DEVICE_ID: {
220 uint64_t device_id;
221 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
222 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
223 return -1;
224 }
225 return device_id;
226 }
227 case PIPE_CAP_ACCELERATED:
228 return 1;
229 case PIPE_CAP_VIDEO_MEMORY:
230 return dev->vram_size >> 20;
231 case PIPE_CAP_UMA:
232 return 0;
233 }
234
235 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
236 return 0;
237 }
238
239 static int
240 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
241 enum pipe_shader_cap param)
242 {
243 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
244
245 switch (shader) {
246 case PIPE_SHADER_VERTEX:
247 case PIPE_SHADER_GEOMETRY:
248 case PIPE_SHADER_FRAGMENT:
249 break;
250 case PIPE_SHADER_TESS_CTRL:
251 case PIPE_SHADER_TESS_EVAL:
252 if (class_3d >= GM107_3D_CLASS)
253 return 0;
254 break;
255 case PIPE_SHADER_COMPUTE:
256 if (class_3d > NVE4_3D_CLASS)
257 return 0;
258 break;
259 default:
260 return 0;
261 }
262
263 switch (param) {
264 case PIPE_SHADER_CAP_PREFERRED_IR:
265 return PIPE_SHADER_IR_TGSI;
266 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
267 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
268 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
269 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
270 return 16384;
271 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
272 return 16;
273 case PIPE_SHADER_CAP_MAX_INPUTS:
274 if (shader == PIPE_SHADER_VERTEX)
275 return 32;
276 /* NOTE: These only count our slots for GENERIC varyings.
277 * The address space may be larger, but the actual hard limit seems to be
278 * less than what the address space layout permits, so don't add TEXCOORD,
279 * COLOR, etc. here.
280 */
281 if (shader == PIPE_SHADER_FRAGMENT)
282 return 0x1f0 / 16;
283 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
284 * and excludes 0x60 per-patch inputs.
285 */
286 return 0x200 / 16;
287 case PIPE_SHADER_CAP_MAX_OUTPUTS:
288 return 32;
289 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
290 return 65536;
291 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
292 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
293 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
294 return NVC0_MAX_PIPE_CONSTBUFS;
295 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
296 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
297 return shader != PIPE_SHADER_FRAGMENT;
298 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
299 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
300 return 1;
301 case PIPE_SHADER_CAP_MAX_PREDS:
302 return 0;
303 case PIPE_SHADER_CAP_MAX_TEMPS:
304 return NVC0_CAP_MAX_PROGRAM_TEMPS;
305 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
306 return 1;
307 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
308 return 0;
309 case PIPE_SHADER_CAP_SUBROUTINES:
310 return 1;
311 case PIPE_SHADER_CAP_INTEGERS:
312 return 1;
313 case PIPE_SHADER_CAP_DOUBLES:
314 return 1;
315 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
316 return 1;
317 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
318 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
319 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
320 return 0;
321 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
322 return 16; /* would be 32 in linked (OpenGL-style) mode */
323 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
324 return 16; /* XXX not sure if more are really safe */
325 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
326 return 32;
327 default:
328 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
329 return 0;
330 }
331 }
332
333 static float
334 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
335 {
336 switch (param) {
337 case PIPE_CAPF_MAX_LINE_WIDTH:
338 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
339 return 10.0f;
340 case PIPE_CAPF_MAX_POINT_WIDTH:
341 return 63.0f;
342 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
343 return 63.375f;
344 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
345 return 16.0f;
346 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
347 return 15.0f;
348 case PIPE_CAPF_GUARD_BAND_LEFT:
349 case PIPE_CAPF_GUARD_BAND_TOP:
350 return 0.0f;
351 case PIPE_CAPF_GUARD_BAND_RIGHT:
352 case PIPE_CAPF_GUARD_BAND_BOTTOM:
353 return 0.0f; /* that or infinity */
354 }
355
356 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
357 return 0.0f;
358 }
359
360 static int
361 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
362 enum pipe_compute_cap param, void *data)
363 {
364 struct nvc0_screen *screen = nvc0_screen(pscreen);
365 const uint16_t obj_class = screen->compute->oclass;
366
367 #define RET(x) do { \
368 if (data) \
369 memcpy(data, x, sizeof(x)); \
370 return sizeof(x); \
371 } while (0)
372
373 switch (param) {
374 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
375 RET((uint64_t []) { 3 });
376 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
377 if (obj_class >= NVE4_COMPUTE_CLASS) {
378 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
379 } else {
380 RET(((uint64_t []) { 65535, 65535, 65535 }));
381 }
382 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
383 RET(((uint64_t []) { 1024, 1024, 64 }));
384 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
385 RET((uint64_t []) { 1024 });
386 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
387 RET((uint64_t []) { 1ULL << 40 });
388 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
389 RET((uint64_t []) { 48 << 10 });
390 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
391 RET((uint64_t []) { 512 << 10 });
392 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
393 RET((uint64_t []) { 4096 });
394 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
395 RET((uint32_t []) { 32 });
396 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
397 RET((uint64_t []) { 1ULL << 40 });
398 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
399 RET((uint32_t []) { 0 });
400 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
401 RET((uint32_t []) { screen->mp_count_compute });
402 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
403 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
404 default:
405 return 0;
406 }
407
408 #undef RET
409 }
410
411 static void
412 nvc0_screen_destroy(struct pipe_screen *pscreen)
413 {
414 struct nvc0_screen *screen = nvc0_screen(pscreen);
415
416 if (!nouveau_drm_screen_unref(&screen->base))
417 return;
418
419 if (screen->base.fence.current) {
420 struct nouveau_fence *current = NULL;
421
422 /* nouveau_fence_wait will create a new current fence, so wait on the
423 * _current_ one, and remove both.
424 */
425 nouveau_fence_ref(screen->base.fence.current, &current);
426 nouveau_fence_wait(current, NULL);
427 nouveau_fence_ref(NULL, &current);
428 nouveau_fence_ref(NULL, &screen->base.fence.current);
429 }
430 if (screen->base.pushbuf)
431 screen->base.pushbuf->user_priv = NULL;
432
433 if (screen->blitter)
434 nvc0_blitter_destroy(screen);
435 if (screen->pm.prog) {
436 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
437 nvc0_program_destroy(NULL, screen->pm.prog);
438 FREE(screen->pm.prog);
439 }
440
441 nouveau_bo_ref(NULL, &screen->text);
442 nouveau_bo_ref(NULL, &screen->uniform_bo);
443 nouveau_bo_ref(NULL, &screen->tls);
444 nouveau_bo_ref(NULL, &screen->txc);
445 nouveau_bo_ref(NULL, &screen->fence.bo);
446 nouveau_bo_ref(NULL, &screen->poly_cache);
447 nouveau_bo_ref(NULL, &screen->parm);
448
449 nouveau_heap_destroy(&screen->lib_code);
450 nouveau_heap_destroy(&screen->text_heap);
451
452 FREE(screen->tic.entries);
453
454 nouveau_object_del(&screen->eng3d);
455 nouveau_object_del(&screen->eng2d);
456 nouveau_object_del(&screen->m2mf);
457 nouveau_object_del(&screen->compute);
458 nouveau_object_del(&screen->nvsw);
459
460 nouveau_screen_fini(&screen->base);
461
462 FREE(screen);
463 }
464
465 static int
466 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
467 unsigned size, const uint32_t *data)
468 {
469 struct nouveau_pushbuf *push = screen->base.pushbuf;
470
471 size /= 4;
472
473 assert((pos + size) <= 0x800);
474
475 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
476 PUSH_DATA (push, (m - 0x3800) / 8);
477 PUSH_DATA (push, pos);
478 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
479 PUSH_DATA (push, pos);
480 PUSH_DATAp(push, data, size);
481
482 return pos + size;
483 }
484
485 static void
486 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
487 {
488 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
489 PUSH_DATA (push, 0xff);
490 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
491 PUSH_DATA (push, 0xff);
492 PUSH_DATA (push, 0xff);
493 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
494 PUSH_DATA (push, 0xff);
495 PUSH_DATA (push, 0xff);
496 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
497 PUSH_DATA (push, 0x3f);
498
499 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
500 PUSH_DATA (push, (3 << 16) | 3);
501 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
502 PUSH_DATA (push, (2 << 16) | 2);
503
504 if (obj_class < GM107_3D_CLASS) {
505 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
506 PUSH_DATA (push, 0);
507 }
508 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
509 PUSH_DATA (push, 0x10);
510 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
511 PUSH_DATA (push, 0x10);
512 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
513 PUSH_DATA (push, 0x10);
514 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
515 PUSH_DATA (push, 0x10);
516 PUSH_DATA (push, 0x10);
517 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
518 PUSH_DATA (push, 0x10);
519 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
520 PUSH_DATA (push, 0xe);
521
522 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
523 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
524 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
525 PUSH_DATA (push, 0);
526 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
527 PUSH_DATA (push, 3);
528
529 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
530 PUSH_DATA (push, 0x3fffff);
531 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
532 PUSH_DATA (push, 1);
533 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
534 PUSH_DATA (push, 1);
535
536 if (obj_class < GM107_3D_CLASS) {
537 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
538 PUSH_DATA (push, 3);
539
540 if (obj_class >= NVE4_3D_CLASS) {
541 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
542 PUSH_DATA (push, 1);
543 }
544 }
545
546 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
547 * are supposed to do */
548 }
549
550 static void
551 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
552 {
553 struct nvc0_screen *screen = nvc0_screen(pscreen);
554 struct nouveau_pushbuf *push = screen->base.pushbuf;
555
556 /* we need to do it after possible flush in MARK_RING */
557 *sequence = ++screen->base.fence.sequence;
558
559 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
560 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
561 PUSH_DATAh(push, screen->fence.bo->offset);
562 PUSH_DATA (push, screen->fence.bo->offset);
563 PUSH_DATA (push, *sequence);
564 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
565 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
566 }
567
568 static u32
569 nvc0_screen_fence_update(struct pipe_screen *pscreen)
570 {
571 struct nvc0_screen *screen = nvc0_screen(pscreen);
572 return screen->fence.map[0];
573 }
574
575 static int
576 nvc0_screen_init_compute(struct nvc0_screen *screen)
577 {
578 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
579
580 switch (screen->base.device->chipset & ~0xf) {
581 case 0xc0:
582 case 0xd0:
583 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
584 case 0xe0:
585 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
586 case 0xf0:
587 case 0x100:
588 case 0x110:
589 return 0;
590 default:
591 return -1;
592 }
593 }
594
595 bool
596 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
597 uint32_t lpos, uint32_t lneg, uint32_t cstack)
598 {
599 struct nouveau_bo *bo = NULL;
600 int ret;
601 uint64_t size = (lpos + lneg) * 32 + cstack;
602
603 if (size >= (1 << 20)) {
604 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
605 return false;
606 }
607
608 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
609 size = align(size, 0x8000);
610 size *= screen->mp_count;
611
612 size = align(size, 1 << 17);
613
614 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
615 NULL, &bo);
616 if (ret) {
617 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
618 return false;
619 }
620 nouveau_bo_ref(NULL, &screen->tls);
621 screen->tls = bo;
622 return true;
623 }
624
625 #define FAIL_SCREEN_INIT(str, err) \
626 do { \
627 NOUVEAU_ERR(str, err); \
628 goto fail; \
629 } while(0)
630
631 struct nouveau_screen *
632 nvc0_screen_create(struct nouveau_device *dev)
633 {
634 struct nvc0_screen *screen;
635 struct pipe_screen *pscreen;
636 struct nouveau_object *chan;
637 struct nouveau_pushbuf *push;
638 uint64_t value;
639 uint32_t obj_class;
640 uint32_t flags;
641 int ret;
642 unsigned i;
643
644 switch (dev->chipset & ~0xf) {
645 case 0xc0:
646 case 0xd0:
647 case 0xe0:
648 case 0xf0:
649 case 0x100:
650 case 0x110:
651 break;
652 default:
653 return NULL;
654 }
655
656 screen = CALLOC_STRUCT(nvc0_screen);
657 if (!screen)
658 return NULL;
659 pscreen = &screen->base.base;
660 pscreen->destroy = nvc0_screen_destroy;
661
662 ret = nouveau_screen_init(&screen->base, dev);
663 if (ret) {
664 nvc0_screen_destroy(pscreen);
665 return NULL;
666 }
667 chan = screen->base.channel;
668 push = screen->base.pushbuf;
669 push->user_priv = screen;
670 push->rsvd_kick = 5;
671
672 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
673 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
674 PIPE_BIND_COMMAND_ARGS_BUFFER;
675 screen->base.sysmem_bindings |=
676 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
677
678 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
679 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
680 screen->base.vidmem_bindings = 0;
681 }
682
683 pscreen->context_create = nvc0_create;
684 pscreen->is_format_supported = nvc0_screen_is_format_supported;
685 pscreen->get_param = nvc0_screen_get_param;
686 pscreen->get_shader_param = nvc0_screen_get_shader_param;
687 pscreen->get_paramf = nvc0_screen_get_paramf;
688 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
689 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
690
691 nvc0_screen_init_resource_functions(pscreen);
692
693 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
694 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
695
696 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
697 if (screen->base.drm->version >= 0x01000202)
698 flags |= NOUVEAU_BO_COHERENT;
699
700 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
701 if (ret)
702 goto fail;
703 nouveau_bo_map(screen->fence.bo, 0, NULL);
704 screen->fence.map = screen->fence.bo->map;
705 screen->base.fence.emit = nvc0_screen_fence_emit;
706 screen->base.fence.update = nvc0_screen_fence_update;
707
708
709 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
710 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
711 if (ret)
712 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
713
714 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
715 PUSH_DATA (push, screen->nvsw->handle);
716
717 switch (dev->chipset & ~0xf) {
718 case 0x110:
719 case 0x100:
720 case 0xf0:
721 obj_class = NVF0_P2MF_CLASS;
722 break;
723 case 0xe0:
724 obj_class = NVE4_P2MF_CLASS;
725 break;
726 default:
727 obj_class = NVC0_M2MF_CLASS;
728 break;
729 }
730 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
731 &screen->m2mf);
732 if (ret)
733 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
734
735 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
736 PUSH_DATA (push, screen->m2mf->oclass);
737 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
738 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
739 PUSH_DATA (push, 0xa0b5);
740 }
741
742 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
743 &screen->eng2d);
744 if (ret)
745 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
746
747 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
748 PUSH_DATA (push, screen->eng2d->oclass);
749 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
750 PUSH_DATA (push, 0);
751 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
752 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
753 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
754 PUSH_DATA (push, 0);
755 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
756 PUSH_DATA (push, 0);
757 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
758 PUSH_DATA (push, 0x3f);
759 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
760 PUSH_DATA (push, 1);
761 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
762 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
763
764 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
765 PUSH_DATAh(push, screen->fence.bo->offset + 16);
766 PUSH_DATA (push, screen->fence.bo->offset + 16);
767
768 switch (dev->chipset & ~0xf) {
769 case 0x110:
770 obj_class = GM107_3D_CLASS;
771 break;
772 case 0x100:
773 case 0xf0:
774 obj_class = NVF0_3D_CLASS;
775 break;
776 case 0xe0:
777 switch (dev->chipset) {
778 case 0xea:
779 obj_class = NVEA_3D_CLASS;
780 break;
781 default:
782 obj_class = NVE4_3D_CLASS;
783 break;
784 }
785 break;
786 case 0xd0:
787 obj_class = NVC8_3D_CLASS;
788 break;
789 case 0xc0:
790 default:
791 switch (dev->chipset) {
792 case 0xc8:
793 obj_class = NVC8_3D_CLASS;
794 break;
795 case 0xc1:
796 obj_class = NVC1_3D_CLASS;
797 break;
798 default:
799 obj_class = NVC0_3D_CLASS;
800 break;
801 }
802 break;
803 }
804 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
805 &screen->eng3d);
806 if (ret)
807 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
808 screen->base.class_3d = obj_class;
809
810 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
811 PUSH_DATA (push, screen->eng3d->oclass);
812
813 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
814 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
815
816 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
817 /* kill shaders after about 1 second (at 100 MHz) */
818 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
819 PUSH_DATA (push, 0x17);
820 }
821
822 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
823 screen->base.drm->version >= 0x01000101);
824 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
825 for (i = 0; i < 8; ++i)
826 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
827
828 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
829 PUSH_DATA (push, 1);
830
831 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
832 PUSH_DATA (push, 0);
833 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
834 PUSH_DATA (push, 0);
835 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
836 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
837 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
838 PUSH_DATA (push, 0);
839 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
840 PUSH_DATA (push, 1);
841 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
842 PUSH_DATA (push, 1);
843 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
844 PUSH_DATA (push, 1);
845 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
846 PUSH_DATA (push, 0);
847 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
848 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
849 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
850 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
851 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
852 } else {
853 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
854 PUSH_DATA (push, 15);
855 }
856 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
857 PUSH_DATA (push, 8); /* 128 */
858 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
859 PUSH_DATA (push, 1);
860 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
861 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
862 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
863 }
864
865 nvc0_magic_3d_init(push, screen->eng3d->oclass);
866
867 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
868 &screen->text);
869 if (ret)
870 goto fail;
871
872 /* XXX: getting a page fault at the end of the code buffer every few
873 * launches, don't use the last 256 bytes to work around them - prefetch ?
874 */
875 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
876
877 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
878 &screen->uniform_bo);
879 if (ret)
880 goto fail;
881
882 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
883
884 for (i = 0; i < 5; ++i) {
885 /* TIC and TSC entries for each unit (nve4+ only) */
886 /* auxiliary constants (6 user clip planes, base instance id) */
887 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
888 PUSH_DATA (push, 512);
889 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
890 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
891 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
892 PUSH_DATA (push, (15 << 4) | 1);
893 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
894 unsigned j;
895 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
896 PUSH_DATA (push, 0);
897 for (j = 0; j < 8; ++j)
898 PUSH_DATA(push, j);
899 } else {
900 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
901 PUSH_DATA (push, 0x54);
902 }
903 }
904 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
905 PUSH_DATA (push, 0);
906
907 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
908 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
909 PUSH_DATA (push, 256);
910 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
911 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
912 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
913 PUSH_DATA (push, 0);
914 PUSH_DATAf(push, 0.0f);
915 PUSH_DATAf(push, 0.0f);
916 PUSH_DATAf(push, 0.0f);
917 PUSH_DATAf(push, 0.0f);
918 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
919 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
920 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
921
922 if (screen->base.drm->version >= 0x01000101) {
923 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
924 if (ret) {
925 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
926 goto fail;
927 }
928 } else {
929 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
930 value = (8 << 8) | 4;
931 else
932 value = (16 << 8) | 4;
933 }
934 screen->gpc_count = value & 0x000000ff;
935 screen->mp_count = value >> 8;
936 screen->mp_count_compute = screen->mp_count;
937
938 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
939
940 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
941 PUSH_DATAh(push, screen->text->offset);
942 PUSH_DATA (push, screen->text->offset);
943 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
944 PUSH_DATAh(push, screen->tls->offset);
945 PUSH_DATA (push, screen->tls->offset);
946 PUSH_DATA (push, screen->tls->size >> 32);
947 PUSH_DATA (push, screen->tls->size);
948 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
949 PUSH_DATA (push, 0);
950 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
951 PUSH_DATA (push, 0);
952
953 if (screen->eng3d->oclass < GM107_3D_CLASS) {
954 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
955 &screen->poly_cache);
956 if (ret)
957 goto fail;
958
959 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
960 PUSH_DATAh(push, screen->poly_cache->offset);
961 PUSH_DATA (push, screen->poly_cache->offset);
962 PUSH_DATA (push, 3);
963 }
964
965 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
966 &screen->txc);
967 if (ret)
968 goto fail;
969
970 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
971 PUSH_DATAh(push, screen->txc->offset);
972 PUSH_DATA (push, screen->txc->offset);
973 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
974
975 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
976 PUSH_DATAh(push, screen->txc->offset + 65536);
977 PUSH_DATA (push, screen->txc->offset + 65536);
978 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
979
980 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
981 PUSH_DATA (push, 0);
982 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
983 PUSH_DATA (push, 0);
984 PUSH_DATA (push, 0);
985 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
986 PUSH_DATA (push, 0x3f);
987
988 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
989 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
990 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
991 for (i = 0; i < 8 * 2; ++i)
992 PUSH_DATA(push, 0);
993 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
994 PUSH_DATA (push, 0);
995 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
996 PUSH_DATA (push, 0);
997
998 /* neither scissors, viewport nor stencil mask should affect clears */
999 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1000 PUSH_DATA (push, 0);
1001
1002 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1003 PUSH_DATA (push, 1);
1004 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1005 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1006 PUSH_DATAf(push, 0.0f);
1007 PUSH_DATAf(push, 1.0f);
1008 }
1009 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1010 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1011
1012 /* We use scissors instead of exact view volume clipping,
1013 * so they're always enabled.
1014 */
1015 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1016 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1017 PUSH_DATA (push, 1);
1018 PUSH_DATA (push, 8192 << 16);
1019 PUSH_DATA (push, 8192 << 16);
1020 }
1021
1022 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1023
1024 i = 0;
1025 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1026 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1027 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1028 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1029 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1030 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1031 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1032 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1033 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1034 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1035 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1036
1037 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1038 PUSH_DATA (push, 1);
1039 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1040 PUSH_DATA (push, 1);
1041 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1042 PUSH_DATA (push, 0x40);
1043 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1044 PUSH_DATA (push, 0);
1045 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1046 PUSH_DATA (push, 0x30);
1047 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1048 PUSH_DATA (push, 3);
1049 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1050 PUSH_DATA (push, 0x20);
1051 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1052 PUSH_DATA (push, 0x00);
1053 screen->save_state.patch_vertices = 3;
1054
1055 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1056 PUSH_DATA (push, 0);
1057 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1058 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1059
1060 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1061
1062 if (nvc0_screen_init_compute(screen))
1063 goto fail;
1064
1065 PUSH_KICK (push);
1066
1067 screen->tic.entries = CALLOC(4096, sizeof(void *));
1068 screen->tsc.entries = screen->tic.entries + 2048;
1069
1070 if (!nvc0_blitter_create(screen))
1071 goto fail;
1072
1073 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1074
1075 return &screen->base;
1076
1077 fail:
1078 screen->base.base.context_create = NULL;
1079 return &screen->base;
1080 }
1081
1082 int
1083 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1084 {
1085 int i = screen->tic.next;
1086
1087 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1088 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1089
1090 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1091
1092 if (screen->tic.entries[i])
1093 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1094
1095 screen->tic.entries[i] = entry;
1096 return i;
1097 }
1098
1099 int
1100 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1101 {
1102 int i = screen->tsc.next;
1103
1104 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1105 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1106
1107 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1108
1109 if (screen->tsc.entries[i])
1110 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1111
1112 screen->tsc.entries[i] = entry;
1113 return i;
1114 }