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gallium: Add PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 if (sample_count > 8)
48 return false;
49 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
50 return false;
51
52 if (!util_format_is_supported(format, bindings))
53 return false;
54
55 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
56 if (util_format_get_blocksizebits(format) == 3 * 32)
57 return false;
58
59 /* transfers & shared are always supported */
60 bindings &= ~(PIPE_BIND_TRANSFER_READ |
61 PIPE_BIND_TRANSFER_WRITE |
62 PIPE_BIND_SHARED);
63
64 return (nvc0_format_table[format].usage & bindings) == bindings;
65 }
66
67 static int
68 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
69 {
70 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
71 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
72
73 switch (param) {
74 /* non-boolean caps */
75 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
76 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
77 return 15;
78 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
79 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
80 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
81 return 2048;
82 case PIPE_CAP_MIN_TEXEL_OFFSET:
83 return -8;
84 case PIPE_CAP_MAX_TEXEL_OFFSET:
85 return 7;
86 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
87 return -32;
88 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
89 return 31;
90 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
91 return 128 * 1024 * 1024;
92 case PIPE_CAP_GLSL_FEATURE_LEVEL:
93 return 410;
94 case PIPE_CAP_MAX_RENDER_TARGETS:
95 return 8;
96 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
97 return 1;
98 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
99 return 4;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
101 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
102 return 128;
103 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
104 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
105 return 1024;
106 case PIPE_CAP_MAX_VERTEX_STREAMS:
107 return 4;
108 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
109 return 2048;
110 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
111 return 256;
112 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
113 return 1; /* 256 for binding as RT, but that's not possible in GL */
114 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
115 return 16;
116 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
117 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
118 case PIPE_CAP_MAX_VIEWPORTS:
119 return NVC0_MAX_VIEWPORTS;
120 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
121 return 4;
122 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
123 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
124 case PIPE_CAP_ENDIANNESS:
125 return PIPE_ENDIAN_LITTLE;
126 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
127 return 30;
128
129 /* supported caps */
130 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
131 case PIPE_CAP_TEXTURE_SWIZZLE:
132 case PIPE_CAP_TEXTURE_SHADOW_MAP:
133 case PIPE_CAP_NPOT_TEXTURES:
134 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
135 case PIPE_CAP_ANISOTROPIC_FILTER:
136 case PIPE_CAP_SEAMLESS_CUBE_MAP:
137 case PIPE_CAP_CUBE_MAP_ARRAY:
138 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
139 case PIPE_CAP_TEXTURE_MULTISAMPLE:
140 case PIPE_CAP_TWO_SIDED_STENCIL:
141 case PIPE_CAP_DEPTH_CLIP_DISABLE:
142 case PIPE_CAP_POINT_SPRITE:
143 case PIPE_CAP_TGSI_TEXCOORD:
144 case PIPE_CAP_SM3:
145 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
146 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
147 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
148 case PIPE_CAP_QUERY_TIMESTAMP:
149 case PIPE_CAP_QUERY_TIME_ELAPSED:
150 case PIPE_CAP_OCCLUSION_QUERY:
151 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
152 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
153 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
154 case PIPE_CAP_INDEP_BLEND_ENABLE:
155 case PIPE_CAP_INDEP_BLEND_FUNC:
156 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
157 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
158 case PIPE_CAP_PRIMITIVE_RESTART:
159 case PIPE_CAP_TGSI_INSTANCEID:
160 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
161 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
162 case PIPE_CAP_CONDITIONAL_RENDER:
163 case PIPE_CAP_TEXTURE_BARRIER:
164 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
165 case PIPE_CAP_START_INSTANCE:
166 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
167 case PIPE_CAP_DRAW_INDIRECT:
168 case PIPE_CAP_USER_CONSTANT_BUFFERS:
169 case PIPE_CAP_USER_INDEX_BUFFERS:
170 case PIPE_CAP_USER_VERTEX_BUFFERS:
171 case PIPE_CAP_TEXTURE_QUERY_LOD:
172 case PIPE_CAP_SAMPLE_SHADING:
173 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
174 case PIPE_CAP_TEXTURE_GATHER_SM5:
175 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
176 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
177 case PIPE_CAP_SAMPLER_VIEW_TARGET:
178 case PIPE_CAP_CLIP_HALFZ:
179 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
180 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
181 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
182 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
183 case PIPE_CAP_DEPTH_BOUNDS_TEST:
184 case PIPE_CAP_TGSI_TXQS:
185 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
186 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
187 case PIPE_CAP_SHAREABLE_SHADERS:
188 case PIPE_CAP_CLEAR_TEXTURE:
189 case PIPE_CAP_DRAW_PARAMETERS:
190 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
191 case PIPE_CAP_MULTI_DRAW_INDIRECT:
192 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
193 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
194 return 1;
195 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
196 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
197 case PIPE_CAP_COMPUTE:
198 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
199 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
200 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
201
202 /* unsupported caps */
203 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
204 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
205 case PIPE_CAP_SHADER_STENCIL_EXPORT:
206 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
207 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
208 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
209 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
210 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
211 case PIPE_CAP_FAKE_SW_MSAA:
212 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
213 case PIPE_CAP_VERTEXID_NOBASE:
214 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
215 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
216 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
217 case PIPE_CAP_INVALIDATE_BUFFER:
218 case PIPE_CAP_GENERATE_MIPMAP:
219 case PIPE_CAP_STRING_MARKER:
220 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
221 return 0;
222
223 case PIPE_CAP_VENDOR_ID:
224 return 0x10de;
225 case PIPE_CAP_DEVICE_ID: {
226 uint64_t device_id;
227 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
228 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
229 return -1;
230 }
231 return device_id;
232 }
233 case PIPE_CAP_ACCELERATED:
234 return 1;
235 case PIPE_CAP_VIDEO_MEMORY:
236 return dev->vram_size >> 20;
237 case PIPE_CAP_UMA:
238 return 0;
239 }
240
241 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
242 return 0;
243 }
244
245 static int
246 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
247 enum pipe_shader_cap param)
248 {
249 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
250
251 switch (shader) {
252 case PIPE_SHADER_VERTEX:
253 case PIPE_SHADER_GEOMETRY:
254 case PIPE_SHADER_FRAGMENT:
255 break;
256 case PIPE_SHADER_TESS_CTRL:
257 case PIPE_SHADER_TESS_EVAL:
258 if (class_3d >= GM107_3D_CLASS)
259 return 0;
260 break;
261 case PIPE_SHADER_COMPUTE:
262 if (class_3d > NVE4_3D_CLASS)
263 return 0;
264 break;
265 default:
266 return 0;
267 }
268
269 switch (param) {
270 case PIPE_SHADER_CAP_PREFERRED_IR:
271 return PIPE_SHADER_IR_TGSI;
272 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
273 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
274 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
275 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
276 return 16384;
277 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
278 return 16;
279 case PIPE_SHADER_CAP_MAX_INPUTS:
280 if (shader == PIPE_SHADER_VERTEX)
281 return 32;
282 /* NOTE: These only count our slots for GENERIC varyings.
283 * The address space may be larger, but the actual hard limit seems to be
284 * less than what the address space layout permits, so don't add TEXCOORD,
285 * COLOR, etc. here.
286 */
287 if (shader == PIPE_SHADER_FRAGMENT)
288 return 0x1f0 / 16;
289 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
290 * and excludes 0x60 per-patch inputs.
291 */
292 return 0x200 / 16;
293 case PIPE_SHADER_CAP_MAX_OUTPUTS:
294 return 32;
295 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
296 return 65536;
297 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
298 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
299 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
300 return NVC0_MAX_PIPE_CONSTBUFS;
301 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
302 return shader != PIPE_SHADER_FRAGMENT;
303 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
304 return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
305 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
306 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
307 return 1;
308 case PIPE_SHADER_CAP_MAX_PREDS:
309 return 0;
310 case PIPE_SHADER_CAP_MAX_TEMPS:
311 return NVC0_CAP_MAX_PROGRAM_TEMPS;
312 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
313 return 1;
314 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
315 return 0;
316 case PIPE_SHADER_CAP_SUBROUTINES:
317 return 1;
318 case PIPE_SHADER_CAP_INTEGERS:
319 return 1;
320 case PIPE_SHADER_CAP_DOUBLES:
321 return 1;
322 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
323 return 1;
324 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
325 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
326 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
327 return 0;
328 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
329 return NVC0_MAX_BUFFERS;
330 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
331 return 16; /* would be 32 in linked (OpenGL-style) mode */
332 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
333 return 16; /* XXX not sure if more are really safe */
334 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
335 return 32;
336 default:
337 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
338 return 0;
339 }
340 }
341
342 static float
343 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
344 {
345 switch (param) {
346 case PIPE_CAPF_MAX_LINE_WIDTH:
347 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
348 return 10.0f;
349 case PIPE_CAPF_MAX_POINT_WIDTH:
350 return 63.0f;
351 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
352 return 63.375f;
353 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
354 return 16.0f;
355 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
356 return 15.0f;
357 case PIPE_CAPF_GUARD_BAND_LEFT:
358 case PIPE_CAPF_GUARD_BAND_TOP:
359 return 0.0f;
360 case PIPE_CAPF_GUARD_BAND_RIGHT:
361 case PIPE_CAPF_GUARD_BAND_BOTTOM:
362 return 0.0f; /* that or infinity */
363 }
364
365 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
366 return 0.0f;
367 }
368
369 static int
370 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
371 enum pipe_compute_cap param, void *data)
372 {
373 struct nvc0_screen *screen = nvc0_screen(pscreen);
374 const uint16_t obj_class = screen->compute->oclass;
375
376 #define RET(x) do { \
377 if (data) \
378 memcpy(data, x, sizeof(x)); \
379 return sizeof(x); \
380 } while (0)
381
382 switch (param) {
383 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
384 RET((uint64_t []) { 3 });
385 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
386 if (obj_class >= NVE4_COMPUTE_CLASS) {
387 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
388 } else {
389 RET(((uint64_t []) { 65535, 65535, 65535 }));
390 }
391 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
392 RET(((uint64_t []) { 1024, 1024, 64 }));
393 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
394 RET((uint64_t []) { 1024 });
395 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
396 RET((uint64_t []) { 1ULL << 40 });
397 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
398 RET((uint64_t []) { 48 << 10 });
399 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
400 RET((uint64_t []) { 512 << 10 });
401 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
402 RET((uint64_t []) { 4096 });
403 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
404 RET((uint32_t []) { 32 });
405 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
406 RET((uint64_t []) { 1ULL << 40 });
407 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
408 RET((uint32_t []) { 0 });
409 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
410 RET((uint32_t []) { screen->mp_count_compute });
411 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
412 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
413 default:
414 return 0;
415 }
416
417 #undef RET
418 }
419
420 static void
421 nvc0_screen_destroy(struct pipe_screen *pscreen)
422 {
423 struct nvc0_screen *screen = nvc0_screen(pscreen);
424
425 if (!nouveau_drm_screen_unref(&screen->base))
426 return;
427
428 if (screen->base.fence.current) {
429 struct nouveau_fence *current = NULL;
430
431 /* nouveau_fence_wait will create a new current fence, so wait on the
432 * _current_ one, and remove both.
433 */
434 nouveau_fence_ref(screen->base.fence.current, &current);
435 nouveau_fence_wait(current, NULL);
436 nouveau_fence_ref(NULL, &current);
437 nouveau_fence_ref(NULL, &screen->base.fence.current);
438 }
439 if (screen->base.pushbuf)
440 screen->base.pushbuf->user_priv = NULL;
441
442 if (screen->blitter)
443 nvc0_blitter_destroy(screen);
444 if (screen->pm.prog) {
445 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
446 nvc0_program_destroy(NULL, screen->pm.prog);
447 FREE(screen->pm.prog);
448 }
449
450 nouveau_bo_ref(NULL, &screen->text);
451 nouveau_bo_ref(NULL, &screen->uniform_bo);
452 nouveau_bo_ref(NULL, &screen->tls);
453 nouveau_bo_ref(NULL, &screen->txc);
454 nouveau_bo_ref(NULL, &screen->fence.bo);
455 nouveau_bo_ref(NULL, &screen->poly_cache);
456 nouveau_bo_ref(NULL, &screen->parm);
457
458 nouveau_heap_destroy(&screen->lib_code);
459 nouveau_heap_destroy(&screen->text_heap);
460
461 FREE(screen->tic.entries);
462
463 nouveau_object_del(&screen->eng3d);
464 nouveau_object_del(&screen->eng2d);
465 nouveau_object_del(&screen->m2mf);
466 nouveau_object_del(&screen->compute);
467 nouveau_object_del(&screen->nvsw);
468
469 nouveau_screen_fini(&screen->base);
470
471 FREE(screen);
472 }
473
474 static int
475 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
476 unsigned size, const uint32_t *data)
477 {
478 struct nouveau_pushbuf *push = screen->base.pushbuf;
479
480 size /= 4;
481
482 assert((pos + size) <= 0x800);
483
484 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
485 PUSH_DATA (push, (m - 0x3800) / 8);
486 PUSH_DATA (push, pos);
487 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
488 PUSH_DATA (push, pos);
489 PUSH_DATAp(push, data, size);
490
491 return pos + size;
492 }
493
494 static void
495 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
496 {
497 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
498 PUSH_DATA (push, 0xff);
499 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
500 PUSH_DATA (push, 0xff);
501 PUSH_DATA (push, 0xff);
502 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
503 PUSH_DATA (push, 0xff);
504 PUSH_DATA (push, 0xff);
505 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
506 PUSH_DATA (push, 0x3f);
507
508 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
509 PUSH_DATA (push, (3 << 16) | 3);
510 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
511 PUSH_DATA (push, (2 << 16) | 2);
512
513 if (obj_class < GM107_3D_CLASS) {
514 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
515 PUSH_DATA (push, 0);
516 }
517 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
518 PUSH_DATA (push, 0x10);
519 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
520 PUSH_DATA (push, 0x10);
521 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
522 PUSH_DATA (push, 0x10);
523 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
524 PUSH_DATA (push, 0x10);
525 PUSH_DATA (push, 0x10);
526 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
527 PUSH_DATA (push, 0x10);
528 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
529 PUSH_DATA (push, 0xe);
530
531 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
532 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
533 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
534 PUSH_DATA (push, 0);
535 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
536 PUSH_DATA (push, 3);
537
538 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
539 PUSH_DATA (push, 0x3fffff);
540 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
541 PUSH_DATA (push, 1);
542 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
543 PUSH_DATA (push, 1);
544
545 if (obj_class < GM107_3D_CLASS) {
546 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
547 PUSH_DATA (push, 3);
548
549 if (obj_class >= NVE4_3D_CLASS) {
550 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
551 PUSH_DATA (push, 1);
552 }
553 }
554
555 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
556 * are supposed to do */
557 }
558
559 static void
560 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
561 {
562 struct nvc0_screen *screen = nvc0_screen(pscreen);
563 struct nouveau_pushbuf *push = screen->base.pushbuf;
564
565 /* we need to do it after possible flush in MARK_RING */
566 *sequence = ++screen->base.fence.sequence;
567
568 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
569 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
570 PUSH_DATAh(push, screen->fence.bo->offset);
571 PUSH_DATA (push, screen->fence.bo->offset);
572 PUSH_DATA (push, *sequence);
573 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
574 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
575 }
576
577 static u32
578 nvc0_screen_fence_update(struct pipe_screen *pscreen)
579 {
580 struct nvc0_screen *screen = nvc0_screen(pscreen);
581 return screen->fence.map[0];
582 }
583
584 static int
585 nvc0_screen_init_compute(struct nvc0_screen *screen)
586 {
587 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
588
589 switch (screen->base.device->chipset & ~0xf) {
590 case 0xc0:
591 case 0xd0:
592 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
593 case 0xe0:
594 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
595 case 0xf0:
596 case 0x100:
597 case 0x110:
598 return 0;
599 default:
600 return -1;
601 }
602 }
603
604 bool
605 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
606 uint32_t lpos, uint32_t lneg, uint32_t cstack)
607 {
608 struct nouveau_bo *bo = NULL;
609 int ret;
610 uint64_t size = (lpos + lneg) * 32 + cstack;
611
612 if (size >= (1 << 20)) {
613 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
614 return false;
615 }
616
617 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
618 size = align(size, 0x8000);
619 size *= screen->mp_count;
620
621 size = align(size, 1 << 17);
622
623 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
624 NULL, &bo);
625 if (ret) {
626 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
627 return false;
628 }
629 nouveau_bo_ref(NULL, &screen->tls);
630 screen->tls = bo;
631 return true;
632 }
633
634 #define FAIL_SCREEN_INIT(str, err) \
635 do { \
636 NOUVEAU_ERR(str, err); \
637 goto fail; \
638 } while(0)
639
640 struct nouveau_screen *
641 nvc0_screen_create(struct nouveau_device *dev)
642 {
643 struct nvc0_screen *screen;
644 struct pipe_screen *pscreen;
645 struct nouveau_object *chan;
646 struct nouveau_pushbuf *push;
647 uint64_t value;
648 uint32_t obj_class;
649 uint32_t flags;
650 int ret;
651 unsigned i;
652
653 switch (dev->chipset & ~0xf) {
654 case 0xc0:
655 case 0xd0:
656 case 0xe0:
657 case 0xf0:
658 case 0x100:
659 case 0x110:
660 break;
661 default:
662 return NULL;
663 }
664
665 screen = CALLOC_STRUCT(nvc0_screen);
666 if (!screen)
667 return NULL;
668 pscreen = &screen->base.base;
669 pscreen->destroy = nvc0_screen_destroy;
670
671 ret = nouveau_screen_init(&screen->base, dev);
672 if (ret) {
673 nvc0_screen_destroy(pscreen);
674 return NULL;
675 }
676 chan = screen->base.channel;
677 push = screen->base.pushbuf;
678 push->user_priv = screen;
679 push->rsvd_kick = 5;
680
681 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
682 PIPE_BIND_SHADER_BUFFER |
683 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
684 PIPE_BIND_COMMAND_ARGS_BUFFER;
685 screen->base.sysmem_bindings |=
686 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
687
688 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
689 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
690 screen->base.vidmem_bindings = 0;
691 }
692
693 pscreen->context_create = nvc0_create;
694 pscreen->is_format_supported = nvc0_screen_is_format_supported;
695 pscreen->get_param = nvc0_screen_get_param;
696 pscreen->get_shader_param = nvc0_screen_get_shader_param;
697 pscreen->get_paramf = nvc0_screen_get_paramf;
698 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
699 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
700
701 nvc0_screen_init_resource_functions(pscreen);
702
703 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
704 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
705
706 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
707 if (screen->base.drm->version >= 0x01000202)
708 flags |= NOUVEAU_BO_COHERENT;
709
710 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
711 if (ret)
712 goto fail;
713 nouveau_bo_map(screen->fence.bo, 0, NULL);
714 screen->fence.map = screen->fence.bo->map;
715 screen->base.fence.emit = nvc0_screen_fence_emit;
716 screen->base.fence.update = nvc0_screen_fence_update;
717
718
719 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
720 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
721 if (ret)
722 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
723
724 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
725 PUSH_DATA (push, screen->nvsw->handle);
726
727 switch (dev->chipset & ~0xf) {
728 case 0x110:
729 case 0x100:
730 case 0xf0:
731 obj_class = NVF0_P2MF_CLASS;
732 break;
733 case 0xe0:
734 obj_class = NVE4_P2MF_CLASS;
735 break;
736 default:
737 obj_class = NVC0_M2MF_CLASS;
738 break;
739 }
740 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
741 &screen->m2mf);
742 if (ret)
743 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
744
745 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
746 PUSH_DATA (push, screen->m2mf->oclass);
747 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
748 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
749 PUSH_DATA (push, 0xa0b5);
750 }
751
752 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
753 &screen->eng2d);
754 if (ret)
755 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
756
757 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
758 PUSH_DATA (push, screen->eng2d->oclass);
759 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
760 PUSH_DATA (push, 0);
761 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
762 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
763 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
764 PUSH_DATA (push, 0);
765 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
766 PUSH_DATA (push, 0);
767 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
768 PUSH_DATA (push, 0x3f);
769 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
770 PUSH_DATA (push, 1);
771 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
772 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
773
774 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
775 PUSH_DATAh(push, screen->fence.bo->offset + 16);
776 PUSH_DATA (push, screen->fence.bo->offset + 16);
777
778 switch (dev->chipset & ~0xf) {
779 case 0x110:
780 obj_class = GM107_3D_CLASS;
781 break;
782 case 0x100:
783 case 0xf0:
784 obj_class = NVF0_3D_CLASS;
785 break;
786 case 0xe0:
787 switch (dev->chipset) {
788 case 0xea:
789 obj_class = NVEA_3D_CLASS;
790 break;
791 default:
792 obj_class = NVE4_3D_CLASS;
793 break;
794 }
795 break;
796 case 0xd0:
797 obj_class = NVC8_3D_CLASS;
798 break;
799 case 0xc0:
800 default:
801 switch (dev->chipset) {
802 case 0xc8:
803 obj_class = NVC8_3D_CLASS;
804 break;
805 case 0xc1:
806 obj_class = NVC1_3D_CLASS;
807 break;
808 default:
809 obj_class = NVC0_3D_CLASS;
810 break;
811 }
812 break;
813 }
814 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
815 &screen->eng3d);
816 if (ret)
817 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
818 screen->base.class_3d = obj_class;
819
820 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
821 PUSH_DATA (push, screen->eng3d->oclass);
822
823 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
824 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
825
826 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
827 /* kill shaders after about 1 second (at 100 MHz) */
828 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
829 PUSH_DATA (push, 0x17);
830 }
831
832 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
833 screen->base.drm->version >= 0x01000101);
834 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
835 for (i = 0; i < 8; ++i)
836 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
837
838 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
839 PUSH_DATA (push, 1);
840
841 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
842 PUSH_DATA (push, 0);
843 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
844 PUSH_DATA (push, 0);
845 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
846 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
847 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
848 PUSH_DATA (push, 0);
849 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
850 PUSH_DATA (push, 1);
851 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
852 PUSH_DATA (push, 1);
853 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
854 PUSH_DATA (push, 1);
855 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
856 PUSH_DATA (push, 0);
857 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
858 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
859 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
860 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
861 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
862 } else {
863 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
864 PUSH_DATA (push, 15);
865 }
866 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
867 PUSH_DATA (push, 8); /* 128 */
868 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
869 PUSH_DATA (push, 1);
870 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
871 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
872 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
873 }
874
875 nvc0_magic_3d_init(push, screen->eng3d->oclass);
876
877 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
878 &screen->text);
879 if (ret)
880 goto fail;
881
882 /* XXX: getting a page fault at the end of the code buffer every few
883 * launches, don't use the last 256 bytes to work around them - prefetch ?
884 */
885 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
886
887 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
888 &screen->uniform_bo);
889 if (ret)
890 goto fail;
891
892 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
893
894 for (i = 0; i < 5; ++i) {
895 /* TIC and TSC entries for each unit (nve4+ only) */
896 /* auxiliary constants (6 user clip planes, base instance id) */
897 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
898 PUSH_DATA (push, 1024);
899 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 10));
900 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 10));
901 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
902 PUSH_DATA (push, (15 << 4) | 1);
903 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
904 unsigned j;
905 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
906 PUSH_DATA (push, 0);
907 for (j = 0; j < 8; ++j)
908 PUSH_DATA(push, j);
909 } else {
910 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
911 PUSH_DATA (push, 0x54);
912 }
913 }
914 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
915 PUSH_DATA (push, 0);
916
917 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
918 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
919 PUSH_DATA (push, 256);
920 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
921 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
922 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
923 PUSH_DATA (push, 0);
924 PUSH_DATAf(push, 0.0f);
925 PUSH_DATAf(push, 0.0f);
926 PUSH_DATAf(push, 0.0f);
927 PUSH_DATAf(push, 0.0f);
928 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
929 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
930 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
931
932 if (screen->base.drm->version >= 0x01000101) {
933 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
934 if (ret) {
935 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
936 goto fail;
937 }
938 } else {
939 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
940 value = (8 << 8) | 4;
941 else
942 value = (16 << 8) | 4;
943 }
944 screen->gpc_count = value & 0x000000ff;
945 screen->mp_count = value >> 8;
946 screen->mp_count_compute = screen->mp_count;
947
948 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
949
950 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
951 PUSH_DATAh(push, screen->text->offset);
952 PUSH_DATA (push, screen->text->offset);
953 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
954 PUSH_DATAh(push, screen->tls->offset);
955 PUSH_DATA (push, screen->tls->offset);
956 PUSH_DATA (push, screen->tls->size >> 32);
957 PUSH_DATA (push, screen->tls->size);
958 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
959 PUSH_DATA (push, 0);
960 /* Reduce likelihood of collision with real buffers by placing the hole at
961 * the top of the 4G area. This will have to be dealt with for real
962 * eventually by blocking off that area from the VM.
963 */
964 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
965 PUSH_DATA (push, 0xff << 24);
966
967 if (screen->eng3d->oclass < GM107_3D_CLASS) {
968 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
969 &screen->poly_cache);
970 if (ret)
971 goto fail;
972
973 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
974 PUSH_DATAh(push, screen->poly_cache->offset);
975 PUSH_DATA (push, screen->poly_cache->offset);
976 PUSH_DATA (push, 3);
977 }
978
979 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
980 &screen->txc);
981 if (ret)
982 goto fail;
983
984 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
985 PUSH_DATAh(push, screen->txc->offset);
986 PUSH_DATA (push, screen->txc->offset);
987 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
988
989 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
990 PUSH_DATAh(push, screen->txc->offset + 65536);
991 PUSH_DATA (push, screen->txc->offset + 65536);
992 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
993
994 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
995 PUSH_DATA (push, 0);
996 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
997 PUSH_DATA (push, 0);
998 PUSH_DATA (push, 0);
999 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1000 PUSH_DATA (push, 0x3f);
1001
1002 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1003 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1004 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1005 for (i = 0; i < 8 * 2; ++i)
1006 PUSH_DATA(push, 0);
1007 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1008 PUSH_DATA (push, 0);
1009 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1010 PUSH_DATA (push, 0);
1011
1012 /* neither scissors, viewport nor stencil mask should affect clears */
1013 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1014 PUSH_DATA (push, 0);
1015
1016 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1017 PUSH_DATA (push, 1);
1018 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1019 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1020 PUSH_DATAf(push, 0.0f);
1021 PUSH_DATAf(push, 1.0f);
1022 }
1023 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1024 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1025
1026 /* We use scissors instead of exact view volume clipping,
1027 * so they're always enabled.
1028 */
1029 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1030 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1031 PUSH_DATA (push, 1);
1032 PUSH_DATA (push, 8192 << 16);
1033 PUSH_DATA (push, 8192 << 16);
1034 }
1035
1036 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1037
1038 i = 0;
1039 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1040 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1041 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1042 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1043 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1044 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1045 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1046 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1047 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1048 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1049 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1050
1051 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1052 PUSH_DATA (push, 1);
1053 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1054 PUSH_DATA (push, 1);
1055 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1056 PUSH_DATA (push, 0x40);
1057 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1058 PUSH_DATA (push, 0);
1059 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1060 PUSH_DATA (push, 0x30);
1061 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1062 PUSH_DATA (push, 3);
1063 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1064 PUSH_DATA (push, 0x20);
1065 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1066 PUSH_DATA (push, 0x00);
1067 screen->save_state.patch_vertices = 3;
1068
1069 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1070 PUSH_DATA (push, 0);
1071 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1072 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1073
1074 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1075
1076 if (nvc0_screen_init_compute(screen))
1077 goto fail;
1078
1079 PUSH_KICK (push);
1080
1081 screen->tic.entries = CALLOC(4096, sizeof(void *));
1082 screen->tsc.entries = screen->tic.entries + 2048;
1083
1084 if (!nvc0_blitter_create(screen))
1085 goto fail;
1086
1087 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1088
1089 return &screen->base;
1090
1091 fail:
1092 screen->base.base.context_create = NULL;
1093 return &screen->base;
1094 }
1095
1096 int
1097 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1098 {
1099 int i = screen->tic.next;
1100
1101 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1102 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1103
1104 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1105
1106 if (screen->tic.entries[i])
1107 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1108
1109 screen->tic.entries[i] = entry;
1110 return i;
1111 }
1112
1113 int
1114 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1115 {
1116 int i = screen->tsc.next;
1117
1118 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1119 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1120
1121 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1122
1123 if (screen->tsc.entries[i])
1124 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1125
1126 screen->tsc.entries[i] = entry;
1127 return i;
1128 }