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gallium: add a cap for VIEWPORT_SUBPIXEL_BITS (v2)
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 const struct util_format_description *desc = util_format_description(format);
49
50 if (sample_count > 8)
51 return false;
52 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
53 return false;
54
55 /* Short-circuit the rest of the logic -- this is used by the state tracker
56 * to determine valid MS levels in a no-attachments scenario.
57 */
58 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
59 return true;
60
61 if (!util_format_is_supported(format, bindings))
62 return false;
63
64 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
65 if (util_format_get_blocksizebits(format) == 3 * 32)
66 return false;
67
68 if (bindings & PIPE_BIND_LINEAR)
69 if (util_format_is_depth_or_stencil(format) ||
70 (target != PIPE_TEXTURE_1D &&
71 target != PIPE_TEXTURE_2D &&
72 target != PIPE_TEXTURE_RECT) ||
73 sample_count > 1)
74 return false;
75
76 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
77 */
78 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
79 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
80 /* The claim is that this should work on GM107 but it doesn't. Need to
81 * test further and figure out if it's a nouveau issue or a HW one.
82 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
83 */
84 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
85 return false;
86
87 /* transfers & shared are always supported */
88 bindings &= ~(PIPE_BIND_TRANSFER_READ |
89 PIPE_BIND_TRANSFER_WRITE |
90 PIPE_BIND_LINEAR |
91 PIPE_BIND_SHARED);
92
93 if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
94 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
95 /* MS images are currently unsupported on Maxwell because they have to
96 * be handled explicitly. */
97 return false;
98 }
99
100 return (( nvc0_format_table[format].usage |
101 nvc0_vertex_format[format].usage) & bindings) == bindings;
102 }
103
104 static int
105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
106 {
107 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
108 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
109
110 switch (param) {
111 /* non-boolean caps */
112 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
113 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
114 return 15;
115 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
116 return 12;
117 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
118 return 2048;
119 case PIPE_CAP_MIN_TEXEL_OFFSET:
120 return -8;
121 case PIPE_CAP_MAX_TEXEL_OFFSET:
122 return 7;
123 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
124 return -32;
125 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
126 return 31;
127 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
128 return 128 * 1024 * 1024;
129 case PIPE_CAP_GLSL_FEATURE_LEVEL:
130 if (class_3d <= NVF0_3D_CLASS)
131 return 430;
132 return 410;
133 case PIPE_CAP_MAX_RENDER_TARGETS:
134 return 8;
135 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
136 return 1;
137 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
138 return 4;
139 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
140 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
141 return 128;
142 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
143 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
144 return 1024;
145 case PIPE_CAP_MAX_VERTEX_STREAMS:
146 return 4;
147 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
148 return 2048;
149 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
150 return 256;
151 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
152 return 16; /* 256 for binding as RT, but that's not possible in GL */
153 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
154 return 16;
155 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
156 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
157 case PIPE_CAP_MAX_VIEWPORTS:
158 return NVC0_MAX_VIEWPORTS;
159 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
160 return 4;
161 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
162 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
163 case PIPE_CAP_ENDIANNESS:
164 return PIPE_ENDIAN_LITTLE;
165 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
166 return 30;
167 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
168 return NVC0_MAX_WINDOW_RECTANGLES;
169
170 /* supported caps */
171 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
172 case PIPE_CAP_TEXTURE_SWIZZLE:
173 case PIPE_CAP_TEXTURE_SHADOW_MAP:
174 case PIPE_CAP_NPOT_TEXTURES:
175 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
176 case PIPE_CAP_ANISOTROPIC_FILTER:
177 case PIPE_CAP_SEAMLESS_CUBE_MAP:
178 case PIPE_CAP_CUBE_MAP_ARRAY:
179 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
180 case PIPE_CAP_TEXTURE_MULTISAMPLE:
181 case PIPE_CAP_TWO_SIDED_STENCIL:
182 case PIPE_CAP_DEPTH_CLIP_DISABLE:
183 case PIPE_CAP_POINT_SPRITE:
184 case PIPE_CAP_TGSI_TEXCOORD:
185 case PIPE_CAP_SM3:
186 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
187 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
188 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
189 case PIPE_CAP_QUERY_TIMESTAMP:
190 case PIPE_CAP_QUERY_TIME_ELAPSED:
191 case PIPE_CAP_OCCLUSION_QUERY:
192 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
193 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
194 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
195 case PIPE_CAP_INDEP_BLEND_ENABLE:
196 case PIPE_CAP_INDEP_BLEND_FUNC:
197 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
198 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
199 case PIPE_CAP_PRIMITIVE_RESTART:
200 case PIPE_CAP_TGSI_INSTANCEID:
201 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
202 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
203 case PIPE_CAP_CONDITIONAL_RENDER:
204 case PIPE_CAP_TEXTURE_BARRIER:
205 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
206 case PIPE_CAP_START_INSTANCE:
207 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
208 case PIPE_CAP_DRAW_INDIRECT:
209 case PIPE_CAP_USER_CONSTANT_BUFFERS:
210 case PIPE_CAP_USER_INDEX_BUFFERS:
211 case PIPE_CAP_USER_VERTEX_BUFFERS:
212 case PIPE_CAP_TEXTURE_QUERY_LOD:
213 case PIPE_CAP_SAMPLE_SHADING:
214 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
215 case PIPE_CAP_TEXTURE_GATHER_SM5:
216 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
217 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
218 case PIPE_CAP_SAMPLER_VIEW_TARGET:
219 case PIPE_CAP_CLIP_HALFZ:
220 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
221 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
222 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
223 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
224 case PIPE_CAP_DEPTH_BOUNDS_TEST:
225 case PIPE_CAP_TGSI_TXQS:
226 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
227 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
228 case PIPE_CAP_SHAREABLE_SHADERS:
229 case PIPE_CAP_CLEAR_TEXTURE:
230 case PIPE_CAP_DRAW_PARAMETERS:
231 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
232 case PIPE_CAP_MULTI_DRAW_INDIRECT:
233 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
234 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
235 case PIPE_CAP_QUERY_BUFFER_OBJECT:
236 case PIPE_CAP_INVALIDATE_BUFFER:
237 case PIPE_CAP_STRING_MARKER:
238 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
239 case PIPE_CAP_CULL_DISTANCE:
240 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
241 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
242 case PIPE_CAP_TGSI_VOTE:
243 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
244 return 1;
245 case PIPE_CAP_COMPUTE:
246 return (class_3d < GP100_3D_CLASS);
247 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
248 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
249 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
250 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
251
252 /* unsupported caps */
253 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
254 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
255 case PIPE_CAP_SHADER_STENCIL_EXPORT:
256 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
257 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
258 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
259 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
260 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
261 case PIPE_CAP_FAKE_SW_MSAA:
262 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
263 case PIPE_CAP_VERTEXID_NOBASE:
264 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
265 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
266 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
267 case PIPE_CAP_GENERATE_MIPMAP:
268 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
269 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
270 case PIPE_CAP_QUERY_MEMORY_INFO:
271 case PIPE_CAP_PCI_GROUP:
272 case PIPE_CAP_PCI_BUS:
273 case PIPE_CAP_PCI_DEVICE:
274 case PIPE_CAP_PCI_FUNCTION:
275 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
276 return 0;
277
278 case PIPE_CAP_VENDOR_ID:
279 return 0x10de;
280 case PIPE_CAP_DEVICE_ID: {
281 uint64_t device_id;
282 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
283 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
284 return -1;
285 }
286 return device_id;
287 }
288 case PIPE_CAP_ACCELERATED:
289 return 1;
290 case PIPE_CAP_VIDEO_MEMORY:
291 return dev->vram_size >> 20;
292 case PIPE_CAP_UMA:
293 return 0;
294 }
295
296 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
297 return 0;
298 }
299
300 static int
301 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
302 enum pipe_shader_cap param)
303 {
304 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
305
306 switch (shader) {
307 case PIPE_SHADER_VERTEX:
308 case PIPE_SHADER_GEOMETRY:
309 case PIPE_SHADER_FRAGMENT:
310 case PIPE_SHADER_COMPUTE:
311 break;
312 case PIPE_SHADER_TESS_CTRL:
313 case PIPE_SHADER_TESS_EVAL:
314 if (class_3d >= GM107_3D_CLASS)
315 return 0;
316 break;
317 default:
318 return 0;
319 }
320
321 switch (param) {
322 case PIPE_SHADER_CAP_PREFERRED_IR:
323 return PIPE_SHADER_IR_TGSI;
324 case PIPE_SHADER_CAP_SUPPORTED_IRS:
325 return 1 << PIPE_SHADER_IR_TGSI;
326 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
327 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
328 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
329 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
330 return 16384;
331 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
332 return 16;
333 case PIPE_SHADER_CAP_MAX_INPUTS:
334 if (shader == PIPE_SHADER_VERTEX)
335 return 32;
336 /* NOTE: These only count our slots for GENERIC varyings.
337 * The address space may be larger, but the actual hard limit seems to be
338 * less than what the address space layout permits, so don't add TEXCOORD,
339 * COLOR, etc. here.
340 */
341 if (shader == PIPE_SHADER_FRAGMENT)
342 return 0x1f0 / 16;
343 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
344 * and excludes 0x60 per-patch inputs.
345 */
346 return 0x200 / 16;
347 case PIPE_SHADER_CAP_MAX_OUTPUTS:
348 return 32;
349 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
350 return 65536;
351 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
352 return NVC0_MAX_PIPE_CONSTBUFS;
353 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
354 return shader != PIPE_SHADER_FRAGMENT;
355 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
356 return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
357 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
358 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
359 return 1;
360 case PIPE_SHADER_CAP_MAX_PREDS:
361 return 0;
362 case PIPE_SHADER_CAP_MAX_TEMPS:
363 return NVC0_CAP_MAX_PROGRAM_TEMPS;
364 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
365 return 1;
366 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
367 return 1;
368 case PIPE_SHADER_CAP_SUBROUTINES:
369 return 1;
370 case PIPE_SHADER_CAP_INTEGERS:
371 return 1;
372 case PIPE_SHADER_CAP_DOUBLES:
373 return 1;
374 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
375 return 1;
376 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
377 return 1;
378 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
379 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
380 return 0;
381 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
382 return NVC0_MAX_BUFFERS;
383 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
384 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
385 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
386 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
387 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
388 return 32;
389 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
390 if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
391 return NVC0_MAX_IMAGES;
392 if (class_3d < NVE4_3D_CLASS)
393 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
394 return NVC0_MAX_IMAGES;
395 return 0;
396 default:
397 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
398 return 0;
399 }
400 }
401
402 static float
403 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
404 {
405 switch (param) {
406 case PIPE_CAPF_MAX_LINE_WIDTH:
407 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
408 return 10.0f;
409 case PIPE_CAPF_MAX_POINT_WIDTH:
410 return 63.0f;
411 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
412 return 63.375f;
413 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
414 return 16.0f;
415 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
416 return 15.0f;
417 case PIPE_CAPF_GUARD_BAND_LEFT:
418 case PIPE_CAPF_GUARD_BAND_TOP:
419 return 0.0f;
420 case PIPE_CAPF_GUARD_BAND_RIGHT:
421 case PIPE_CAPF_GUARD_BAND_BOTTOM:
422 return 0.0f; /* that or infinity */
423 }
424
425 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
426 return 0.0f;
427 }
428
429 static int
430 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
431 enum pipe_shader_ir ir_type,
432 enum pipe_compute_cap param, void *data)
433 {
434 struct nvc0_screen *screen = nvc0_screen(pscreen);
435 const uint16_t obj_class = screen->compute->oclass;
436
437 #define RET(x) do { \
438 if (data) \
439 memcpy(data, x, sizeof(x)); \
440 return sizeof(x); \
441 } while (0)
442
443 switch (param) {
444 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
445 RET((uint64_t []) { 3 });
446 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
447 if (obj_class >= NVE4_COMPUTE_CLASS) {
448 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
449 } else {
450 RET(((uint64_t []) { 65535, 65535, 65535 }));
451 }
452 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
453 RET(((uint64_t []) { 1024, 1024, 64 }));
454 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
455 RET((uint64_t []) { 1024 });
456 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
457 RET((uint64_t []) { 1ULL << 40 });
458 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
459 switch (obj_class) {
460 case GM200_COMPUTE_CLASS:
461 RET((uint64_t []) { 96 << 10 });
462 break;
463 case GM107_COMPUTE_CLASS:
464 RET((uint64_t []) { 64 << 10 });
465 break;
466 default:
467 RET((uint64_t []) { 48 << 10 });
468 break;
469 }
470 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
471 RET((uint64_t []) { 512 << 10 });
472 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
473 RET((uint64_t []) { 4096 });
474 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
475 RET((uint32_t []) { 32 });
476 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
477 RET((uint64_t []) { 1ULL << 40 });
478 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
479 RET((uint32_t []) { 0 });
480 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
481 RET((uint32_t []) { screen->mp_count_compute });
482 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
483 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
484 default:
485 return 0;
486 }
487
488 #undef RET
489 }
490
491 static void
492 nvc0_screen_destroy(struct pipe_screen *pscreen)
493 {
494 struct nvc0_screen *screen = nvc0_screen(pscreen);
495
496 if (!nouveau_drm_screen_unref(&screen->base))
497 return;
498
499 if (screen->base.fence.current) {
500 struct nouveau_fence *current = NULL;
501
502 /* nouveau_fence_wait will create a new current fence, so wait on the
503 * _current_ one, and remove both.
504 */
505 nouveau_fence_ref(screen->base.fence.current, &current);
506 nouveau_fence_wait(current, NULL);
507 nouveau_fence_ref(NULL, &current);
508 nouveau_fence_ref(NULL, &screen->base.fence.current);
509 }
510 if (screen->base.pushbuf)
511 screen->base.pushbuf->user_priv = NULL;
512
513 if (screen->blitter)
514 nvc0_blitter_destroy(screen);
515 if (screen->pm.prog) {
516 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
517 nvc0_program_destroy(NULL, screen->pm.prog);
518 FREE(screen->pm.prog);
519 }
520
521 nouveau_bo_ref(NULL, &screen->text);
522 nouveau_bo_ref(NULL, &screen->uniform_bo);
523 nouveau_bo_ref(NULL, &screen->tls);
524 nouveau_bo_ref(NULL, &screen->txc);
525 nouveau_bo_ref(NULL, &screen->fence.bo);
526 nouveau_bo_ref(NULL, &screen->poly_cache);
527
528 nouveau_heap_destroy(&screen->lib_code);
529 nouveau_heap_destroy(&screen->text_heap);
530
531 FREE(screen->tic.entries);
532
533 nouveau_object_del(&screen->eng3d);
534 nouveau_object_del(&screen->eng2d);
535 nouveau_object_del(&screen->m2mf);
536 nouveau_object_del(&screen->compute);
537 nouveau_object_del(&screen->nvsw);
538
539 nouveau_screen_fini(&screen->base);
540
541 FREE(screen);
542 }
543
544 static int
545 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
546 unsigned size, const uint32_t *data)
547 {
548 struct nouveau_pushbuf *push = screen->base.pushbuf;
549
550 size /= 4;
551
552 assert((pos + size) <= 0x800);
553
554 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
555 PUSH_DATA (push, (m - 0x3800) / 8);
556 PUSH_DATA (push, pos);
557 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
558 PUSH_DATA (push, pos);
559 PUSH_DATAp(push, data, size);
560
561 return pos + size;
562 }
563
564 static void
565 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
566 {
567 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
568 PUSH_DATA (push, 0xff);
569 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
570 PUSH_DATA (push, 0xff);
571 PUSH_DATA (push, 0xff);
572 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
573 PUSH_DATA (push, 0xff);
574 PUSH_DATA (push, 0xff);
575 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
576 PUSH_DATA (push, 0x3f);
577
578 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
579 PUSH_DATA (push, (3 << 16) | 3);
580 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
581 PUSH_DATA (push, (2 << 16) | 2);
582
583 if (obj_class < GM107_3D_CLASS) {
584 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
585 PUSH_DATA (push, 0);
586 }
587 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
588 PUSH_DATA (push, 0x10);
589 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
590 PUSH_DATA (push, 0x10);
591 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
592 PUSH_DATA (push, 0x10);
593 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
594 PUSH_DATA (push, 0x10);
595 PUSH_DATA (push, 0x10);
596 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
597 PUSH_DATA (push, 0x10);
598 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
599 PUSH_DATA (push, 0xe);
600
601 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
602 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
603 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
604 PUSH_DATA (push, 0);
605 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
606 PUSH_DATA (push, 3);
607
608 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
609 PUSH_DATA (push, 0x3fffff);
610 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
611 PUSH_DATA (push, 1);
612 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
613 PUSH_DATA (push, 1);
614
615 if (obj_class < GM107_3D_CLASS) {
616 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
617 PUSH_DATA (push, 3);
618
619 if (obj_class >= NVE4_3D_CLASS) {
620 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
621 PUSH_DATA (push, 1);
622 }
623 }
624
625 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
626 * are supposed to do */
627 }
628
629 static void
630 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
631 {
632 struct nvc0_screen *screen = nvc0_screen(pscreen);
633 struct nouveau_pushbuf *push = screen->base.pushbuf;
634
635 /* we need to do it after possible flush in MARK_RING */
636 *sequence = ++screen->base.fence.sequence;
637
638 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
639 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
640 PUSH_DATAh(push, screen->fence.bo->offset);
641 PUSH_DATA (push, screen->fence.bo->offset);
642 PUSH_DATA (push, *sequence);
643 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
644 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
645 }
646
647 static u32
648 nvc0_screen_fence_update(struct pipe_screen *pscreen)
649 {
650 struct nvc0_screen *screen = nvc0_screen(pscreen);
651 return screen->fence.map[0];
652 }
653
654 static int
655 nvc0_screen_init_compute(struct nvc0_screen *screen)
656 {
657 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
658
659 switch (screen->base.device->chipset & ~0xf) {
660 case 0xc0:
661 case 0xd0:
662 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
663 case 0xe0:
664 case 0xf0:
665 case 0x100:
666 case 0x110:
667 case 0x120:
668 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
669 case 0x130:
670 return 0;
671 default:
672 return -1;
673 }
674 }
675
676 bool
677 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
678 uint32_t lpos, uint32_t lneg, uint32_t cstack)
679 {
680 struct nouveau_bo *bo = NULL;
681 int ret;
682 uint64_t size = (lpos + lneg) * 32 + cstack;
683
684 if (size >= (1 << 20)) {
685 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
686 return false;
687 }
688
689 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
690 size = align(size, 0x8000);
691 size *= screen->mp_count;
692
693 size = align(size, 1 << 17);
694
695 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
696 NULL, &bo);
697 if (ret) {
698 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
699 return false;
700 }
701 nouveau_bo_ref(NULL, &screen->tls);
702 screen->tls = bo;
703 return true;
704 }
705
706 #define FAIL_SCREEN_INIT(str, err) \
707 do { \
708 NOUVEAU_ERR(str, err); \
709 goto fail; \
710 } while(0)
711
712 struct nouveau_screen *
713 nvc0_screen_create(struct nouveau_device *dev)
714 {
715 struct nvc0_screen *screen;
716 struct pipe_screen *pscreen;
717 struct nouveau_object *chan;
718 struct nouveau_pushbuf *push;
719 uint64_t value;
720 uint32_t obj_class;
721 uint32_t flags;
722 int ret;
723 unsigned i;
724
725 switch (dev->chipset & ~0xf) {
726 case 0xc0:
727 case 0xd0:
728 case 0xe0:
729 case 0xf0:
730 case 0x100:
731 case 0x110:
732 case 0x120:
733 case 0x130:
734 break;
735 default:
736 return NULL;
737 }
738
739 screen = CALLOC_STRUCT(nvc0_screen);
740 if (!screen)
741 return NULL;
742 pscreen = &screen->base.base;
743 pscreen->destroy = nvc0_screen_destroy;
744
745 ret = nouveau_screen_init(&screen->base, dev);
746 if (ret)
747 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
748 chan = screen->base.channel;
749 push = screen->base.pushbuf;
750 push->user_priv = screen;
751 push->rsvd_kick = 5;
752
753 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
754 PIPE_BIND_SHADER_BUFFER |
755 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
756 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
757 screen->base.sysmem_bindings |=
758 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
759
760 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
761 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
762 screen->base.vidmem_bindings = 0;
763 }
764
765 pscreen->context_create = nvc0_create;
766 pscreen->is_format_supported = nvc0_screen_is_format_supported;
767 pscreen->get_param = nvc0_screen_get_param;
768 pscreen->get_shader_param = nvc0_screen_get_shader_param;
769 pscreen->get_paramf = nvc0_screen_get_paramf;
770 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
771 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
772
773 nvc0_screen_init_resource_functions(pscreen);
774
775 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
776 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
777
778 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
779 if (screen->base.drm->version >= 0x01000202)
780 flags |= NOUVEAU_BO_COHERENT;
781
782 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
783 if (ret)
784 goto fail;
785 nouveau_bo_map(screen->fence.bo, 0, NULL);
786 screen->fence.map = screen->fence.bo->map;
787 screen->base.fence.emit = nvc0_screen_fence_emit;
788 screen->base.fence.update = nvc0_screen_fence_update;
789
790
791 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
792 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
793 if (ret)
794 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
795
796 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
797 PUSH_DATA (push, screen->nvsw->handle);
798
799 switch (dev->chipset & ~0xf) {
800 case 0x130:
801 case 0x120:
802 case 0x110:
803 case 0x100:
804 case 0xf0:
805 obj_class = NVF0_P2MF_CLASS;
806 break;
807 case 0xe0:
808 obj_class = NVE4_P2MF_CLASS;
809 break;
810 default:
811 obj_class = NVC0_M2MF_CLASS;
812 break;
813 }
814 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
815 &screen->m2mf);
816 if (ret)
817 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
818
819 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
820 PUSH_DATA (push, screen->m2mf->oclass);
821 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
822 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
823 PUSH_DATA (push, 0xa0b5);
824 }
825
826 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
827 &screen->eng2d);
828 if (ret)
829 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
830
831 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
832 PUSH_DATA (push, screen->eng2d->oclass);
833 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
834 PUSH_DATA (push, 0);
835 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
836 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
837 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
838 PUSH_DATA (push, 0);
839 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
840 PUSH_DATA (push, 0);
841 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
842 PUSH_DATA (push, 0x3f);
843 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
844 PUSH_DATA (push, 1);
845 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
846 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
847
848 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
849 PUSH_DATAh(push, screen->fence.bo->offset + 16);
850 PUSH_DATA (push, screen->fence.bo->offset + 16);
851
852 switch (dev->chipset & ~0xf) {
853 case 0x130:
854 obj_class = GP100_3D_CLASS;
855 break;
856 case 0x120:
857 obj_class = GM200_3D_CLASS;
858 break;
859 case 0x110:
860 obj_class = GM107_3D_CLASS;
861 break;
862 case 0x100:
863 case 0xf0:
864 obj_class = NVF0_3D_CLASS;
865 break;
866 case 0xe0:
867 switch (dev->chipset) {
868 case 0xea:
869 obj_class = NVEA_3D_CLASS;
870 break;
871 default:
872 obj_class = NVE4_3D_CLASS;
873 break;
874 }
875 break;
876 case 0xd0:
877 obj_class = NVC8_3D_CLASS;
878 break;
879 case 0xc0:
880 default:
881 switch (dev->chipset) {
882 case 0xc8:
883 obj_class = NVC8_3D_CLASS;
884 break;
885 case 0xc1:
886 obj_class = NVC1_3D_CLASS;
887 break;
888 default:
889 obj_class = NVC0_3D_CLASS;
890 break;
891 }
892 break;
893 }
894 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
895 &screen->eng3d);
896 if (ret)
897 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
898 screen->base.class_3d = obj_class;
899
900 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
901 PUSH_DATA (push, screen->eng3d->oclass);
902
903 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
904 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
905
906 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
907 /* kill shaders after about 1 second (at 100 MHz) */
908 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
909 PUSH_DATA (push, 0x17);
910 }
911
912 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
913 screen->base.drm->version >= 0x01000101);
914 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
915 for (i = 0; i < 8; ++i)
916 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
917
918 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
919 PUSH_DATA (push, 1);
920
921 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
922 PUSH_DATA (push, 0);
923 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
924 PUSH_DATA (push, 0);
925 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
926 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
927 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
928 PUSH_DATA (push, 0);
929 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
930 PUSH_DATA (push, 1);
931 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
932 PUSH_DATA (push, 1);
933 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
934 PUSH_DATA (push, 1);
935 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
936 PUSH_DATA (push, 0);
937 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
938 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
939 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
940 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
941 } else {
942 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
943 PUSH_DATA (push, 15);
944 }
945 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
946 PUSH_DATA (push, 8); /* 128 */
947 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
948 PUSH_DATA (push, 1);
949 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
950 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
951 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
952 }
953
954 nvc0_magic_3d_init(push, screen->eng3d->oclass);
955
956 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
957 &screen->text);
958 if (ret)
959 goto fail;
960
961 /* XXX: getting a page fault at the end of the code buffer every few
962 * launches, don't use the last 256 bytes to work around them - prefetch ?
963 */
964 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
965
966 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
967 &screen->uniform_bo);
968 if (ret)
969 goto fail;
970
971 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
972
973 for (i = 0; i < 5; ++i) {
974 /* TIC and TSC entries for each unit (nve4+ only) */
975 /* auxiliary constants (6 user clip planes, base instance id) */
976 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
977 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
978 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
979 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
980 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
981 PUSH_DATA (push, (15 << 4) | 1);
982 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
983 unsigned j;
984 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
985 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
986 for (j = 0; j < 8; ++j)
987 PUSH_DATA(push, j);
988 } else {
989 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
990 PUSH_DATA (push, 0x54);
991 }
992
993 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
994 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
995 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
996 PUSH_DATA (push, 0); /* 0 */
997 PUSH_DATA (push, 0);
998 PUSH_DATA (push, 1); /* 1 */
999 PUSH_DATA (push, 0);
1000 PUSH_DATA (push, 0); /* 2 */
1001 PUSH_DATA (push, 1);
1002 PUSH_DATA (push, 1); /* 3 */
1003 PUSH_DATA (push, 1);
1004 PUSH_DATA (push, 2); /* 4 */
1005 PUSH_DATA (push, 0);
1006 PUSH_DATA (push, 3); /* 5 */
1007 PUSH_DATA (push, 0);
1008 PUSH_DATA (push, 2); /* 6 */
1009 PUSH_DATA (push, 1);
1010 PUSH_DATA (push, 3); /* 7 */
1011 PUSH_DATA (push, 1);
1012 }
1013 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1014 PUSH_DATA (push, 0);
1015
1016 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1017 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1018 PUSH_DATA (push, 256);
1019 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1020 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1021 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1022 PUSH_DATA (push, 0);
1023 PUSH_DATAf(push, 0.0f);
1024 PUSH_DATAf(push, 0.0f);
1025 PUSH_DATAf(push, 0.0f);
1026 PUSH_DATAf(push, 0.0f);
1027 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1028 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1029 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1030
1031 if (screen->base.drm->version >= 0x01000101) {
1032 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1033 if (ret) {
1034 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
1035 goto fail;
1036 }
1037 } else {
1038 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1039 value = (8 << 8) | 4;
1040 else
1041 value = (16 << 8) | 4;
1042 }
1043 screen->gpc_count = value & 0x000000ff;
1044 screen->mp_count = value >> 8;
1045 screen->mp_count_compute = screen->mp_count;
1046
1047 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1048
1049 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
1050 PUSH_DATAh(push, screen->text->offset);
1051 PUSH_DATA (push, screen->text->offset);
1052 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1053 PUSH_DATAh(push, screen->tls->offset);
1054 PUSH_DATA (push, screen->tls->offset);
1055 PUSH_DATA (push, screen->tls->size >> 32);
1056 PUSH_DATA (push, screen->tls->size);
1057 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1058 PUSH_DATA (push, 0);
1059 /* Reduce likelihood of collision with real buffers by placing the hole at
1060 * the top of the 4G area. This will have to be dealt with for real
1061 * eventually by blocking off that area from the VM.
1062 */
1063 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1064 PUSH_DATA (push, 0xff << 24);
1065
1066 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1067 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1068 &screen->poly_cache);
1069 if (ret)
1070 goto fail;
1071
1072 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1073 PUSH_DATAh(push, screen->poly_cache->offset);
1074 PUSH_DATA (push, screen->poly_cache->offset);
1075 PUSH_DATA (push, 3);
1076 }
1077
1078 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1079 &screen->txc);
1080 if (ret)
1081 goto fail;
1082
1083 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1084 PUSH_DATAh(push, screen->txc->offset);
1085 PUSH_DATA (push, screen->txc->offset);
1086 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1087 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1088 screen->tic.maxwell = true;
1089 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1090 screen->tic.maxwell =
1091 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1092 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1093 }
1094 }
1095
1096 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1097 PUSH_DATAh(push, screen->txc->offset + 65536);
1098 PUSH_DATA (push, screen->txc->offset + 65536);
1099 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1100
1101 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1102 PUSH_DATA (push, 0);
1103 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1104 PUSH_DATA (push, 0);
1105 PUSH_DATA (push, 0);
1106 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1107 PUSH_DATA (push, 0x3f);
1108
1109 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1110 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1111 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1112 for (i = 0; i < 8 * 2; ++i)
1113 PUSH_DATA(push, 0);
1114 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1115 PUSH_DATA (push, 0);
1116 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1117 PUSH_DATA (push, 0);
1118
1119 /* neither scissors, viewport nor stencil mask should affect clears */
1120 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1121 PUSH_DATA (push, 0);
1122
1123 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1124 PUSH_DATA (push, 1);
1125 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1126 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1127 PUSH_DATAf(push, 0.0f);
1128 PUSH_DATAf(push, 1.0f);
1129 }
1130 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1131 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1132
1133 /* We use scissors instead of exact view volume clipping,
1134 * so they're always enabled.
1135 */
1136 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1137 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1138 PUSH_DATA (push, 1);
1139 PUSH_DATA (push, 8192 << 16);
1140 PUSH_DATA (push, 8192 << 16);
1141 }
1142
1143 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1144
1145 i = 0;
1146 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1147 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1148 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1149 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1150 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1151 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1152 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1153 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1154 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1155 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1156 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1157 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1158 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1159
1160 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1161 PUSH_DATA (push, 1);
1162 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1163 PUSH_DATA (push, 1);
1164 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1165 PUSH_DATA (push, 0x40);
1166 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1167 PUSH_DATA (push, 0);
1168 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1169 PUSH_DATA (push, 0x30);
1170 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1171 PUSH_DATA (push, 3);
1172 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1173 PUSH_DATA (push, 0x20);
1174 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1175 PUSH_DATA (push, 0x00);
1176 screen->save_state.patch_vertices = 3;
1177
1178 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1179 PUSH_DATA (push, 0);
1180 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1181 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1182
1183 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1184
1185 if (nvc0_screen_init_compute(screen))
1186 goto fail;
1187
1188 PUSH_KICK (push);
1189
1190 screen->tic.entries = CALLOC(4096, sizeof(void *));
1191 screen->tsc.entries = screen->tic.entries + 2048;
1192
1193 if (!nvc0_blitter_create(screen))
1194 goto fail;
1195
1196 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1197
1198 return &screen->base;
1199
1200 fail:
1201 screen->base.base.context_create = NULL;
1202 return &screen->base;
1203 }
1204
1205 int
1206 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1207 {
1208 int i = screen->tic.next;
1209
1210 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1211 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1212
1213 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1214
1215 if (screen->tic.entries[i])
1216 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1217
1218 screen->tic.entries[i] = entry;
1219 return i;
1220 }
1221
1222 int
1223 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1224 {
1225 int i = screen->tsc.next;
1226
1227 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1228 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1229
1230 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1231
1232 if (screen->tsc.entries[i])
1233 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1234
1235 screen->tsc.entries[i] = entry;
1236 return i;
1237 }