src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/nvc0_graph_macros.h"
  36
  37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  39 #endif
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    if (sample_count > 8)
  49       return FALSE;
  50    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  51       return FALSE;
  52
  53    if (!util_format_is_supported(format, bindings))
  54       return FALSE;
  55
  56    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  57       if (util_format_get_blocksizebits(format) == 3 * 32)
  58          return FALSE;
  59
  60    /* transfers & shared are always supported */
  61    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  62                  PIPE_BIND_TRANSFER_WRITE |
  63                  PIPE_BIND_SHARED);
  64
  65    return (nvc0_format_table[format].usage & bindings) == bindings;
  66 }
  67
  68 static int
  69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  70 {
  71    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  72
  73    switch (param) {
  74    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  75    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  76       return 15;
  77    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  78       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  79    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  80       return 2048;
  81    case PIPE_CAP_MIN_TEXEL_OFFSET:
  82       return -8;
  83    case PIPE_CAP_MAX_TEXEL_OFFSET:
  84       return 7;
  85    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  86       return -32;
  87    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
  88       return 31;
  89    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  90    case PIPE_CAP_TEXTURE_SWIZZLE:
  91    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  92    case PIPE_CAP_NPOT_TEXTURES:
  93    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  94    case PIPE_CAP_ANISOTROPIC_FILTER:
  95    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  96    case PIPE_CAP_CUBE_MAP_ARRAY:
  97    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  98    case PIPE_CAP_TEXTURE_MULTISAMPLE:
  99       return 1;
 100    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 101       return 65536;
 102    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 103       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 104    case PIPE_CAP_TWO_SIDED_STENCIL:
 105    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 106    case PIPE_CAP_POINT_SPRITE:
 107    case PIPE_CAP_TGSI_TEXCOORD:
 108       return 1;
 109    case PIPE_CAP_SM3:
 110       return 1;
 111    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 112       return 330;
 113    case PIPE_CAP_MAX_RENDER_TARGETS:
 114       return 8;
 115    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 116       return 1;
 117    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 118    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 119    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 120       return 1;
 121    case PIPE_CAP_QUERY_TIMESTAMP:
 122    case PIPE_CAP_QUERY_TIME_ELAPSED:
 123    case PIPE_CAP_OCCLUSION_QUERY:
 124    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 125    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 126       return 1;
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 128       return 4;
 129    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 130    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 131       return 128;
 132    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 133    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 134       return 1024;
 135    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 136    case PIPE_CAP_INDEP_BLEND_ENABLE:
 137    case PIPE_CAP_INDEP_BLEND_FUNC:
 138       return 1;
 139    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 140    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 141       return 1;
 142    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 143    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 144       return 0;
 145    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 146       return 0;
 147    case PIPE_CAP_PRIMITIVE_RESTART:
 148    case PIPE_CAP_TGSI_INSTANCEID:
 149    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 150    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 151    case PIPE_CAP_CONDITIONAL_RENDER:
 152    case PIPE_CAP_TEXTURE_BARRIER:
 153    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 154    case PIPE_CAP_START_INSTANCE:
 155    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 156       return 1;
 157    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 158       return 0; /* state trackers will know better */
 159    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 160    case PIPE_CAP_USER_INDEX_BUFFERS:
 161    case PIPE_CAP_USER_VERTEX_BUFFERS:
 162       return 1;
 163    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 164       return 256;
 165    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 166       return 1; /* 256 for binding as RT, but that's not possible in GL */
 167    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 168       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 169    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 170    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 171    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 172       return 0;
 173    case PIPE_CAP_COMPUTE:
 174       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 175    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 176       return 1;
 177    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 178       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 179    case PIPE_CAP_ENDIANNESS:
 180       return PIPE_ENDIAN_LITTLE;
 181    case PIPE_CAP_TGSI_VS_LAYER:
 182    case PIPE_CAP_TEXTURE_GATHER_SM5:
 183    case PIPE_CAP_FAKE_SW_MSAA:
 184       return 0;
 185    case PIPE_CAP_MAX_VIEWPORTS:
 186       return 1;
 187    case PIPE_CAP_TEXTURE_QUERY_LOD:
 188    case PIPE_CAP_SAMPLE_SHADING:
 189       return 1;
 190    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 191       return 4;
 192    default:
 193       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 194       return 0;
 195    }
 196 }
 197
 198 static int
 199 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 200                              enum pipe_shader_cap param)
 201 {
 202    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 203
 204    switch (shader) {
 205    case PIPE_SHADER_VERTEX:
 206       /*
 207    case PIPE_SHADER_TESSELLATION_CONTROL:
 208    case PIPE_SHADER_TESSELLATION_EVALUATION:
 209       */
 210    case PIPE_SHADER_GEOMETRY:
 211    case PIPE_SHADER_FRAGMENT:
 212       break;
 213    case PIPE_SHADER_COMPUTE:
 214       if (class_3d < NVE4_3D_CLASS)
 215          return 0;
 216       break;
 217    default:
 218       return 0;
 219    }
 220
 221    switch (param) {
 222    case PIPE_SHADER_CAP_PREFERRED_IR:
 223       return PIPE_SHADER_IR_TGSI;
 224    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 225    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 226    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 227    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 228       return 16384;
 229    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 230       return 16;
 231    case PIPE_SHADER_CAP_MAX_INPUTS:
 232       if (shader == PIPE_SHADER_VERTEX)
 233          return 32;
 234       /* NOTE: These only count our slots for GENERIC varyings.
 235        * The address space may be larger, but the actual hard limit seems to be
 236        * less than what the address space layout permits, so don't add TEXCOORD,
 237        * COLOR, etc. here.
 238        */
 239       if (shader == PIPE_SHADER_FRAGMENT)
 240          return 0x1f0 / 16;
 241       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 242        * and excludes 0x60 per-patch inputs.
 243        */
 244       return 0x200 / 16;
 245    case PIPE_SHADER_CAP_MAX_CONSTS:
 246       return 65536 / 16;
 247    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 248       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 249          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 250       return NVC0_MAX_PIPE_CONSTBUFS;
 251    case PIPE_SHADER_CAP_MAX_ADDRS:
 252       return 1;
 253    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 254    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 255       return shader != PIPE_SHADER_FRAGMENT;
 256    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 257    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 258       return 1;
 259    case PIPE_SHADER_CAP_MAX_PREDS:
 260       return 0;
 261    case PIPE_SHADER_CAP_MAX_TEMPS:
 262       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 263    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 264       return 1;
 265    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 266       return 0;
 267    case PIPE_SHADER_CAP_SUBROUTINES:
 268       return 1;
 269    case PIPE_SHADER_CAP_INTEGERS:
 270       return 1;
 271    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 272       return 16; /* would be 32 in linked (OpenGL-style) mode */
 273    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 274       return 16; /* XXX not sure if more are really safe */
 275    default:
 276       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 277       return 0;
 278    }
 279 }
 280
 281 static float
 282 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 283 {
 284    switch (param) {
 285    case PIPE_CAPF_MAX_LINE_WIDTH:
 286    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 287       return 10.0f;
 288    case PIPE_CAPF_MAX_POINT_WIDTH:
 289       return 63.0f;
 290    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 291       return 63.375f;
 292    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 293       return 16.0f;
 294    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 295       return 15.0f;
 296    default:
 297       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 298       return 0.0f;
 299    }
 300 }
 301
 302 static int
 303 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 304                               enum pipe_compute_cap param, void *data)
 305 {
 306    uint64_t *data64 = (uint64_t *)data;
 307    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
 308
 309    switch (param) {
 310    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 311       data64[0] = 3;
 312       return 8;
 313    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 314       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
 315       data64[1] = 65535;
 316       data64[2] = 65535;
 317       return 24;
 318    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 319       data64[0] = 1024;
 320       data64[1] = 1024;
 321       data64[2] = 64;
 322       return 24;
 323    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 324       data64[0] = 1024;
 325       return 8;
 326    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 327       data64[0] = (uint64_t)1 << 40;
 328       return 8;
 329    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 330       data64[0] = 48 << 10;
 331       return 8;
 332    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 333       data64[0] = 512 << 10;
 334       return 8;
 335    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 336       data64[0] = 4096;
 337       return 8;
 338    default:
 339       return 0;
 340    }
 341 }
 342
 343 static void
 344 nvc0_screen_destroy(struct pipe_screen *pscreen)
 345 {
 346    struct nvc0_screen *screen = nvc0_screen(pscreen);
 347
 348    if (!nouveau_drm_screen_unref(&screen->base))
 349       return;
 350
 351    if (screen->base.fence.current) {
 352       struct nouveau_fence *current = NULL;
 353
 354       /* nouveau_fence_wait will create a new current fence, so wait on the
 355        * _current_ one, and remove both.
 356        */
 357       nouveau_fence_ref(screen->base.fence.current, &current);
 358       nouveau_fence_wait(current);
 359       nouveau_fence_ref(NULL, &current);
 360       nouveau_fence_ref(NULL, &screen->base.fence.current);
 361    }
 362    if (screen->base.pushbuf)
 363       screen->base.pushbuf->user_priv = NULL;
 364
 365    if (screen->blitter)
 366       nvc0_blitter_destroy(screen);
 367    if (screen->pm.prog) {
 368       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 369       nvc0_program_destroy(NULL, screen->pm.prog);
 370    }
 371
 372    nouveau_bo_ref(NULL, &screen->text);
 373    nouveau_bo_ref(NULL, &screen->uniform_bo);
 374    nouveau_bo_ref(NULL, &screen->tls);
 375    nouveau_bo_ref(NULL, &screen->txc);
 376    nouveau_bo_ref(NULL, &screen->fence.bo);
 377    nouveau_bo_ref(NULL, &screen->poly_cache);
 378    nouveau_bo_ref(NULL, &screen->parm);
 379
 380    nouveau_heap_destroy(&screen->lib_code);
 381    nouveau_heap_destroy(&screen->text_heap);
 382
 383    FREE(screen->tic.entries);
 384
 385    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 386
 387    nouveau_object_del(&screen->eng3d);
 388    nouveau_object_del(&screen->eng2d);
 389    nouveau_object_del(&screen->m2mf);
 390    nouveau_object_del(&screen->compute);
 391    nouveau_object_del(&screen->nvsw);
 392
 393    nouveau_screen_fini(&screen->base);
 394
 395    FREE(screen);
 396 }
 397
 398 static int
 399 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 400                      unsigned size, const uint32_t *data)
 401 {
 402    struct nouveau_pushbuf *push = screen->base.pushbuf;
 403
 404    size /= 4;
 405
 406    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 407    PUSH_DATA (push, (m - 0x3800) / 8);
 408    PUSH_DATA (push, pos);
 409    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 410    PUSH_DATA (push, pos);
 411    PUSH_DATAp(push, data, size);
 412
 413    return pos + size;
 414 }
 415
 416 static void
 417 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 418 {
 419    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 420    PUSH_DATA (push, 0xff);
 421    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 422    PUSH_DATA (push, 0xff);
 423    PUSH_DATA (push, 0xff);
 424    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 425    PUSH_DATA (push, 0xff);
 426    PUSH_DATA (push, 0xff);
 427    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 428    PUSH_DATA (push, 0x3f);
 429
 430    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 431    PUSH_DATA (push, (3 << 16) | 3);
 432    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 433    PUSH_DATA (push, (2 << 16) | 2);
 434    BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
 435    PUSH_DATA (push, 1);
 436
 437    BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 438    PUSH_DATA (push, 0);
 439    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 440    PUSH_DATA (push, 0x10);
 441    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 442    PUSH_DATA (push, 0x10);
 443    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 444    PUSH_DATA (push, 0x10);
 445    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 446    PUSH_DATA (push, 0x10);
 447    PUSH_DATA (push, 0x10);
 448    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 449    PUSH_DATA (push, 0x10);
 450    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 451    PUSH_DATA (push, 0xe);
 452
 453    BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
 454    PUSH_DATA (push, 1 << 12);
 455    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 456    PUSH_DATA (push, 0);
 457    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 458    PUSH_DATA (push, 3);
 459
 460    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 461    PUSH_DATA (push, 0x3fffff);
 462    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 463    PUSH_DATA (push, 1);
 464    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 465    PUSH_DATA (push, 1);
 466    BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 467    PUSH_DATA (push, 3);
 468
 469    if (obj_class >= NVE4_3D_CLASS) {
 470       BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 471       PUSH_DATA (push, 1);
 472    }
 473
 474    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 475     * are supposed to do */
 476 }
 477
 478 static void
 479 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 480 {
 481    struct nvc0_screen *screen = nvc0_screen(pscreen);
 482    struct nouveau_pushbuf *push = screen->base.pushbuf;
 483
 484    /* we need to do it after possible flush in MARK_RING */
 485    *sequence = ++screen->base.fence.sequence;
 486
 487    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
 488    PUSH_DATAh(push, screen->fence.bo->offset);
 489    PUSH_DATA (push, screen->fence.bo->offset);
 490    PUSH_DATA (push, *sequence);
 491    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 492               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 493 }
 494
 495 static u32
 496 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 497 {
 498    struct nvc0_screen *screen = nvc0_screen(pscreen);
 499    return screen->fence.map[0];
 500 }
 501
 502 static int
 503 nvc0_screen_init_compute(struct nvc0_screen *screen)
 504 {
 505    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 506
 507    switch (screen->base.device->chipset & ~0xf) {
 508    case 0xc0:
 509    case 0xd0:
 510       /* Using COMPUTE has weird effects on 3D state, we need to
 511        * investigate this further before enabling it by default.
 512        */
 513       if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
 514          return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 515       return 0;
 516    case 0xe0:
 517    case 0xf0:
 518    case 0x100:
 519       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 520    default:
 521       return -1;
 522    }
 523 }
 524
 525 boolean
 526 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 527                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 528 {
 529    struct nouveau_bo *bo = NULL;
 530    int ret;
 531    uint64_t size = (lpos + lneg) * 32 + cstack;
 532
 533    if (size >= (1 << 20)) {
 534       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 535       return FALSE;
 536    }
 537
 538    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 539    size  = align(size, 0x8000);
 540    size *= screen->mp_count;
 541
 542    size = align(size, 1 << 17);
 543
 544    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
 545                         NULL, &bo);
 546    if (ret) {
 547       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 548       return FALSE;
 549    }
 550    nouveau_bo_ref(NULL, &screen->tls);
 551    screen->tls = bo;
 552    return TRUE;
 553 }
 554
 555 #define FAIL_SCREEN_INIT(str, err)                    \
 556    do {                                               \
 557       NOUVEAU_ERR(str, err);                          \
 558       nvc0_screen_destroy(pscreen);                   \
 559       return NULL;                                    \
 560    } while(0)
 561
 562 struct pipe_screen *
 563 nvc0_screen_create(struct nouveau_device *dev)
 564 {
 565    struct nvc0_screen *screen;
 566    struct pipe_screen *pscreen;
 567    struct nouveau_object *chan;
 568    struct nouveau_pushbuf *push;
 569    uint64_t value;
 570    uint32_t obj_class;
 571    int ret;
 572    unsigned i;
 573    union nouveau_bo_config mm_config;
 574
 575    switch (dev->chipset & ~0xf) {
 576    case 0xc0:
 577    case 0xd0:
 578    case 0xe0:
 579    case 0xf0:
 580    case 0x100:
 581       break;
 582    default:
 583       return NULL;
 584    }
 585
 586    screen = CALLOC_STRUCT(nvc0_screen);
 587    if (!screen)
 588       return NULL;
 589    pscreen = &screen->base.base;
 590
 591    ret = nouveau_screen_init(&screen->base, dev);
 592    if (ret) {
 593       nvc0_screen_destroy(pscreen);
 594       return NULL;
 595    }
 596    chan = screen->base.channel;
 597    push = screen->base.pushbuf;
 598    push->user_priv = screen;
 599    push->rsvd_kick = 5;
 600
 601    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 602       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 603    screen->base.sysmem_bindings |=
 604       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 605
 606    pscreen->destroy = nvc0_screen_destroy;
 607    pscreen->context_create = nvc0_create;
 608    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 609    pscreen->get_param = nvc0_screen_get_param;
 610    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 611    pscreen->get_paramf = nvc0_screen_get_paramf;
 612    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 613
 614    nvc0_screen_init_resource_functions(pscreen);
 615
 616    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 617    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 618
 619    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
 620                         &screen->fence.bo);
 621    if (ret)
 622       goto fail;
 623    nouveau_bo_map(screen->fence.bo, 0, NULL);
 624    screen->fence.map = screen->fence.bo->map;
 625    screen->base.fence.emit = nvc0_screen_fence_emit;
 626    screen->base.fence.update = nvc0_screen_fence_update;
 627
 628
 629    ret = nouveau_object_new(chan,
 630                             (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
 631                             NULL, 0, &screen->nvsw);
 632    if (ret)
 633       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 634
 635
 636    switch (dev->chipset & ~0xf) {
 637    case 0x100:
 638    case 0xf0:
 639       obj_class = NVF0_P2MF_CLASS;
 640       break;
 641    case 0xe0:
 642       obj_class = NVE4_P2MF_CLASS;
 643       break;
 644    default:
 645       obj_class = NVC0_M2MF_CLASS;
 646       break;
 647    }
 648    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 649                             &screen->m2mf);
 650    if (ret)
 651       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 652
 653    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 654    PUSH_DATA (push, screen->m2mf->oclass);
 655    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 656       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 657       PUSH_DATA (push, 0xa0b5);
 658    }
 659
 660    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 661                             &screen->eng2d);
 662    if (ret)
 663       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 664
 665    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 666    PUSH_DATA (push, screen->eng2d->oclass);
 667    BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
 668    PUSH_DATA (push, 0);
 669    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 670    PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
 671    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 672    PUSH_DATA (push, 0);
 673    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 674    PUSH_DATA (push, 0);
 675    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 676    PUSH_DATA (push, 0x3f);
 677    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 678    PUSH_DATA (push, 1);
 679
 680    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 681    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 682    PUSH_DATA (push, screen->fence.bo->offset + 16);
 683
 684    switch (dev->chipset & ~0xf) {
 685    case 0x100:
 686    case 0xf0:
 687       obj_class = NVF0_3D_CLASS;
 688       break;
 689    case 0xe0:
 690       obj_class = NVE4_3D_CLASS;
 691       break;
 692    case 0xd0:
 693       obj_class = NVC8_3D_CLASS;
 694       break;
 695    case 0xc0:
 696    default:
 697       switch (dev->chipset) {
 698       case 0xc8:
 699          obj_class = NVC8_3D_CLASS;
 700          break;
 701       case 0xc1:
 702          obj_class = NVC1_3D_CLASS;
 703          break;
 704       default:
 705          obj_class = NVC0_3D_CLASS;
 706          break;
 707       }
 708       break;
 709    }
 710    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 711                             &screen->eng3d);
 712    if (ret)
 713       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 714    screen->base.class_3d = obj_class;
 715
 716    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 717    PUSH_DATA (push, screen->eng3d->oclass);
 718
 719    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 720    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 721
 722    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 723       /* kill shaders after about 1 second (at 100 MHz) */
 724       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 725       PUSH_DATA (push, 0x17);
 726    }
 727
 728    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
 729    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 730    for (i = 0; i < 8; ++i)
 731            PUSH_DATA(push, dev->drm_version >= 0x01000101);
 732
 733    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 734    PUSH_DATA (push, 1);
 735
 736    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 737    PUSH_DATA (push, 0);
 738    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 739    PUSH_DATA (push, 0);
 740    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 741    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 742    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 743    PUSH_DATA (push, 0);
 744    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 745    PUSH_DATA (push, 1);
 746    BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
 747    PUSH_DATA (push, 0);
 748    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 749    PUSH_DATA (push, 1);
 750    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 751    PUSH_DATA (push, 0);
 752    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 753       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 754       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 755    } else {
 756       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 757       PUSH_DATA (push, 15);
 758    }
 759    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 760    PUSH_DATA (push, 8); /* 128 */
 761    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 762    PUSH_DATA (push, 1);
 763    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 764       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 765       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 766    }
 767
 768    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 769
 770    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 771                         &screen->text);
 772    if (ret)
 773       goto fail;
 774
 775    /* XXX: getting a page fault at the end of the code buffer every few
 776     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 777     */
 778    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 779
 780    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
 781                         &screen->uniform_bo);
 782    if (ret)
 783       goto fail;
 784
 785    PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 786
 787    for (i = 0; i < 5; ++i) {
 788       /* TIC and TSC entries for each unit (nve4+ only) */
 789       /* auxiliary constants (6 user clip planes, base instance id) */
 790       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 791       PUSH_DATA (push, 512);
 792       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 793       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 794       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 795       PUSH_DATA (push, (15 << 4) | 1);
 796       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 797          unsigned j;
 798          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 799          PUSH_DATA (push, 0);
 800          for (j = 0; j < 8; ++j)
 801             PUSH_DATA(push, j);
 802       } else {
 803          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 804          PUSH_DATA (push, 0x54);
 805       }
 806    }
 807    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 808    PUSH_DATA (push, 0);
 809
 810    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 811    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 812    PUSH_DATA (push, 256);
 813    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 814    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 815    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 816    PUSH_DATA (push, 0);
 817    PUSH_DATAf(push, 0.0f);
 818    PUSH_DATAf(push, 0.0f);
 819    PUSH_DATAf(push, 0.0f);
 820    PUSH_DATAf(push, 0.0f);
 821    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 822    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 823    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 824
 825    if (dev->drm_version >= 0x01000101) {
 826       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 827       if (ret) {
 828          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 829          goto fail;
 830       }
 831    } else {
 832       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 833          value = (8 << 8) | 4;
 834       else
 835          value = (16 << 8) | 4;
 836    }
 837    screen->mp_count = value >> 8;
 838    screen->mp_count_compute = screen->mp_count;
 839
 840    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 841
 842    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 843    PUSH_DATAh(push, screen->text->offset);
 844    PUSH_DATA (push, screen->text->offset);
 845    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 846    PUSH_DATAh(push, screen->tls->offset);
 847    PUSH_DATA (push, screen->tls->offset);
 848    PUSH_DATA (push, screen->tls->size >> 32);
 849    PUSH_DATA (push, screen->tls->size);
 850    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 851    PUSH_DATA (push, 0);
 852    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 853    PUSH_DATA (push, 0);
 854
 855    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 856                         &screen->poly_cache);
 857    if (ret)
 858       goto fail;
 859
 860    BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 861    PUSH_DATAh(push, screen->poly_cache->offset);
 862    PUSH_DATA (push, screen->poly_cache->offset);
 863    PUSH_DATA (push, 3);
 864
 865    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
 866                         &screen->txc);
 867    if (ret)
 868       goto fail;
 869
 870    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 871    PUSH_DATAh(push, screen->txc->offset);
 872    PUSH_DATA (push, screen->txc->offset);
 873    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 874
 875    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 876    PUSH_DATAh(push, screen->txc->offset + 65536);
 877    PUSH_DATA (push, screen->txc->offset + 65536);
 878    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 879
 880    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 881    PUSH_DATA (push, 0);
 882    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 883    PUSH_DATA (push, 0);
 884    PUSH_DATA (push, 0);
 885    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 886    PUSH_DATA (push, 0x3f);
 887
 888    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 889    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 890    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 891    for (i = 0; i < 8 * 2; ++i)
 892       PUSH_DATA(push, 0);
 893    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 894    PUSH_DATA (push, 0);
 895    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 896    PUSH_DATA (push, 0);
 897
 898    /* neither scissors, viewport nor stencil mask should affect clears */
 899    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 900    PUSH_DATA (push, 0);
 901
 902    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 903    PUSH_DATA (push, 1);
 904    BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
 905    PUSH_DATAf(push, 0.0f);
 906    PUSH_DATAf(push, 1.0f);
 907    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 908    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 909
 910    /* We use scissors instead of exact view volume clipping,
 911     * so they're always enabled.
 912     */
 913    BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
 914    PUSH_DATA (push, 1);
 915    PUSH_DATA (push, 8192 << 16);
 916    PUSH_DATA (push, 8192 << 16);
 917
 918 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 919
 920    i = 0;
 921    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
 922    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
 923    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 924    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
 925    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
 926    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 927    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 928
 929    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
 930    PUSH_DATA (push, 1);
 931    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
 932    PUSH_DATA (push, 1);
 933    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 934    PUSH_DATA (push, 0x40);
 935    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
 936    PUSH_DATA (push, 0);
 937    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 938    PUSH_DATA (push, 0x30);
 939    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
 940    PUSH_DATA (push, 3);
 941    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
 942    PUSH_DATA (push, 0x20);
 943    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
 944    PUSH_DATA (push, 0x00);
 945
 946    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
 947    PUSH_DATA (push, 0);
 948    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
 949    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
 950
 951    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
 952
 953    if (nvc0_screen_init_compute(screen))
 954       goto fail;
 955
 956    PUSH_KICK (push);
 957
 958    screen->tic.entries = CALLOC(4096, sizeof(void *));
 959    screen->tsc.entries = screen->tic.entries + 2048;
 960
 961    mm_config.nvc0.tile_mode = 0;
 962    mm_config.nvc0.memtype = 0xfe0;
 963    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
 964
 965    if (!nvc0_blitter_create(screen))
 966       goto fail;
 967
 968    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 969
 970    return pscreen;
 971
 972 fail:
 973    nvc0_screen_destroy(pscreen);
 974    return NULL;
 975 }
 976
 977 int
 978 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 979 {
 980    int i = screen->tic.next;
 981
 982    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 983       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 984
 985    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 986
 987    if (screen->tic.entries[i])
 988       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 989
 990    screen->tic.entries[i] = entry;
 991    return i;
 992 }
 993
 994 int
 995 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 996 {
 997    int i = screen->tsc.next;
 998
 999    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1000       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1001
1002    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1003
1004    if (screen->tsc.entries[i])
1005       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1006
1007    screen->tsc.entries[i] = entry;
1008    return i;
1009 }