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nvc0: enable texture query lod
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/nvc0_graph_macros.h"
36
37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
39 #endif
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 if (sample_count > 8)
49 return FALSE;
50 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
51 return FALSE;
52
53 if (!util_format_is_supported(format, bindings))
54 return FALSE;
55
56 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
57 if (util_format_get_blocksizebits(format) == 3 * 32)
58 return FALSE;
59
60 /* transfers & shared are always supported */
61 bindings &= ~(PIPE_BIND_TRANSFER_READ |
62 PIPE_BIND_TRANSFER_WRITE |
63 PIPE_BIND_SHARED);
64
65 return (nvc0_format_table[format].usage & bindings) == bindings;
66 }
67
68 static int
69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
70 {
71 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
72
73 switch (param) {
74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
76 return 15;
77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
78 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
80 return 2048;
81 case PIPE_CAP_MIN_TEXEL_OFFSET:
82 return -8;
83 case PIPE_CAP_MAX_TEXEL_OFFSET:
84 return 7;
85 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
86 case PIPE_CAP_TEXTURE_SWIZZLE:
87 case PIPE_CAP_TEXTURE_SHADOW_MAP:
88 case PIPE_CAP_NPOT_TEXTURES:
89 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
90 case PIPE_CAP_ANISOTROPIC_FILTER:
91 case PIPE_CAP_SEAMLESS_CUBE_MAP:
92 case PIPE_CAP_CUBE_MAP_ARRAY:
93 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
94 case PIPE_CAP_TEXTURE_MULTISAMPLE:
95 return 1;
96 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
97 return 65536;
98 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
99 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
100 case PIPE_CAP_TWO_SIDED_STENCIL:
101 case PIPE_CAP_DEPTH_CLIP_DISABLE:
102 case PIPE_CAP_POINT_SPRITE:
103 case PIPE_CAP_TGSI_TEXCOORD:
104 return 1;
105 case PIPE_CAP_SM3:
106 return 1;
107 case PIPE_CAP_GLSL_FEATURE_LEVEL:
108 return 330;
109 case PIPE_CAP_MAX_RENDER_TARGETS:
110 return 8;
111 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
112 return 1;
113 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
114 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
115 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
116 return 1;
117 case PIPE_CAP_QUERY_TIMESTAMP:
118 case PIPE_CAP_QUERY_TIME_ELAPSED:
119 case PIPE_CAP_OCCLUSION_QUERY:
120 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
121 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
122 return 1;
123 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
124 return 4;
125 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
126 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
127 return 128;
128 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
129 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
130 return 1024;
131 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
132 case PIPE_CAP_INDEP_BLEND_ENABLE:
133 case PIPE_CAP_INDEP_BLEND_FUNC:
134 return 1;
135 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
136 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
137 return 1;
138 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
139 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
140 return 0;
141 case PIPE_CAP_SHADER_STENCIL_EXPORT:
142 return 0;
143 case PIPE_CAP_PRIMITIVE_RESTART:
144 case PIPE_CAP_TGSI_INSTANCEID:
145 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
146 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
147 case PIPE_CAP_CONDITIONAL_RENDER:
148 case PIPE_CAP_TEXTURE_BARRIER:
149 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
150 case PIPE_CAP_START_INSTANCE:
151 return 1;
152 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
153 return 0; /* state trackers will know better */
154 case PIPE_CAP_USER_CONSTANT_BUFFERS:
155 case PIPE_CAP_USER_INDEX_BUFFERS:
156 case PIPE_CAP_USER_VERTEX_BUFFERS:
157 return 1;
158 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
159 return 256;
160 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
161 return 1; /* 256 for binding as RT, but that's not possible in GL */
162 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
163 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
164 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
165 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
166 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
167 return 0;
168 case PIPE_CAP_COMPUTE:
169 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
170 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
171 return 1;
172 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
173 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
174 case PIPE_CAP_ENDIANNESS:
175 return PIPE_ENDIAN_LITTLE;
176 case PIPE_CAP_TGSI_VS_LAYER:
177 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
178 case PIPE_CAP_TEXTURE_GATHER_SM5:
179 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
180 case PIPE_CAP_FAKE_SW_MSAA:
181 return 0;
182 case PIPE_CAP_MAX_VIEWPORTS:
183 return 1;
184 case PIPE_CAP_TEXTURE_QUERY_LOD:
185 return 1;
186 default:
187 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
188 return 0;
189 }
190 }
191
192 static int
193 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
194 enum pipe_shader_cap param)
195 {
196 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
197
198 switch (shader) {
199 case PIPE_SHADER_VERTEX:
200 /*
201 case PIPE_SHADER_TESSELLATION_CONTROL:
202 case PIPE_SHADER_TESSELLATION_EVALUATION:
203 */
204 case PIPE_SHADER_GEOMETRY:
205 case PIPE_SHADER_FRAGMENT:
206 break;
207 case PIPE_SHADER_COMPUTE:
208 if (class_3d < NVE4_3D_CLASS)
209 return 0;
210 break;
211 default:
212 return 0;
213 }
214
215 switch (param) {
216 case PIPE_SHADER_CAP_PREFERRED_IR:
217 return PIPE_SHADER_IR_TGSI;
218 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
219 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
220 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
221 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
222 return 16384;
223 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
224 return 16;
225 case PIPE_SHADER_CAP_MAX_INPUTS:
226 if (shader == PIPE_SHADER_VERTEX)
227 return 32;
228 /* NOTE: These only count our slots for GENERIC varyings.
229 * The address space may be larger, but the actual hard limit seems to be
230 * less than what the address space layout permits, so don't add TEXCOORD,
231 * COLOR, etc. here.
232 */
233 if (shader == PIPE_SHADER_FRAGMENT)
234 return 0x1f0 / 16;
235 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
236 * and excludes 0x60 per-patch inputs.
237 */
238 return 0x200 / 16;
239 case PIPE_SHADER_CAP_MAX_CONSTS:
240 return 65536 / 16;
241 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
242 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
243 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
244 return NVC0_MAX_PIPE_CONSTBUFS;
245 case PIPE_SHADER_CAP_MAX_ADDRS:
246 return 1;
247 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
248 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
249 return shader != PIPE_SHADER_FRAGMENT;
250 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
251 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
252 return 1;
253 case PIPE_SHADER_CAP_MAX_PREDS:
254 return 0;
255 case PIPE_SHADER_CAP_MAX_TEMPS:
256 return NVC0_CAP_MAX_PROGRAM_TEMPS;
257 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
258 return 1;
259 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
260 return 0;
261 case PIPE_SHADER_CAP_SUBROUTINES:
262 return 1;
263 case PIPE_SHADER_CAP_INTEGERS:
264 return 1;
265 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
266 return 16; /* would be 32 in linked (OpenGL-style) mode */
267 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
268 return 16; /* XXX not sure if more are really safe */
269 default:
270 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
271 return 0;
272 }
273 }
274
275 static float
276 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
277 {
278 switch (param) {
279 case PIPE_CAPF_MAX_LINE_WIDTH:
280 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
281 return 10.0f;
282 case PIPE_CAPF_MAX_POINT_WIDTH:
283 return 63.0f;
284 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
285 return 63.375f;
286 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
287 return 16.0f;
288 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
289 return 15.0f;
290 default:
291 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
292 return 0.0f;
293 }
294 }
295
296 static int
297 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
298 enum pipe_compute_cap param, void *data)
299 {
300 uint64_t *data64 = (uint64_t *)data;
301 const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
302
303 switch (param) {
304 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
305 data64[0] = 3;
306 return 8;
307 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
308 data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
309 data64[1] = 65535;
310 data64[2] = 65535;
311 return 24;
312 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
313 data64[0] = 1024;
314 data64[1] = 1024;
315 data64[2] = 64;
316 return 24;
317 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
318 data64[0] = 1024;
319 return 8;
320 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
321 data64[0] = (uint64_t)1 << 40;
322 return 8;
323 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
324 data64[0] = 48 << 10;
325 return 8;
326 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
327 data64[0] = 512 << 10;
328 return 8;
329 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
330 data64[0] = 4096;
331 return 8;
332 default:
333 return 0;
334 }
335 }
336
337 static void
338 nvc0_screen_destroy(struct pipe_screen *pscreen)
339 {
340 struct nvc0_screen *screen = nvc0_screen(pscreen);
341
342 if (!nouveau_drm_screen_unref(&screen->base))
343 return;
344
345 if (screen->base.fence.current) {
346 struct nouveau_fence *current = NULL;
347
348 /* nouveau_fence_wait will create a new current fence, so wait on the
349 * _current_ one, and remove both.
350 */
351 nouveau_fence_ref(screen->base.fence.current, &current);
352 nouveau_fence_wait(current);
353 nouveau_fence_ref(NULL, &current);
354 nouveau_fence_ref(NULL, &screen->base.fence.current);
355 }
356 if (screen->base.pushbuf)
357 screen->base.pushbuf->user_priv = NULL;
358
359 if (screen->blitter)
360 nvc0_blitter_destroy(screen);
361 if (screen->pm.prog) {
362 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
363 nvc0_program_destroy(NULL, screen->pm.prog);
364 }
365
366 nouveau_bo_ref(NULL, &screen->text);
367 nouveau_bo_ref(NULL, &screen->uniform_bo);
368 nouveau_bo_ref(NULL, &screen->tls);
369 nouveau_bo_ref(NULL, &screen->txc);
370 nouveau_bo_ref(NULL, &screen->fence.bo);
371 nouveau_bo_ref(NULL, &screen->poly_cache);
372 nouveau_bo_ref(NULL, &screen->parm);
373
374 nouveau_heap_destroy(&screen->lib_code);
375 nouveau_heap_destroy(&screen->text_heap);
376
377 FREE(screen->tic.entries);
378
379 nouveau_mm_destroy(screen->mm_VRAM_fe0);
380
381 nouveau_object_del(&screen->eng3d);
382 nouveau_object_del(&screen->eng2d);
383 nouveau_object_del(&screen->m2mf);
384 nouveau_object_del(&screen->compute);
385 nouveau_object_del(&screen->nvsw);
386
387 nouveau_screen_fini(&screen->base);
388
389 FREE(screen);
390 }
391
392 static int
393 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
394 unsigned size, const uint32_t *data)
395 {
396 struct nouveau_pushbuf *push = screen->base.pushbuf;
397
398 size /= 4;
399
400 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
401 PUSH_DATA (push, (m - 0x3800) / 8);
402 PUSH_DATA (push, pos);
403 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
404 PUSH_DATA (push, pos);
405 PUSH_DATAp(push, data, size);
406
407 return pos + size;
408 }
409
410 static void
411 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
412 {
413 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
414 PUSH_DATA (push, 0xff);
415 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
416 PUSH_DATA (push, 0xff);
417 PUSH_DATA (push, 0xff);
418 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
419 PUSH_DATA (push, 0xff);
420 PUSH_DATA (push, 0xff);
421 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
422 PUSH_DATA (push, 0x3f);
423
424 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
425 PUSH_DATA (push, (3 << 16) | 3);
426 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
427 PUSH_DATA (push, (2 << 16) | 2);
428 BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
429 PUSH_DATA (push, 1);
430
431 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
432 PUSH_DATA (push, 0);
433 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
434 PUSH_DATA (push, 0x10);
435 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
436 PUSH_DATA (push, 0x10);
437 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
438 PUSH_DATA (push, 0x10);
439 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
440 PUSH_DATA (push, 0x10);
441 PUSH_DATA (push, 0x10);
442 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
443 PUSH_DATA (push, 0x10);
444 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
445 PUSH_DATA (push, 0xe);
446
447 BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
448 PUSH_DATA (push, 1 << 12);
449 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
450 PUSH_DATA (push, 0);
451 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
452 PUSH_DATA (push, 3);
453
454 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
455 PUSH_DATA (push, 0x3fffff);
456 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
457 PUSH_DATA (push, 1);
458 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
459 PUSH_DATA (push, 1);
460 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
461 PUSH_DATA (push, 3);
462
463 if (obj_class >= NVE4_3D_CLASS) {
464 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
465 PUSH_DATA (push, 1);
466 }
467
468 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
469 * are supposed to do */
470 }
471
472 static void
473 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
474 {
475 struct nvc0_screen *screen = nvc0_screen(pscreen);
476 struct nouveau_pushbuf *push = screen->base.pushbuf;
477
478 /* we need to do it after possible flush in MARK_RING */
479 *sequence = ++screen->base.fence.sequence;
480
481 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
482 PUSH_DATAh(push, screen->fence.bo->offset);
483 PUSH_DATA (push, screen->fence.bo->offset);
484 PUSH_DATA (push, *sequence);
485 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
486 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
487 }
488
489 static u32
490 nvc0_screen_fence_update(struct pipe_screen *pscreen)
491 {
492 struct nvc0_screen *screen = nvc0_screen(pscreen);
493 return screen->fence.map[0];
494 }
495
496 static int
497 nvc0_screen_init_compute(struct nvc0_screen *screen)
498 {
499 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
500
501 switch (screen->base.device->chipset & ~0xf) {
502 case 0xc0:
503 case 0xd0:
504 /* Using COMPUTE has weird effects on 3D state, we need to
505 * investigate this further before enabling it by default.
506 */
507 if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
508 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
509 return 0;
510 case 0xe0:
511 case 0xf0:
512 case 0x100:
513 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
514 default:
515 return -1;
516 }
517 }
518
519 boolean
520 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
521 uint32_t lpos, uint32_t lneg, uint32_t cstack)
522 {
523 struct nouveau_bo *bo = NULL;
524 int ret;
525 uint64_t size = (lpos + lneg) * 32 + cstack;
526
527 if (size >= (1 << 20)) {
528 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
529 return FALSE;
530 }
531
532 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
533 size = align(size, 0x8000);
534 size *= screen->mp_count;
535
536 size = align(size, 1 << 17);
537
538 ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
539 NULL, &bo);
540 if (ret) {
541 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
542 return FALSE;
543 }
544 nouveau_bo_ref(NULL, &screen->tls);
545 screen->tls = bo;
546 return TRUE;
547 }
548
549 #define FAIL_SCREEN_INIT(str, err) \
550 do { \
551 NOUVEAU_ERR(str, err); \
552 nvc0_screen_destroy(pscreen); \
553 return NULL; \
554 } while(0)
555
556 struct pipe_screen *
557 nvc0_screen_create(struct nouveau_device *dev)
558 {
559 struct nvc0_screen *screen;
560 struct pipe_screen *pscreen;
561 struct nouveau_object *chan;
562 struct nouveau_pushbuf *push;
563 uint64_t value;
564 uint32_t obj_class;
565 int ret;
566 unsigned i;
567 union nouveau_bo_config mm_config;
568
569 switch (dev->chipset & ~0xf) {
570 case 0xc0:
571 case 0xd0:
572 case 0xe0:
573 case 0xf0:
574 case 0x100:
575 break;
576 default:
577 return NULL;
578 }
579
580 screen = CALLOC_STRUCT(nvc0_screen);
581 if (!screen)
582 return NULL;
583 pscreen = &screen->base.base;
584
585 ret = nouveau_screen_init(&screen->base, dev);
586 if (ret) {
587 nvc0_screen_destroy(pscreen);
588 return NULL;
589 }
590 chan = screen->base.channel;
591 push = screen->base.pushbuf;
592 push->user_priv = screen;
593 push->rsvd_kick = 5;
594
595 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
596 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
597 screen->base.sysmem_bindings |=
598 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
599
600 pscreen->destroy = nvc0_screen_destroy;
601 pscreen->context_create = nvc0_create;
602 pscreen->is_format_supported = nvc0_screen_is_format_supported;
603 pscreen->get_param = nvc0_screen_get_param;
604 pscreen->get_shader_param = nvc0_screen_get_shader_param;
605 pscreen->get_paramf = nvc0_screen_get_paramf;
606 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
607
608 nvc0_screen_init_resource_functions(pscreen);
609
610 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
611 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
612
613 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
614 &screen->fence.bo);
615 if (ret)
616 goto fail;
617 nouveau_bo_map(screen->fence.bo, 0, NULL);
618 screen->fence.map = screen->fence.bo->map;
619 screen->base.fence.emit = nvc0_screen_fence_emit;
620 screen->base.fence.update = nvc0_screen_fence_update;
621
622
623 ret = nouveau_object_new(chan,
624 (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
625 NULL, 0, &screen->nvsw);
626 if (ret)
627 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
628
629
630 switch (dev->chipset & ~0xf) {
631 case 0x100:
632 case 0xf0:
633 obj_class = NVF0_P2MF_CLASS;
634 break;
635 case 0xe0:
636 obj_class = NVE4_P2MF_CLASS;
637 break;
638 default:
639 obj_class = NVC0_M2MF_CLASS;
640 break;
641 }
642 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
643 &screen->m2mf);
644 if (ret)
645 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
646
647 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
648 PUSH_DATA (push, screen->m2mf->oclass);
649 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
650 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
651 PUSH_DATA (push, 0xa0b5);
652 }
653
654 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
655 &screen->eng2d);
656 if (ret)
657 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
658
659 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
660 PUSH_DATA (push, screen->eng2d->oclass);
661 BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
662 PUSH_DATA (push, 0);
663 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
664 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
665 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
666 PUSH_DATA (push, 0);
667 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
668 PUSH_DATA (push, 0);
669 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
670 PUSH_DATA (push, 0x3f);
671 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
672 PUSH_DATA (push, 1);
673
674 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
675 PUSH_DATAh(push, screen->fence.bo->offset + 16);
676 PUSH_DATA (push, screen->fence.bo->offset + 16);
677
678 switch (dev->chipset & ~0xf) {
679 case 0x100:
680 case 0xf0:
681 obj_class = NVF0_3D_CLASS;
682 break;
683 case 0xe0:
684 obj_class = NVE4_3D_CLASS;
685 break;
686 case 0xd0:
687 obj_class = NVC8_3D_CLASS;
688 break;
689 case 0xc0:
690 default:
691 switch (dev->chipset) {
692 case 0xc8:
693 obj_class = NVC8_3D_CLASS;
694 break;
695 case 0xc1:
696 obj_class = NVC1_3D_CLASS;
697 break;
698 default:
699 obj_class = NVC0_3D_CLASS;
700 break;
701 }
702 break;
703 }
704 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
705 &screen->eng3d);
706 if (ret)
707 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
708 screen->base.class_3d = obj_class;
709
710 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
711 PUSH_DATA (push, screen->eng3d->oclass);
712
713 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
714 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
715
716 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
717 /* kill shaders after about 1 second (at 100 MHz) */
718 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
719 PUSH_DATA (push, 0x17);
720 }
721
722 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
723 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
724 for (i = 0; i < 8; ++i)
725 PUSH_DATA(push, dev->drm_version >= 0x01000101);
726
727 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
728 PUSH_DATA (push, 1);
729
730 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
731 PUSH_DATA (push, 0);
732 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
733 PUSH_DATA (push, 0);
734 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
735 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
736 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
737 PUSH_DATA (push, 0);
738 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
739 PUSH_DATA (push, 1);
740 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
741 PUSH_DATA (push, 0);
742 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
743 PUSH_DATA (push, 1);
744 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
745 PUSH_DATA (push, 0);
746 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
747 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
748 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
749 } else {
750 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
751 PUSH_DATA (push, 15);
752 }
753 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
754 PUSH_DATA (push, 8); /* 128 */
755 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
756 PUSH_DATA (push, 1);
757 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
758 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
759 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
760 }
761
762 nvc0_magic_3d_init(push, screen->eng3d->oclass);
763
764 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
765 &screen->text);
766 if (ret)
767 goto fail;
768
769 /* XXX: getting a page fault at the end of the code buffer every few
770 * launches, don't use the last 256 bytes to work around them - prefetch ?
771 */
772 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
773
774 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
775 &screen->uniform_bo);
776 if (ret)
777 goto fail;
778
779 PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
780
781 for (i = 0; i < 5; ++i) {
782 /* TIC and TSC entries for each unit (nve4+ only) */
783 /* auxiliary constants (6 user clip planes, base instance id) */
784 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
785 PUSH_DATA (push, 512);
786 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
787 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
788 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
789 PUSH_DATA (push, (15 << 4) | 1);
790 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
791 unsigned j;
792 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
793 PUSH_DATA (push, 0);
794 for (j = 0; j < 8; ++j)
795 PUSH_DATA(push, j);
796 } else {
797 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
798 PUSH_DATA (push, 0x54);
799 }
800 }
801 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
802 PUSH_DATA (push, 0);
803
804 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
805 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
806 PUSH_DATA (push, 256);
807 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
808 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
809 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
810 PUSH_DATA (push, 0);
811 PUSH_DATAf(push, 0.0f);
812 PUSH_DATAf(push, 0.0f);
813 PUSH_DATAf(push, 0.0f);
814 PUSH_DATAf(push, 0.0f);
815 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
816 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
817 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
818
819 if (dev->drm_version >= 0x01000101) {
820 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
821 if (ret) {
822 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
823 goto fail;
824 }
825 } else {
826 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
827 value = (8 << 8) | 4;
828 else
829 value = (16 << 8) | 4;
830 }
831 screen->mp_count = value >> 8;
832 screen->mp_count_compute = screen->mp_count;
833
834 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
835
836 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
837 PUSH_DATAh(push, screen->text->offset);
838 PUSH_DATA (push, screen->text->offset);
839 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
840 PUSH_DATAh(push, screen->tls->offset);
841 PUSH_DATA (push, screen->tls->offset);
842 PUSH_DATA (push, screen->tls->size >> 32);
843 PUSH_DATA (push, screen->tls->size);
844 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
845 PUSH_DATA (push, 0);
846 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
847 PUSH_DATA (push, 0);
848
849 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
850 &screen->poly_cache);
851 if (ret)
852 goto fail;
853
854 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
855 PUSH_DATAh(push, screen->poly_cache->offset);
856 PUSH_DATA (push, screen->poly_cache->offset);
857 PUSH_DATA (push, 3);
858
859 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
860 &screen->txc);
861 if (ret)
862 goto fail;
863
864 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
865 PUSH_DATAh(push, screen->txc->offset);
866 PUSH_DATA (push, screen->txc->offset);
867 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
868
869 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
870 PUSH_DATAh(push, screen->txc->offset + 65536);
871 PUSH_DATA (push, screen->txc->offset + 65536);
872 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
873
874 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
875 PUSH_DATA (push, 0);
876 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
877 PUSH_DATA (push, 0);
878 PUSH_DATA (push, 0);
879 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
880 PUSH_DATA (push, 0x3f);
881
882 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
883 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
884 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
885 for (i = 0; i < 8 * 2; ++i)
886 PUSH_DATA(push, 0);
887 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
888 PUSH_DATA (push, 0);
889 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
890 PUSH_DATA (push, 0);
891
892 /* neither scissors, viewport nor stencil mask should affect clears */
893 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
894 PUSH_DATA (push, 0);
895
896 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
897 PUSH_DATA (push, 1);
898 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
899 PUSH_DATAf(push, 0.0f);
900 PUSH_DATAf(push, 1.0f);
901 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
902 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
903
904 /* We use scissors instead of exact view volume clipping,
905 * so they're always enabled.
906 */
907 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
908 PUSH_DATA (push, 1);
909 PUSH_DATA (push, 8192 << 16);
910 PUSH_DATA (push, 8192 << 16);
911
912 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
913
914 i = 0;
915 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
916 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
917 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
918 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
919 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
920 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
921 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
922
923 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
924 PUSH_DATA (push, 1);
925 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
926 PUSH_DATA (push, 1);
927 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
928 PUSH_DATA (push, 0x40);
929 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
930 PUSH_DATA (push, 0);
931 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
932 PUSH_DATA (push, 0x30);
933 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
934 PUSH_DATA (push, 3);
935 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
936 PUSH_DATA (push, 0x20);
937 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
938 PUSH_DATA (push, 0x00);
939
940 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
941 PUSH_DATA (push, 0);
942 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
943 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
944
945 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
946
947 if (nvc0_screen_init_compute(screen))
948 goto fail;
949
950 PUSH_KICK (push);
951
952 screen->tic.entries = CALLOC(4096, sizeof(void *));
953 screen->tsc.entries = screen->tic.entries + 2048;
954
955 mm_config.nvc0.tile_mode = 0;
956 mm_config.nvc0.memtype = 0xfe0;
957 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
958
959 if (!nvc0_blitter_create(screen))
960 goto fail;
961
962 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
963
964 return pscreen;
965
966 fail:
967 nvc0_screen_destroy(pscreen);
968 return NULL;
969 }
970
971 int
972 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
973 {
974 int i = screen->tic.next;
975
976 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
977 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
978
979 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
980
981 if (screen->tic.entries[i])
982 nv50_tic_entry(screen->tic.entries[i])->id = -1;
983
984 screen->tic.entries[i] = entry;
985 return i;
986 }
987
988 int
989 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
990 {
991 int i = screen->tsc.next;
992
993 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
994 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
995
996 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
997
998 if (screen->tsc.entries[i])
999 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1000
1001 screen->tsc.entries[i] = entry;
1002 return i;
1003 }