src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/nvc0_graph_macros.h"
  36
  37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  39 #endif
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    if (sample_count > 8)
  49       return FALSE;
  50    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  51       return FALSE;
  52
  53    if (!util_format_is_supported(format, bindings))
  54       return FALSE;
  55
  56    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  57       if (util_format_get_blocksizebits(format) == 3 * 32)
  58          return FALSE;
  59
  60    /* transfers & shared are always supported */
  61    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  62                  PIPE_BIND_TRANSFER_WRITE |
  63                  PIPE_BIND_SHARED);
  64
  65    return (nvc0_format_table[format].usage & bindings) == bindings;
  66 }
  67
  68 static int
  69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  70 {
  71    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  72
  73    switch (param) {
  74    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  75    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  76       return 15;
  77    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  78       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  79    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  80       return 2048;
  81    case PIPE_CAP_MIN_TEXEL_OFFSET:
  82       return -8;
  83    case PIPE_CAP_MAX_TEXEL_OFFSET:
  84       return 7;
  85    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  86       return -32;
  87    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
  88       return 31;
  89    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  90    case PIPE_CAP_TEXTURE_SWIZZLE:
  91    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  92    case PIPE_CAP_NPOT_TEXTURES:
  93    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  94    case PIPE_CAP_ANISOTROPIC_FILTER:
  95    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  96    case PIPE_CAP_CUBE_MAP_ARRAY:
  97    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  98    case PIPE_CAP_TEXTURE_MULTISAMPLE:
  99       return 1;
 100    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 101       return 65536;
 102    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 103       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 104    case PIPE_CAP_TWO_SIDED_STENCIL:
 105    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 106    case PIPE_CAP_POINT_SPRITE:
 107    case PIPE_CAP_TGSI_TEXCOORD:
 108       return 1;
 109    case PIPE_CAP_SM3:
 110       return 1;
 111    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 112       return 330;
 113    case PIPE_CAP_MAX_RENDER_TARGETS:
 114       return 8;
 115    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 116       return 1;
 117    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 118    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 119    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 120       return 1;
 121    case PIPE_CAP_QUERY_TIMESTAMP:
 122    case PIPE_CAP_QUERY_TIME_ELAPSED:
 123    case PIPE_CAP_OCCLUSION_QUERY:
 124    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 125    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 126       return 1;
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 128       return 4;
 129    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 130    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 131       return 128;
 132    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 133    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 134       return 1024;
 135    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 136    case PIPE_CAP_INDEP_BLEND_ENABLE:
 137    case PIPE_CAP_INDEP_BLEND_FUNC:
 138       return 1;
 139    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 140    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 141       return 1;
 142    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 143    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 144       return 0;
 145    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 146       return 0;
 147    case PIPE_CAP_PRIMITIVE_RESTART:
 148    case PIPE_CAP_TGSI_INSTANCEID:
 149    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 150    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 151    case PIPE_CAP_CONDITIONAL_RENDER:
 152    case PIPE_CAP_TEXTURE_BARRIER:
 153    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 154    case PIPE_CAP_START_INSTANCE:
 155    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 156       return 1;
 157    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 158       return 0; /* state trackers will know better */
 159    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 160    case PIPE_CAP_USER_INDEX_BUFFERS:
 161    case PIPE_CAP_USER_VERTEX_BUFFERS:
 162       return 1;
 163    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 164       return 256;
 165    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 166       return 1; /* 256 for binding as RT, but that's not possible in GL */
 167    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 168       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 169    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 170    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 171    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 172       return 0;
 173    case PIPE_CAP_COMPUTE:
 174       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 175    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 176       return 1;
 177    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 178       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 179    case PIPE_CAP_ENDIANNESS:
 180       return PIPE_ENDIAN_LITTLE;
 181    case PIPE_CAP_TGSI_VS_LAYER:
 182    case PIPE_CAP_TEXTURE_GATHER_SM5:
 183    case PIPE_CAP_FAKE_SW_MSAA:
 184       return 0;
 185    case PIPE_CAP_MAX_VIEWPORTS:
 186       return 1;
 187    case PIPE_CAP_TEXTURE_QUERY_LOD:
 188    case PIPE_CAP_SAMPLE_SHADING:
 189    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 190       return 1;
 191    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 192       return 4;
 193    default:
 194       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 195       return 0;
 196    }
 197 }
 198
 199 static int
 200 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 201                              enum pipe_shader_cap param)
 202 {
 203    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 204
 205    switch (shader) {
 206    case PIPE_SHADER_VERTEX:
 207       /*
 208    case PIPE_SHADER_TESSELLATION_CONTROL:
 209    case PIPE_SHADER_TESSELLATION_EVALUATION:
 210       */
 211    case PIPE_SHADER_GEOMETRY:
 212    case PIPE_SHADER_FRAGMENT:
 213       break;
 214    case PIPE_SHADER_COMPUTE:
 215       if (class_3d < NVE4_3D_CLASS)
 216          return 0;
 217       break;
 218    default:
 219       return 0;
 220    }
 221
 222    switch (param) {
 223    case PIPE_SHADER_CAP_PREFERRED_IR:
 224       return PIPE_SHADER_IR_TGSI;
 225    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 226    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 227    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 228    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 229       return 16384;
 230    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 231       return 16;
 232    case PIPE_SHADER_CAP_MAX_INPUTS:
 233       if (shader == PIPE_SHADER_VERTEX)
 234          return 32;
 235       /* NOTE: These only count our slots for GENERIC varyings.
 236        * The address space may be larger, but the actual hard limit seems to be
 237        * less than what the address space layout permits, so don't add TEXCOORD,
 238        * COLOR, etc. here.
 239        */
 240       if (shader == PIPE_SHADER_FRAGMENT)
 241          return 0x1f0 / 16;
 242       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 243        * and excludes 0x60 per-patch inputs.
 244        */
 245       return 0x200 / 16;
 246    case PIPE_SHADER_CAP_MAX_CONSTS:
 247       return 65536 / 16;
 248    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 249       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 250          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 251       return NVC0_MAX_PIPE_CONSTBUFS;
 252    case PIPE_SHADER_CAP_MAX_ADDRS:
 253       return 1;
 254    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 255    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 256       return shader != PIPE_SHADER_FRAGMENT;
 257    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 258    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 259       return 1;
 260    case PIPE_SHADER_CAP_MAX_PREDS:
 261       return 0;
 262    case PIPE_SHADER_CAP_MAX_TEMPS:
 263       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 264    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 265       return 1;
 266    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 267       return 0;
 268    case PIPE_SHADER_CAP_SUBROUTINES:
 269       return 1;
 270    case PIPE_SHADER_CAP_INTEGERS:
 271       return 1;
 272    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 273       return 16; /* would be 32 in linked (OpenGL-style) mode */
 274    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 275       return 16; /* XXX not sure if more are really safe */
 276    default:
 277       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 278       return 0;
 279    }
 280 }
 281
 282 static float
 283 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 284 {
 285    switch (param) {
 286    case PIPE_CAPF_MAX_LINE_WIDTH:
 287    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 288       return 10.0f;
 289    case PIPE_CAPF_MAX_POINT_WIDTH:
 290       return 63.0f;
 291    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 292       return 63.375f;
 293    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 294       return 16.0f;
 295    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 296       return 15.0f;
 297    default:
 298       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 299       return 0.0f;
 300    }
 301 }
 302
 303 static int
 304 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 305                               enum pipe_compute_cap param, void *data)
 306 {
 307    uint64_t *data64 = (uint64_t *)data;
 308    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
 309
 310    switch (param) {
 311    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 312       data64[0] = 3;
 313       return 8;
 314    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 315       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
 316       data64[1] = 65535;
 317       data64[2] = 65535;
 318       return 24;
 319    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 320       data64[0] = 1024;
 321       data64[1] = 1024;
 322       data64[2] = 64;
 323       return 24;
 324    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 325       data64[0] = 1024;
 326       return 8;
 327    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 328       data64[0] = (uint64_t)1 << 40;
 329       return 8;
 330    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 331       data64[0] = 48 << 10;
 332       return 8;
 333    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 334       data64[0] = 512 << 10;
 335       return 8;
 336    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 337       data64[0] = 4096;
 338       return 8;
 339    default:
 340       return 0;
 341    }
 342 }
 343
 344 static void
 345 nvc0_screen_destroy(struct pipe_screen *pscreen)
 346 {
 347    struct nvc0_screen *screen = nvc0_screen(pscreen);
 348
 349    if (!nouveau_drm_screen_unref(&screen->base))
 350       return;
 351
 352    if (screen->base.fence.current) {
 353       struct nouveau_fence *current = NULL;
 354
 355       /* nouveau_fence_wait will create a new current fence, so wait on the
 356        * _current_ one, and remove both.
 357        */
 358       nouveau_fence_ref(screen->base.fence.current, &current);
 359       nouveau_fence_wait(current);
 360       nouveau_fence_ref(NULL, &current);
 361       nouveau_fence_ref(NULL, &screen->base.fence.current);
 362    }
 363    if (screen->base.pushbuf)
 364       screen->base.pushbuf->user_priv = NULL;
 365
 366    if (screen->blitter)
 367       nvc0_blitter_destroy(screen);
 368    if (screen->pm.prog) {
 369       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 370       nvc0_program_destroy(NULL, screen->pm.prog);
 371    }
 372
 373    nouveau_bo_ref(NULL, &screen->text);
 374    nouveau_bo_ref(NULL, &screen->uniform_bo);
 375    nouveau_bo_ref(NULL, &screen->tls);
 376    nouveau_bo_ref(NULL, &screen->txc);
 377    nouveau_bo_ref(NULL, &screen->fence.bo);
 378    nouveau_bo_ref(NULL, &screen->poly_cache);
 379    nouveau_bo_ref(NULL, &screen->parm);
 380
 381    nouveau_heap_destroy(&screen->lib_code);
 382    nouveau_heap_destroy(&screen->text_heap);
 383
 384    FREE(screen->tic.entries);
 385
 386    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 387
 388    nouveau_object_del(&screen->eng3d);
 389    nouveau_object_del(&screen->eng2d);
 390    nouveau_object_del(&screen->m2mf);
 391    nouveau_object_del(&screen->compute);
 392    nouveau_object_del(&screen->nvsw);
 393
 394    nouveau_screen_fini(&screen->base);
 395
 396    FREE(screen);
 397 }
 398
 399 static int
 400 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 401                      unsigned size, const uint32_t *data)
 402 {
 403    struct nouveau_pushbuf *push = screen->base.pushbuf;
 404
 405    size /= 4;
 406
 407    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 408    PUSH_DATA (push, (m - 0x3800) / 8);
 409    PUSH_DATA (push, pos);
 410    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 411    PUSH_DATA (push, pos);
 412    PUSH_DATAp(push, data, size);
 413
 414    return pos + size;
 415 }
 416
 417 static void
 418 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 419 {
 420    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 421    PUSH_DATA (push, 0xff);
 422    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 423    PUSH_DATA (push, 0xff);
 424    PUSH_DATA (push, 0xff);
 425    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 426    PUSH_DATA (push, 0xff);
 427    PUSH_DATA (push, 0xff);
 428    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 429    PUSH_DATA (push, 0x3f);
 430
 431    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 432    PUSH_DATA (push, (3 << 16) | 3);
 433    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 434    PUSH_DATA (push, (2 << 16) | 2);
 435    BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
 436    PUSH_DATA (push, 1);
 437
 438    BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 439    PUSH_DATA (push, 0);
 440    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 441    PUSH_DATA (push, 0x10);
 442    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 443    PUSH_DATA (push, 0x10);
 444    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 445    PUSH_DATA (push, 0x10);
 446    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 447    PUSH_DATA (push, 0x10);
 448    PUSH_DATA (push, 0x10);
 449    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 450    PUSH_DATA (push, 0x10);
 451    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 452    PUSH_DATA (push, 0xe);
 453
 454    BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
 455    PUSH_DATA (push, 1 << 12);
 456    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 457    PUSH_DATA (push, 0);
 458    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 459    PUSH_DATA (push, 3);
 460
 461    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 462    PUSH_DATA (push, 0x3fffff);
 463    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 464    PUSH_DATA (push, 1);
 465    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 466    PUSH_DATA (push, 1);
 467    BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 468    PUSH_DATA (push, 3);
 469
 470    if (obj_class >= NVE4_3D_CLASS) {
 471       BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 472       PUSH_DATA (push, 1);
 473    }
 474
 475    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 476     * are supposed to do */
 477 }
 478
 479 static void
 480 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 481 {
 482    struct nvc0_screen *screen = nvc0_screen(pscreen);
 483    struct nouveau_pushbuf *push = screen->base.pushbuf;
 484
 485    /* we need to do it after possible flush in MARK_RING */
 486    *sequence = ++screen->base.fence.sequence;
 487
 488    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
 489    PUSH_DATAh(push, screen->fence.bo->offset);
 490    PUSH_DATA (push, screen->fence.bo->offset);
 491    PUSH_DATA (push, *sequence);
 492    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 493               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 494 }
 495
 496 static u32
 497 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 498 {
 499    struct nvc0_screen *screen = nvc0_screen(pscreen);
 500    return screen->fence.map[0];
 501 }
 502
 503 static int
 504 nvc0_screen_init_compute(struct nvc0_screen *screen)
 505 {
 506    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 507
 508    switch (screen->base.device->chipset & ~0xf) {
 509    case 0xc0:
 510    case 0xd0:
 511       /* Using COMPUTE has weird effects on 3D state, we need to
 512        * investigate this further before enabling it by default.
 513        */
 514       if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
 515          return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 516       return 0;
 517    case 0xe0:
 518    case 0xf0:
 519    case 0x100:
 520       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 521    default:
 522       return -1;
 523    }
 524 }
 525
 526 boolean
 527 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 528                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 529 {
 530    struct nouveau_bo *bo = NULL;
 531    int ret;
 532    uint64_t size = (lpos + lneg) * 32 + cstack;
 533
 534    if (size >= (1 << 20)) {
 535       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 536       return FALSE;
 537    }
 538
 539    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 540    size  = align(size, 0x8000);
 541    size *= screen->mp_count;
 542
 543    size = align(size, 1 << 17);
 544
 545    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
 546                         NULL, &bo);
 547    if (ret) {
 548       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 549       return FALSE;
 550    }
 551    nouveau_bo_ref(NULL, &screen->tls);
 552    screen->tls = bo;
 553    return TRUE;
 554 }
 555
 556 #define FAIL_SCREEN_INIT(str, err)                    \
 557    do {                                               \
 558       NOUVEAU_ERR(str, err);                          \
 559       nvc0_screen_destroy(pscreen);                   \
 560       return NULL;                                    \
 561    } while(0)
 562
 563 struct pipe_screen *
 564 nvc0_screen_create(struct nouveau_device *dev)
 565 {
 566    struct nvc0_screen *screen;
 567    struct pipe_screen *pscreen;
 568    struct nouveau_object *chan;
 569    struct nouveau_pushbuf *push;
 570    uint64_t value;
 571    uint32_t obj_class;
 572    int ret;
 573    unsigned i;
 574    union nouveau_bo_config mm_config;
 575
 576    switch (dev->chipset & ~0xf) {
 577    case 0xc0:
 578    case 0xd0:
 579    case 0xe0:
 580    case 0xf0:
 581    case 0x100:
 582       break;
 583    default:
 584       return NULL;
 585    }
 586
 587    screen = CALLOC_STRUCT(nvc0_screen);
 588    if (!screen)
 589       return NULL;
 590    pscreen = &screen->base.base;
 591
 592    ret = nouveau_screen_init(&screen->base, dev);
 593    if (ret) {
 594       nvc0_screen_destroy(pscreen);
 595       return NULL;
 596    }
 597    chan = screen->base.channel;
 598    push = screen->base.pushbuf;
 599    push->user_priv = screen;
 600    push->rsvd_kick = 5;
 601
 602    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 603       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 604    screen->base.sysmem_bindings |=
 605       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 606
 607    pscreen->destroy = nvc0_screen_destroy;
 608    pscreen->context_create = nvc0_create;
 609    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 610    pscreen->get_param = nvc0_screen_get_param;
 611    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 612    pscreen->get_paramf = nvc0_screen_get_paramf;
 613    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 614
 615    nvc0_screen_init_resource_functions(pscreen);
 616
 617    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 618    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 619
 620    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
 621                         &screen->fence.bo);
 622    if (ret)
 623       goto fail;
 624    nouveau_bo_map(screen->fence.bo, 0, NULL);
 625    screen->fence.map = screen->fence.bo->map;
 626    screen->base.fence.emit = nvc0_screen_fence_emit;
 627    screen->base.fence.update = nvc0_screen_fence_update;
 628
 629
 630    ret = nouveau_object_new(chan,
 631                             (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
 632                             NULL, 0, &screen->nvsw);
 633    if (ret)
 634       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 635
 636
 637    switch (dev->chipset & ~0xf) {
 638    case 0x100:
 639    case 0xf0:
 640       obj_class = NVF0_P2MF_CLASS;
 641       break;
 642    case 0xe0:
 643       obj_class = NVE4_P2MF_CLASS;
 644       break;
 645    default:
 646       obj_class = NVC0_M2MF_CLASS;
 647       break;
 648    }
 649    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 650                             &screen->m2mf);
 651    if (ret)
 652       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 653
 654    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 655    PUSH_DATA (push, screen->m2mf->oclass);
 656    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 657       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 658       PUSH_DATA (push, 0xa0b5);
 659    }
 660
 661    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 662                             &screen->eng2d);
 663    if (ret)
 664       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 665
 666    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 667    PUSH_DATA (push, screen->eng2d->oclass);
 668    BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
 669    PUSH_DATA (push, 0);
 670    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 671    PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
 672    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 673    PUSH_DATA (push, 0);
 674    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 675    PUSH_DATA (push, 0);
 676    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 677    PUSH_DATA (push, 0x3f);
 678    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 679    PUSH_DATA (push, 1);
 680    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 681    PUSH_DATA (push, NVC0_2D_COND_MODE_ALWAYS);
 682
 683    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 684    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 685    PUSH_DATA (push, screen->fence.bo->offset + 16);
 686
 687    switch (dev->chipset & ~0xf) {
 688    case 0x100:
 689    case 0xf0:
 690       obj_class = NVF0_3D_CLASS;
 691       break;
 692    case 0xe0:
 693       obj_class = NVE4_3D_CLASS;
 694       break;
 695    case 0xd0:
 696       obj_class = NVC8_3D_CLASS;
 697       break;
 698    case 0xc0:
 699    default:
 700       switch (dev->chipset) {
 701       case 0xc8:
 702          obj_class = NVC8_3D_CLASS;
 703          break;
 704       case 0xc1:
 705          obj_class = NVC1_3D_CLASS;
 706          break;
 707       default:
 708          obj_class = NVC0_3D_CLASS;
 709          break;
 710       }
 711       break;
 712    }
 713    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 714                             &screen->eng3d);
 715    if (ret)
 716       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 717    screen->base.class_3d = obj_class;
 718
 719    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 720    PUSH_DATA (push, screen->eng3d->oclass);
 721
 722    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 723    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 724
 725    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 726       /* kill shaders after about 1 second (at 100 MHz) */
 727       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 728       PUSH_DATA (push, 0x17);
 729    }
 730
 731    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
 732    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 733    for (i = 0; i < 8; ++i)
 734            PUSH_DATA(push, dev->drm_version >= 0x01000101);
 735
 736    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 737    PUSH_DATA (push, 1);
 738
 739    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 740    PUSH_DATA (push, 0);
 741    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 742    PUSH_DATA (push, 0);
 743    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 744    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 745    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 746    PUSH_DATA (push, 0);
 747    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 748    PUSH_DATA (push, 1);
 749    BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
 750    PUSH_DATA (push, 0);
 751    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 752    PUSH_DATA (push, 1);
 753    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 754    PUSH_DATA (push, 0);
 755    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 756       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 757       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 758    } else {
 759       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 760       PUSH_DATA (push, 15);
 761    }
 762    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 763    PUSH_DATA (push, 8); /* 128 */
 764    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 765    PUSH_DATA (push, 1);
 766    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 767       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 768       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 769    }
 770
 771    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 772
 773    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 774                         &screen->text);
 775    if (ret)
 776       goto fail;
 777
 778    /* XXX: getting a page fault at the end of the code buffer every few
 779     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 780     */
 781    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 782
 783    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
 784                         &screen->uniform_bo);
 785    if (ret)
 786       goto fail;
 787
 788    PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 789
 790    for (i = 0; i < 5; ++i) {
 791       /* TIC and TSC entries for each unit (nve4+ only) */
 792       /* auxiliary constants (6 user clip planes, base instance id) */
 793       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 794       PUSH_DATA (push, 512);
 795       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 796       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 797       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 798       PUSH_DATA (push, (15 << 4) | 1);
 799       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 800          unsigned j;
 801          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 802          PUSH_DATA (push, 0);
 803          for (j = 0; j < 8; ++j)
 804             PUSH_DATA(push, j);
 805       } else {
 806          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 807          PUSH_DATA (push, 0x54);
 808       }
 809    }
 810    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 811    PUSH_DATA (push, 0);
 812
 813    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 814    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 815    PUSH_DATA (push, 256);
 816    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 817    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 818    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 819    PUSH_DATA (push, 0);
 820    PUSH_DATAf(push, 0.0f);
 821    PUSH_DATAf(push, 0.0f);
 822    PUSH_DATAf(push, 0.0f);
 823    PUSH_DATAf(push, 0.0f);
 824    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 825    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 826    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 827
 828    if (dev->drm_version >= 0x01000101) {
 829       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 830       if (ret) {
 831          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 832          goto fail;
 833       }
 834    } else {
 835       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 836          value = (8 << 8) | 4;
 837       else
 838          value = (16 << 8) | 4;
 839    }
 840    screen->mp_count = value >> 8;
 841    screen->mp_count_compute = screen->mp_count;
 842
 843    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 844
 845    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 846    PUSH_DATAh(push, screen->text->offset);
 847    PUSH_DATA (push, screen->text->offset);
 848    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 849    PUSH_DATAh(push, screen->tls->offset);
 850    PUSH_DATA (push, screen->tls->offset);
 851    PUSH_DATA (push, screen->tls->size >> 32);
 852    PUSH_DATA (push, screen->tls->size);
 853    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 854    PUSH_DATA (push, 0);
 855    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 856    PUSH_DATA (push, 0);
 857
 858    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 859                         &screen->poly_cache);
 860    if (ret)
 861       goto fail;
 862
 863    BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 864    PUSH_DATAh(push, screen->poly_cache->offset);
 865    PUSH_DATA (push, screen->poly_cache->offset);
 866    PUSH_DATA (push, 3);
 867
 868    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
 869                         &screen->txc);
 870    if (ret)
 871       goto fail;
 872
 873    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 874    PUSH_DATAh(push, screen->txc->offset);
 875    PUSH_DATA (push, screen->txc->offset);
 876    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 877
 878    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 879    PUSH_DATAh(push, screen->txc->offset + 65536);
 880    PUSH_DATA (push, screen->txc->offset + 65536);
 881    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 882
 883    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 884    PUSH_DATA (push, 0);
 885    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 886    PUSH_DATA (push, 0);
 887    PUSH_DATA (push, 0);
 888    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 889    PUSH_DATA (push, 0x3f);
 890
 891    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 892    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 893    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 894    for (i = 0; i < 8 * 2; ++i)
 895       PUSH_DATA(push, 0);
 896    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 897    PUSH_DATA (push, 0);
 898    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 899    PUSH_DATA (push, 0);
 900
 901    /* neither scissors, viewport nor stencil mask should affect clears */
 902    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 903    PUSH_DATA (push, 0);
 904
 905    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 906    PUSH_DATA (push, 1);
 907    BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
 908    PUSH_DATAf(push, 0.0f);
 909    PUSH_DATAf(push, 1.0f);
 910    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 911    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 912
 913    /* We use scissors instead of exact view volume clipping,
 914     * so they're always enabled.
 915     */
 916    BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
 917    PUSH_DATA (push, 1);
 918    PUSH_DATA (push, 8192 << 16);
 919    PUSH_DATA (push, 8192 << 16);
 920
 921 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 922
 923    i = 0;
 924    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
 925    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
 926    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 927    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
 928    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
 929    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 930    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 931
 932    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
 933    PUSH_DATA (push, 1);
 934    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
 935    PUSH_DATA (push, 1);
 936    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 937    PUSH_DATA (push, 0x40);
 938    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
 939    PUSH_DATA (push, 0);
 940    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 941    PUSH_DATA (push, 0x30);
 942    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
 943    PUSH_DATA (push, 3);
 944    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
 945    PUSH_DATA (push, 0x20);
 946    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
 947    PUSH_DATA (push, 0x00);
 948
 949    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
 950    PUSH_DATA (push, 0);
 951    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
 952    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
 953
 954    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
 955
 956    if (nvc0_screen_init_compute(screen))
 957       goto fail;
 958
 959    PUSH_KICK (push);
 960
 961    screen->tic.entries = CALLOC(4096, sizeof(void *));
 962    screen->tsc.entries = screen->tic.entries + 2048;
 963
 964    mm_config.nvc0.tile_mode = 0;
 965    mm_config.nvc0.memtype = 0xfe0;
 966    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
 967
 968    if (!nvc0_blitter_create(screen))
 969       goto fail;
 970
 971    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 972
 973    return pscreen;
 974
 975 fail:
 976    nvc0_screen_destroy(pscreen);
 977    return NULL;
 978 }
 979
 980 int
 981 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 982 {
 983    int i = screen->tic.next;
 984
 985    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 986       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 987
 988    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 989
 990    if (screen->tic.entries[i])
 991       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 992
 993    screen->tic.entries[i] = entry;
 994    return i;
 995 }
 996
 997 int
 998 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 999 {
1000    int i = screen->tsc.next;
1001
1002    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1003       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1004
1005    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1006
1007    if (screen->tsc.entries[i])
1008       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1009
1010    screen->tsc.entries[i] = entry;
1011    return i;
1012 }