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gm107/ir: don't do indirect frag shader inputs on GM107
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 if (sample_count > 8)
48 return false;
49 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
50 return false;
51
52 if (!util_format_is_supported(format, bindings))
53 return false;
54
55 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
56 if (util_format_get_blocksizebits(format) == 3 * 32)
57 return false;
58
59 /* transfers & shared are always supported */
60 bindings &= ~(PIPE_BIND_TRANSFER_READ |
61 PIPE_BIND_TRANSFER_WRITE |
62 PIPE_BIND_SHARED);
63
64 return (nvc0_format_table[format].usage & bindings) == bindings;
65 }
66
67 static int
68 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
69 {
70 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
71 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
72
73 switch (param) {
74 /* non-boolean caps */
75 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
76 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
77 return 15;
78 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
79 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
80 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
81 return 2048;
82 case PIPE_CAP_MIN_TEXEL_OFFSET:
83 return -8;
84 case PIPE_CAP_MAX_TEXEL_OFFSET:
85 return 7;
86 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
87 return -32;
88 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
89 return 31;
90 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
91 return 128 * 1024 * 1024;
92 case PIPE_CAP_GLSL_FEATURE_LEVEL:
93 return 410;
94 case PIPE_CAP_MAX_RENDER_TARGETS:
95 return 8;
96 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
97 return 1;
98 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
99 return 4;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
101 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
102 return 128;
103 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
104 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
105 return 1024;
106 case PIPE_CAP_MAX_VERTEX_STREAMS:
107 return 4;
108 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
109 return 2048;
110 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
111 return 256;
112 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
113 return 1; /* 256 for binding as RT, but that's not possible in GL */
114 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
115 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
116 case PIPE_CAP_MAX_VIEWPORTS:
117 return NVC0_MAX_VIEWPORTS;
118 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
119 return 4;
120 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
121 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
122 case PIPE_CAP_ENDIANNESS:
123 return PIPE_ENDIAN_LITTLE;
124 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
125 return 30;
126
127 /* supported caps */
128 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
129 case PIPE_CAP_TEXTURE_SWIZZLE:
130 case PIPE_CAP_TEXTURE_SHADOW_MAP:
131 case PIPE_CAP_NPOT_TEXTURES:
132 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
133 case PIPE_CAP_ANISOTROPIC_FILTER:
134 case PIPE_CAP_SEAMLESS_CUBE_MAP:
135 case PIPE_CAP_CUBE_MAP_ARRAY:
136 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
137 case PIPE_CAP_TEXTURE_MULTISAMPLE:
138 case PIPE_CAP_TWO_SIDED_STENCIL:
139 case PIPE_CAP_DEPTH_CLIP_DISABLE:
140 case PIPE_CAP_POINT_SPRITE:
141 case PIPE_CAP_TGSI_TEXCOORD:
142 case PIPE_CAP_SM3:
143 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
144 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
145 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
146 case PIPE_CAP_QUERY_TIMESTAMP:
147 case PIPE_CAP_QUERY_TIME_ELAPSED:
148 case PIPE_CAP_OCCLUSION_QUERY:
149 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
150 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
151 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
152 case PIPE_CAP_INDEP_BLEND_ENABLE:
153 case PIPE_CAP_INDEP_BLEND_FUNC:
154 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
155 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
156 case PIPE_CAP_PRIMITIVE_RESTART:
157 case PIPE_CAP_TGSI_INSTANCEID:
158 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
159 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
160 case PIPE_CAP_CONDITIONAL_RENDER:
161 case PIPE_CAP_TEXTURE_BARRIER:
162 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
163 case PIPE_CAP_START_INSTANCE:
164 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
165 case PIPE_CAP_DRAW_INDIRECT:
166 case PIPE_CAP_USER_CONSTANT_BUFFERS:
167 case PIPE_CAP_USER_INDEX_BUFFERS:
168 case PIPE_CAP_USER_VERTEX_BUFFERS:
169 case PIPE_CAP_TEXTURE_QUERY_LOD:
170 case PIPE_CAP_SAMPLE_SHADING:
171 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
172 case PIPE_CAP_TEXTURE_GATHER_SM5:
173 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
174 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
175 case PIPE_CAP_SAMPLER_VIEW_TARGET:
176 case PIPE_CAP_CLIP_HALFZ:
177 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
178 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
179 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
180 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
181 case PIPE_CAP_DEPTH_BOUNDS_TEST:
182 case PIPE_CAP_TGSI_TXQS:
183 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
184 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
185 case PIPE_CAP_SHAREABLE_SHADERS:
186 case PIPE_CAP_CLEAR_TEXTURE:
187 case PIPE_CAP_DRAW_PARAMETERS:
188 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
189 case PIPE_CAP_MULTI_DRAW_INDIRECT:
190 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
191 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
192 return 1;
193 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
194 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
195 case PIPE_CAP_COMPUTE:
196 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
197 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
198 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
199
200 /* unsupported caps */
201 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
202 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
203 case PIPE_CAP_SHADER_STENCIL_EXPORT:
204 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
205 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
206 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
207 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
208 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
209 case PIPE_CAP_FAKE_SW_MSAA:
210 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
211 case PIPE_CAP_VERTEXID_NOBASE:
212 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
213 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
214 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
215 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
216 case PIPE_CAP_INVALIDATE_BUFFER:
217 case PIPE_CAP_GENERATE_MIPMAP:
218 return 0;
219
220 case PIPE_CAP_VENDOR_ID:
221 return 0x10de;
222 case PIPE_CAP_DEVICE_ID: {
223 uint64_t device_id;
224 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
225 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
226 return -1;
227 }
228 return device_id;
229 }
230 case PIPE_CAP_ACCELERATED:
231 return 1;
232 case PIPE_CAP_VIDEO_MEMORY:
233 return dev->vram_size >> 20;
234 case PIPE_CAP_UMA:
235 return 0;
236 }
237
238 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
239 return 0;
240 }
241
242 static int
243 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
244 enum pipe_shader_cap param)
245 {
246 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
247
248 switch (shader) {
249 case PIPE_SHADER_VERTEX:
250 case PIPE_SHADER_GEOMETRY:
251 case PIPE_SHADER_FRAGMENT:
252 break;
253 case PIPE_SHADER_TESS_CTRL:
254 case PIPE_SHADER_TESS_EVAL:
255 if (class_3d >= GM107_3D_CLASS)
256 return 0;
257 break;
258 case PIPE_SHADER_COMPUTE:
259 if (class_3d > NVE4_3D_CLASS)
260 return 0;
261 break;
262 default:
263 return 0;
264 }
265
266 switch (param) {
267 case PIPE_SHADER_CAP_PREFERRED_IR:
268 return PIPE_SHADER_IR_TGSI;
269 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
270 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
271 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
272 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
273 return 16384;
274 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
275 return 16;
276 case PIPE_SHADER_CAP_MAX_INPUTS:
277 if (shader == PIPE_SHADER_VERTEX)
278 return 32;
279 /* NOTE: These only count our slots for GENERIC varyings.
280 * The address space may be larger, but the actual hard limit seems to be
281 * less than what the address space layout permits, so don't add TEXCOORD,
282 * COLOR, etc. here.
283 */
284 if (shader == PIPE_SHADER_FRAGMENT)
285 return 0x1f0 / 16;
286 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
287 * and excludes 0x60 per-patch inputs.
288 */
289 return 0x200 / 16;
290 case PIPE_SHADER_CAP_MAX_OUTPUTS:
291 return 32;
292 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
293 return 65536;
294 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
295 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
296 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
297 return NVC0_MAX_PIPE_CONSTBUFS;
298 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
299 return shader != PIPE_SHADER_FRAGMENT;
300 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
301 return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
302 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
303 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
304 return 1;
305 case PIPE_SHADER_CAP_MAX_PREDS:
306 return 0;
307 case PIPE_SHADER_CAP_MAX_TEMPS:
308 return NVC0_CAP_MAX_PROGRAM_TEMPS;
309 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
310 return 1;
311 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
312 return 0;
313 case PIPE_SHADER_CAP_SUBROUTINES:
314 return 1;
315 case PIPE_SHADER_CAP_INTEGERS:
316 return 1;
317 case PIPE_SHADER_CAP_DOUBLES:
318 return 1;
319 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
320 return 1;
321 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
322 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
323 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
324 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
325 return 0;
326 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
327 return 16; /* would be 32 in linked (OpenGL-style) mode */
328 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
329 return 16; /* XXX not sure if more are really safe */
330 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
331 return 32;
332 default:
333 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
334 return 0;
335 }
336 }
337
338 static float
339 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
340 {
341 switch (param) {
342 case PIPE_CAPF_MAX_LINE_WIDTH:
343 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
344 return 10.0f;
345 case PIPE_CAPF_MAX_POINT_WIDTH:
346 return 63.0f;
347 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
348 return 63.375f;
349 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
350 return 16.0f;
351 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
352 return 15.0f;
353 case PIPE_CAPF_GUARD_BAND_LEFT:
354 case PIPE_CAPF_GUARD_BAND_TOP:
355 return 0.0f;
356 case PIPE_CAPF_GUARD_BAND_RIGHT:
357 case PIPE_CAPF_GUARD_BAND_BOTTOM:
358 return 0.0f; /* that or infinity */
359 }
360
361 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
362 return 0.0f;
363 }
364
365 static int
366 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
367 enum pipe_compute_cap param, void *data)
368 {
369 struct nvc0_screen *screen = nvc0_screen(pscreen);
370 const uint16_t obj_class = screen->compute->oclass;
371
372 #define RET(x) do { \
373 if (data) \
374 memcpy(data, x, sizeof(x)); \
375 return sizeof(x); \
376 } while (0)
377
378 switch (param) {
379 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
380 RET((uint64_t []) { 3 });
381 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
382 if (obj_class >= NVE4_COMPUTE_CLASS) {
383 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
384 } else {
385 RET(((uint64_t []) { 65535, 65535, 65535 }));
386 }
387 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
388 RET(((uint64_t []) { 1024, 1024, 64 }));
389 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
390 RET((uint64_t []) { 1024 });
391 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
392 RET((uint64_t []) { 1ULL << 40 });
393 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
394 RET((uint64_t []) { 48 << 10 });
395 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
396 RET((uint64_t []) { 512 << 10 });
397 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
398 RET((uint64_t []) { 4096 });
399 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
400 RET((uint32_t []) { 32 });
401 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
402 RET((uint64_t []) { 1ULL << 40 });
403 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
404 RET((uint32_t []) { 0 });
405 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
406 RET((uint32_t []) { screen->mp_count_compute });
407 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
408 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
409 default:
410 return 0;
411 }
412
413 #undef RET
414 }
415
416 static void
417 nvc0_screen_destroy(struct pipe_screen *pscreen)
418 {
419 struct nvc0_screen *screen = nvc0_screen(pscreen);
420
421 if (!nouveau_drm_screen_unref(&screen->base))
422 return;
423
424 if (screen->base.fence.current) {
425 struct nouveau_fence *current = NULL;
426
427 /* nouveau_fence_wait will create a new current fence, so wait on the
428 * _current_ one, and remove both.
429 */
430 nouveau_fence_ref(screen->base.fence.current, &current);
431 nouveau_fence_wait(current, NULL);
432 nouveau_fence_ref(NULL, &current);
433 nouveau_fence_ref(NULL, &screen->base.fence.current);
434 }
435 if (screen->base.pushbuf)
436 screen->base.pushbuf->user_priv = NULL;
437
438 if (screen->blitter)
439 nvc0_blitter_destroy(screen);
440 if (screen->pm.prog) {
441 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
442 nvc0_program_destroy(NULL, screen->pm.prog);
443 FREE(screen->pm.prog);
444 }
445
446 nouveau_bo_ref(NULL, &screen->text);
447 nouveau_bo_ref(NULL, &screen->uniform_bo);
448 nouveau_bo_ref(NULL, &screen->tls);
449 nouveau_bo_ref(NULL, &screen->txc);
450 nouveau_bo_ref(NULL, &screen->fence.bo);
451 nouveau_bo_ref(NULL, &screen->poly_cache);
452 nouveau_bo_ref(NULL, &screen->parm);
453
454 nouveau_heap_destroy(&screen->lib_code);
455 nouveau_heap_destroy(&screen->text_heap);
456
457 FREE(screen->tic.entries);
458
459 nouveau_object_del(&screen->eng3d);
460 nouveau_object_del(&screen->eng2d);
461 nouveau_object_del(&screen->m2mf);
462 nouveau_object_del(&screen->compute);
463 nouveau_object_del(&screen->nvsw);
464
465 nouveau_screen_fini(&screen->base);
466
467 FREE(screen);
468 }
469
470 static int
471 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
472 unsigned size, const uint32_t *data)
473 {
474 struct nouveau_pushbuf *push = screen->base.pushbuf;
475
476 size /= 4;
477
478 assert((pos + size) <= 0x800);
479
480 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
481 PUSH_DATA (push, (m - 0x3800) / 8);
482 PUSH_DATA (push, pos);
483 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
484 PUSH_DATA (push, pos);
485 PUSH_DATAp(push, data, size);
486
487 return pos + size;
488 }
489
490 static void
491 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
492 {
493 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
494 PUSH_DATA (push, 0xff);
495 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
496 PUSH_DATA (push, 0xff);
497 PUSH_DATA (push, 0xff);
498 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
499 PUSH_DATA (push, 0xff);
500 PUSH_DATA (push, 0xff);
501 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
502 PUSH_DATA (push, 0x3f);
503
504 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
505 PUSH_DATA (push, (3 << 16) | 3);
506 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
507 PUSH_DATA (push, (2 << 16) | 2);
508
509 if (obj_class < GM107_3D_CLASS) {
510 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
511 PUSH_DATA (push, 0);
512 }
513 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
514 PUSH_DATA (push, 0x10);
515 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
516 PUSH_DATA (push, 0x10);
517 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
518 PUSH_DATA (push, 0x10);
519 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
520 PUSH_DATA (push, 0x10);
521 PUSH_DATA (push, 0x10);
522 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
523 PUSH_DATA (push, 0x10);
524 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
525 PUSH_DATA (push, 0xe);
526
527 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
528 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
529 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
530 PUSH_DATA (push, 0);
531 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
532 PUSH_DATA (push, 3);
533
534 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
535 PUSH_DATA (push, 0x3fffff);
536 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
537 PUSH_DATA (push, 1);
538 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
539 PUSH_DATA (push, 1);
540
541 if (obj_class < GM107_3D_CLASS) {
542 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
543 PUSH_DATA (push, 3);
544
545 if (obj_class >= NVE4_3D_CLASS) {
546 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
547 PUSH_DATA (push, 1);
548 }
549 }
550
551 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
552 * are supposed to do */
553 }
554
555 static void
556 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
557 {
558 struct nvc0_screen *screen = nvc0_screen(pscreen);
559 struct nouveau_pushbuf *push = screen->base.pushbuf;
560
561 /* we need to do it after possible flush in MARK_RING */
562 *sequence = ++screen->base.fence.sequence;
563
564 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
565 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
566 PUSH_DATAh(push, screen->fence.bo->offset);
567 PUSH_DATA (push, screen->fence.bo->offset);
568 PUSH_DATA (push, *sequence);
569 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
570 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
571 }
572
573 static u32
574 nvc0_screen_fence_update(struct pipe_screen *pscreen)
575 {
576 struct nvc0_screen *screen = nvc0_screen(pscreen);
577 return screen->fence.map[0];
578 }
579
580 static int
581 nvc0_screen_init_compute(struct nvc0_screen *screen)
582 {
583 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
584
585 switch (screen->base.device->chipset & ~0xf) {
586 case 0xc0:
587 case 0xd0:
588 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
589 case 0xe0:
590 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
591 case 0xf0:
592 case 0x100:
593 case 0x110:
594 return 0;
595 default:
596 return -1;
597 }
598 }
599
600 bool
601 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
602 uint32_t lpos, uint32_t lneg, uint32_t cstack)
603 {
604 struct nouveau_bo *bo = NULL;
605 int ret;
606 uint64_t size = (lpos + lneg) * 32 + cstack;
607
608 if (size >= (1 << 20)) {
609 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
610 return false;
611 }
612
613 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
614 size = align(size, 0x8000);
615 size *= screen->mp_count;
616
617 size = align(size, 1 << 17);
618
619 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
620 NULL, &bo);
621 if (ret) {
622 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
623 return false;
624 }
625 nouveau_bo_ref(NULL, &screen->tls);
626 screen->tls = bo;
627 return true;
628 }
629
630 #define FAIL_SCREEN_INIT(str, err) \
631 do { \
632 NOUVEAU_ERR(str, err); \
633 goto fail; \
634 } while(0)
635
636 struct nouveau_screen *
637 nvc0_screen_create(struct nouveau_device *dev)
638 {
639 struct nvc0_screen *screen;
640 struct pipe_screen *pscreen;
641 struct nouveau_object *chan;
642 struct nouveau_pushbuf *push;
643 uint64_t value;
644 uint32_t obj_class;
645 uint32_t flags;
646 int ret;
647 unsigned i;
648
649 switch (dev->chipset & ~0xf) {
650 case 0xc0:
651 case 0xd0:
652 case 0xe0:
653 case 0xf0:
654 case 0x100:
655 case 0x110:
656 break;
657 default:
658 return NULL;
659 }
660
661 screen = CALLOC_STRUCT(nvc0_screen);
662 if (!screen)
663 return NULL;
664 pscreen = &screen->base.base;
665 pscreen->destroy = nvc0_screen_destroy;
666
667 ret = nouveau_screen_init(&screen->base, dev);
668 if (ret) {
669 nvc0_screen_destroy(pscreen);
670 return NULL;
671 }
672 chan = screen->base.channel;
673 push = screen->base.pushbuf;
674 push->user_priv = screen;
675 push->rsvd_kick = 5;
676
677 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
678 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
679 PIPE_BIND_COMMAND_ARGS_BUFFER;
680 screen->base.sysmem_bindings |=
681 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
682
683 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
684 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
685 screen->base.vidmem_bindings = 0;
686 }
687
688 pscreen->context_create = nvc0_create;
689 pscreen->is_format_supported = nvc0_screen_is_format_supported;
690 pscreen->get_param = nvc0_screen_get_param;
691 pscreen->get_shader_param = nvc0_screen_get_shader_param;
692 pscreen->get_paramf = nvc0_screen_get_paramf;
693 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
694 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
695
696 nvc0_screen_init_resource_functions(pscreen);
697
698 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
699 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
700
701 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
702 if (screen->base.drm->version >= 0x01000202)
703 flags |= NOUVEAU_BO_COHERENT;
704
705 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
706 if (ret)
707 goto fail;
708 nouveau_bo_map(screen->fence.bo, 0, NULL);
709 screen->fence.map = screen->fence.bo->map;
710 screen->base.fence.emit = nvc0_screen_fence_emit;
711 screen->base.fence.update = nvc0_screen_fence_update;
712
713
714 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
715 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
716 if (ret)
717 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
718
719 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
720 PUSH_DATA (push, screen->nvsw->handle);
721
722 switch (dev->chipset & ~0xf) {
723 case 0x110:
724 case 0x100:
725 case 0xf0:
726 obj_class = NVF0_P2MF_CLASS;
727 break;
728 case 0xe0:
729 obj_class = NVE4_P2MF_CLASS;
730 break;
731 default:
732 obj_class = NVC0_M2MF_CLASS;
733 break;
734 }
735 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
736 &screen->m2mf);
737 if (ret)
738 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
739
740 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
741 PUSH_DATA (push, screen->m2mf->oclass);
742 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
743 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
744 PUSH_DATA (push, 0xa0b5);
745 }
746
747 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
748 &screen->eng2d);
749 if (ret)
750 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
751
752 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
753 PUSH_DATA (push, screen->eng2d->oclass);
754 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
755 PUSH_DATA (push, 0);
756 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
757 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
758 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
759 PUSH_DATA (push, 0);
760 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
761 PUSH_DATA (push, 0);
762 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
763 PUSH_DATA (push, 0x3f);
764 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
765 PUSH_DATA (push, 1);
766 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
767 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
768
769 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
770 PUSH_DATAh(push, screen->fence.bo->offset + 16);
771 PUSH_DATA (push, screen->fence.bo->offset + 16);
772
773 switch (dev->chipset & ~0xf) {
774 case 0x110:
775 obj_class = GM107_3D_CLASS;
776 break;
777 case 0x100:
778 case 0xf0:
779 obj_class = NVF0_3D_CLASS;
780 break;
781 case 0xe0:
782 switch (dev->chipset) {
783 case 0xea:
784 obj_class = NVEA_3D_CLASS;
785 break;
786 default:
787 obj_class = NVE4_3D_CLASS;
788 break;
789 }
790 break;
791 case 0xd0:
792 obj_class = NVC8_3D_CLASS;
793 break;
794 case 0xc0:
795 default:
796 switch (dev->chipset) {
797 case 0xc8:
798 obj_class = NVC8_3D_CLASS;
799 break;
800 case 0xc1:
801 obj_class = NVC1_3D_CLASS;
802 break;
803 default:
804 obj_class = NVC0_3D_CLASS;
805 break;
806 }
807 break;
808 }
809 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
810 &screen->eng3d);
811 if (ret)
812 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
813 screen->base.class_3d = obj_class;
814
815 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
816 PUSH_DATA (push, screen->eng3d->oclass);
817
818 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
819 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
820
821 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
822 /* kill shaders after about 1 second (at 100 MHz) */
823 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
824 PUSH_DATA (push, 0x17);
825 }
826
827 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
828 screen->base.drm->version >= 0x01000101);
829 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
830 for (i = 0; i < 8; ++i)
831 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
832
833 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
834 PUSH_DATA (push, 1);
835
836 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
837 PUSH_DATA (push, 0);
838 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
839 PUSH_DATA (push, 0);
840 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
841 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
842 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
843 PUSH_DATA (push, 0);
844 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
845 PUSH_DATA (push, 1);
846 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
847 PUSH_DATA (push, 1);
848 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
849 PUSH_DATA (push, 1);
850 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
851 PUSH_DATA (push, 0);
852 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
853 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
854 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
855 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
856 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
857 } else {
858 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
859 PUSH_DATA (push, 15);
860 }
861 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
862 PUSH_DATA (push, 8); /* 128 */
863 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
864 PUSH_DATA (push, 1);
865 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
866 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
867 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
868 }
869
870 nvc0_magic_3d_init(push, screen->eng3d->oclass);
871
872 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
873 &screen->text);
874 if (ret)
875 goto fail;
876
877 /* XXX: getting a page fault at the end of the code buffer every few
878 * launches, don't use the last 256 bytes to work around them - prefetch ?
879 */
880 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
881
882 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
883 &screen->uniform_bo);
884 if (ret)
885 goto fail;
886
887 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
888
889 for (i = 0; i < 5; ++i) {
890 /* TIC and TSC entries for each unit (nve4+ only) */
891 /* auxiliary constants (6 user clip planes, base instance id) */
892 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
893 PUSH_DATA (push, 512);
894 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
895 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
896 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
897 PUSH_DATA (push, (15 << 4) | 1);
898 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
899 unsigned j;
900 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
901 PUSH_DATA (push, 0);
902 for (j = 0; j < 8; ++j)
903 PUSH_DATA(push, j);
904 } else {
905 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
906 PUSH_DATA (push, 0x54);
907 }
908 }
909 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
910 PUSH_DATA (push, 0);
911
912 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
913 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
914 PUSH_DATA (push, 256);
915 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
916 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
917 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
918 PUSH_DATA (push, 0);
919 PUSH_DATAf(push, 0.0f);
920 PUSH_DATAf(push, 0.0f);
921 PUSH_DATAf(push, 0.0f);
922 PUSH_DATAf(push, 0.0f);
923 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
924 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
925 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
926
927 if (screen->base.drm->version >= 0x01000101) {
928 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
929 if (ret) {
930 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
931 goto fail;
932 }
933 } else {
934 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
935 value = (8 << 8) | 4;
936 else
937 value = (16 << 8) | 4;
938 }
939 screen->gpc_count = value & 0x000000ff;
940 screen->mp_count = value >> 8;
941 screen->mp_count_compute = screen->mp_count;
942
943 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
944
945 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
946 PUSH_DATAh(push, screen->text->offset);
947 PUSH_DATA (push, screen->text->offset);
948 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
949 PUSH_DATAh(push, screen->tls->offset);
950 PUSH_DATA (push, screen->tls->offset);
951 PUSH_DATA (push, screen->tls->size >> 32);
952 PUSH_DATA (push, screen->tls->size);
953 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
954 PUSH_DATA (push, 0);
955 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
956 PUSH_DATA (push, 0);
957
958 if (screen->eng3d->oclass < GM107_3D_CLASS) {
959 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
960 &screen->poly_cache);
961 if (ret)
962 goto fail;
963
964 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
965 PUSH_DATAh(push, screen->poly_cache->offset);
966 PUSH_DATA (push, screen->poly_cache->offset);
967 PUSH_DATA (push, 3);
968 }
969
970 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
971 &screen->txc);
972 if (ret)
973 goto fail;
974
975 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
976 PUSH_DATAh(push, screen->txc->offset);
977 PUSH_DATA (push, screen->txc->offset);
978 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
979
980 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
981 PUSH_DATAh(push, screen->txc->offset + 65536);
982 PUSH_DATA (push, screen->txc->offset + 65536);
983 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
984
985 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
986 PUSH_DATA (push, 0);
987 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
988 PUSH_DATA (push, 0);
989 PUSH_DATA (push, 0);
990 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
991 PUSH_DATA (push, 0x3f);
992
993 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
994 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
995 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
996 for (i = 0; i < 8 * 2; ++i)
997 PUSH_DATA(push, 0);
998 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
999 PUSH_DATA (push, 0);
1000 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1001 PUSH_DATA (push, 0);
1002
1003 /* neither scissors, viewport nor stencil mask should affect clears */
1004 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1005 PUSH_DATA (push, 0);
1006
1007 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1008 PUSH_DATA (push, 1);
1009 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1010 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1011 PUSH_DATAf(push, 0.0f);
1012 PUSH_DATAf(push, 1.0f);
1013 }
1014 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1015 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1016
1017 /* We use scissors instead of exact view volume clipping,
1018 * so they're always enabled.
1019 */
1020 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1021 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1022 PUSH_DATA (push, 1);
1023 PUSH_DATA (push, 8192 << 16);
1024 PUSH_DATA (push, 8192 << 16);
1025 }
1026
1027 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1028
1029 i = 0;
1030 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1031 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1032 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1033 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1034 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1035 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1036 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1037 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1038 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1039 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1040 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1041
1042 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1043 PUSH_DATA (push, 1);
1044 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1045 PUSH_DATA (push, 1);
1046 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1047 PUSH_DATA (push, 0x40);
1048 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1049 PUSH_DATA (push, 0);
1050 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1051 PUSH_DATA (push, 0x30);
1052 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1053 PUSH_DATA (push, 3);
1054 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1055 PUSH_DATA (push, 0x20);
1056 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1057 PUSH_DATA (push, 0x00);
1058 screen->save_state.patch_vertices = 3;
1059
1060 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1061 PUSH_DATA (push, 0);
1062 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1063 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1064
1065 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1066
1067 if (nvc0_screen_init_compute(screen))
1068 goto fail;
1069
1070 PUSH_KICK (push);
1071
1072 screen->tic.entries = CALLOC(4096, sizeof(void *));
1073 screen->tsc.entries = screen->tic.entries + 2048;
1074
1075 if (!nvc0_blitter_create(screen))
1076 goto fail;
1077
1078 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1079
1080 return &screen->base;
1081
1082 fail:
1083 screen->base.base.context_create = NULL;
1084 return &screen->base;
1085 }
1086
1087 int
1088 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1089 {
1090 int i = screen->tic.next;
1091
1092 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1093 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1094
1095 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1096
1097 if (screen->tic.entries[i])
1098 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1099
1100 screen->tic.entries[i] = entry;
1101 return i;
1102 }
1103
1104 int
1105 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1106 {
1107 int i = screen->tsc.next;
1108
1109 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1110 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1111
1112 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1113
1114 if (screen->tsc.entries[i])
1115 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1116
1117 screen->tsc.entries[i] = entry;
1118 return i;
1119 }