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gallium: introduce PIPE_CAP_MEMOBJ
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/mme/com9097.mme.h"
36 #include "nvc0/mme/com90c0.mme.h"
37
38 #include "nv50/g80_texture.xml.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 const struct util_format_description *desc = util_format_description(format);
48
49 if (sample_count > 8)
50 return false;
51 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
52 return false;
53
54 /* Short-circuit the rest of the logic -- this is used by the state tracker
55 * to determine valid MS levels in a no-attachments scenario.
56 */
57 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
58 return true;
59
60 if (!util_format_is_supported(format, bindings))
61 return false;
62
63 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
64 if (util_format_get_blocksizebits(format) == 3 * 32)
65 return false;
66
67 if (bindings & PIPE_BIND_LINEAR)
68 if (util_format_is_depth_or_stencil(format) ||
69 (target != PIPE_TEXTURE_1D &&
70 target != PIPE_TEXTURE_2D &&
71 target != PIPE_TEXTURE_RECT) ||
72 sample_count > 1)
73 return false;
74
75 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
76 */
77 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
78 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
79 /* The claim is that this should work on GM107 but it doesn't. Need to
80 * test further and figure out if it's a nouveau issue or a HW one.
81 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
82 */
83 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
84 return false;
85
86 /* shared is always supported */
87 bindings &= ~(PIPE_BIND_LINEAR |
88 PIPE_BIND_SHARED);
89
90 if (bindings & PIPE_BIND_SHADER_IMAGE) {
91 if (sample_count > 1 &&
92 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
93 /* MS images are currently unsupported on Maxwell because they have to
94 * be handled explicitly. */
95 return false;
96 }
97
98 if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
99 nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
100 /* This should work on Fermi, but for currently unknown reasons it
101 * does not and results in breaking reads from pbos. */
102 return false;
103 }
104 }
105
106 return (( nvc0_format_table[format].usage |
107 nvc0_vertex_format[format].usage) & bindings) == bindings;
108 }
109
110 static int
111 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
112 {
113 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
114 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
115
116 switch (param) {
117 /* non-boolean caps */
118 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
119 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
120 return 15;
121 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
122 return 12;
123 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
124 return 2048;
125 case PIPE_CAP_MIN_TEXEL_OFFSET:
126 return -8;
127 case PIPE_CAP_MAX_TEXEL_OFFSET:
128 return 7;
129 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
130 return -32;
131 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
132 return 31;
133 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
134 return 128 * 1024 * 1024;
135 case PIPE_CAP_GLSL_FEATURE_LEVEL:
136 return 430;
137 case PIPE_CAP_MAX_RENDER_TARGETS:
138 return 8;
139 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
140 return 1;
141 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
142 return 4;
143 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
144 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
145 return 128;
146 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
147 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
148 return 1024;
149 case PIPE_CAP_MAX_VERTEX_STREAMS:
150 return 4;
151 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
152 return 2048;
153 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
154 return 256;
155 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
156 if (class_3d < GM107_3D_CLASS)
157 return 256; /* IMAGE bindings require alignment to 256 */
158 return 16;
159 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
160 return 16;
161 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
162 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
163 case PIPE_CAP_MAX_VIEWPORTS:
164 return NVC0_MAX_VIEWPORTS;
165 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
166 return 4;
167 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
168 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
169 case PIPE_CAP_ENDIANNESS:
170 return PIPE_ENDIAN_LITTLE;
171 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
172 return 30;
173 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
174 return NVC0_MAX_WINDOW_RECTANGLES;
175
176 /* supported caps */
177 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
178 case PIPE_CAP_TEXTURE_SWIZZLE:
179 case PIPE_CAP_TEXTURE_SHADOW_MAP:
180 case PIPE_CAP_NPOT_TEXTURES:
181 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
182 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
183 case PIPE_CAP_ANISOTROPIC_FILTER:
184 case PIPE_CAP_SEAMLESS_CUBE_MAP:
185 case PIPE_CAP_CUBE_MAP_ARRAY:
186 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
187 case PIPE_CAP_TEXTURE_MULTISAMPLE:
188 case PIPE_CAP_TWO_SIDED_STENCIL:
189 case PIPE_CAP_DEPTH_CLIP_DISABLE:
190 case PIPE_CAP_POINT_SPRITE:
191 case PIPE_CAP_TGSI_TEXCOORD:
192 case PIPE_CAP_SM3:
193 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
194 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
195 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
196 case PIPE_CAP_QUERY_TIMESTAMP:
197 case PIPE_CAP_QUERY_TIME_ELAPSED:
198 case PIPE_CAP_OCCLUSION_QUERY:
199 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
200 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
201 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
202 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
203 case PIPE_CAP_INDEP_BLEND_ENABLE:
204 case PIPE_CAP_INDEP_BLEND_FUNC:
205 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
206 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
207 case PIPE_CAP_PRIMITIVE_RESTART:
208 case PIPE_CAP_TGSI_INSTANCEID:
209 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
210 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
211 case PIPE_CAP_CONDITIONAL_RENDER:
212 case PIPE_CAP_TEXTURE_BARRIER:
213 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
214 case PIPE_CAP_START_INSTANCE:
215 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
216 case PIPE_CAP_DRAW_INDIRECT:
217 case PIPE_CAP_USER_CONSTANT_BUFFERS:
218 case PIPE_CAP_USER_VERTEX_BUFFERS:
219 case PIPE_CAP_TEXTURE_QUERY_LOD:
220 case PIPE_CAP_SAMPLE_SHADING:
221 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
222 case PIPE_CAP_TEXTURE_GATHER_SM5:
223 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
224 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
225 case PIPE_CAP_SAMPLER_VIEW_TARGET:
226 case PIPE_CAP_CLIP_HALFZ:
227 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
228 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
229 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
230 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
231 case PIPE_CAP_DEPTH_BOUNDS_TEST:
232 case PIPE_CAP_TGSI_TXQS:
233 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
234 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
235 case PIPE_CAP_SHAREABLE_SHADERS:
236 case PIPE_CAP_CLEAR_TEXTURE:
237 case PIPE_CAP_DRAW_PARAMETERS:
238 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
239 case PIPE_CAP_MULTI_DRAW_INDIRECT:
240 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
241 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
242 case PIPE_CAP_QUERY_BUFFER_OBJECT:
243 case PIPE_CAP_INVALIDATE_BUFFER:
244 case PIPE_CAP_STRING_MARKER:
245 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
246 case PIPE_CAP_CULL_DISTANCE:
247 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
248 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
249 case PIPE_CAP_TGSI_VOTE:
250 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
251 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
252 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
253 case PIPE_CAP_DOUBLES:
254 case PIPE_CAP_INT64:
255 case PIPE_CAP_TGSI_TEX_TXF_LZ:
256 case PIPE_CAP_TGSI_CLOCK:
257 case PIPE_CAP_COMPUTE:
258 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
259 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
260 return 1;
261 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
262 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
263 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
264 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
265 case PIPE_CAP_TGSI_FS_FBFETCH:
266 return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
267 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
268 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
269 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
270 case PIPE_CAP_POST_DEPTH_COVERAGE:
271 return class_3d >= GM200_3D_CLASS;
272 case PIPE_CAP_TGSI_BALLOT:
273 return class_3d >= NVE4_3D_CLASS;
274
275 /* unsupported caps */
276 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
277 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
278 case PIPE_CAP_SHADER_STENCIL_EXPORT:
279 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
280 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
281 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
282 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
283 case PIPE_CAP_FAKE_SW_MSAA:
284 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
285 case PIPE_CAP_VERTEXID_NOBASE:
286 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
287 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
288 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
289 case PIPE_CAP_GENERATE_MIPMAP:
290 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
291 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
292 case PIPE_CAP_QUERY_MEMORY_INFO:
293 case PIPE_CAP_PCI_GROUP:
294 case PIPE_CAP_PCI_BUS:
295 case PIPE_CAP_PCI_DEVICE:
296 case PIPE_CAP_PCI_FUNCTION:
297 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
298 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
299 case PIPE_CAP_NATIVE_FENCE_FD:
300 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
301 case PIPE_CAP_INT64_DIVMOD:
302 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
303 case PIPE_CAP_BINDLESS_TEXTURE:
304 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
305 case PIPE_CAP_QUERY_SO_OVERFLOW:
306 case PIPE_CAP_MEMOBJ:
307 return 0;
308
309 case PIPE_CAP_VENDOR_ID:
310 return 0x10de;
311 case PIPE_CAP_DEVICE_ID: {
312 uint64_t device_id;
313 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
314 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
315 return -1;
316 }
317 return device_id;
318 }
319 case PIPE_CAP_ACCELERATED:
320 return 1;
321 case PIPE_CAP_VIDEO_MEMORY:
322 return dev->vram_size >> 20;
323 case PIPE_CAP_UMA:
324 return 0;
325 }
326
327 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
328 return 0;
329 }
330
331 static int
332 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
333 enum pipe_shader_type shader,
334 enum pipe_shader_cap param)
335 {
336 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
337
338 switch (shader) {
339 case PIPE_SHADER_VERTEX:
340 case PIPE_SHADER_GEOMETRY:
341 case PIPE_SHADER_FRAGMENT:
342 case PIPE_SHADER_COMPUTE:
343 case PIPE_SHADER_TESS_CTRL:
344 case PIPE_SHADER_TESS_EVAL:
345 break;
346 default:
347 return 0;
348 }
349
350 switch (param) {
351 case PIPE_SHADER_CAP_PREFERRED_IR:
352 return PIPE_SHADER_IR_TGSI;
353 case PIPE_SHADER_CAP_SUPPORTED_IRS:
354 return 1 << PIPE_SHADER_IR_TGSI;
355 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
356 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
357 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
358 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
359 return 16384;
360 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
361 return 16;
362 case PIPE_SHADER_CAP_MAX_INPUTS:
363 if (shader == PIPE_SHADER_VERTEX)
364 return 32;
365 /* NOTE: These only count our slots for GENERIC varyings.
366 * The address space may be larger, but the actual hard limit seems to be
367 * less than what the address space layout permits, so don't add TEXCOORD,
368 * COLOR, etc. here.
369 */
370 if (shader == PIPE_SHADER_FRAGMENT)
371 return 0x1f0 / 16;
372 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
373 * and excludes 0x60 per-patch inputs.
374 */
375 return 0x200 / 16;
376 case PIPE_SHADER_CAP_MAX_OUTPUTS:
377 return 32;
378 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
379 return 65536;
380 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
381 return NVC0_MAX_PIPE_CONSTBUFS;
382 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
383 return shader != PIPE_SHADER_FRAGMENT;
384 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
385 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
386 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
387 return 1;
388 case PIPE_SHADER_CAP_MAX_TEMPS:
389 return NVC0_CAP_MAX_PROGRAM_TEMPS;
390 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
391 return 1;
392 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
393 return 1;
394 case PIPE_SHADER_CAP_SUBROUTINES:
395 return 1;
396 case PIPE_SHADER_CAP_INTEGERS:
397 return 1;
398 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
399 return 1;
400 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
401 return 1;
402 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
403 return 1;
404 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
405 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
406 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
407 return 0;
408 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
409 return NVC0_MAX_BUFFERS;
410 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
411 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
412 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
413 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
414 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
415 return 32;
416 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
417 if (class_3d >= NVE4_3D_CLASS)
418 return NVC0_MAX_IMAGES;
419 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
420 return NVC0_MAX_IMAGES;
421 return 0;
422 default:
423 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
424 return 0;
425 }
426 }
427
428 static float
429 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
430 {
431 switch (param) {
432 case PIPE_CAPF_MAX_LINE_WIDTH:
433 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
434 return 10.0f;
435 case PIPE_CAPF_MAX_POINT_WIDTH:
436 return 63.0f;
437 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
438 return 63.375f;
439 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
440 return 16.0f;
441 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
442 return 15.0f;
443 case PIPE_CAPF_GUARD_BAND_LEFT:
444 case PIPE_CAPF_GUARD_BAND_TOP:
445 return 0.0f;
446 case PIPE_CAPF_GUARD_BAND_RIGHT:
447 case PIPE_CAPF_GUARD_BAND_BOTTOM:
448 return 0.0f; /* that or infinity */
449 }
450
451 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
452 return 0.0f;
453 }
454
455 static int
456 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
457 enum pipe_shader_ir ir_type,
458 enum pipe_compute_cap param, void *data)
459 {
460 struct nvc0_screen *screen = nvc0_screen(pscreen);
461 const uint16_t obj_class = screen->compute->oclass;
462
463 #define RET(x) do { \
464 if (data) \
465 memcpy(data, x, sizeof(x)); \
466 return sizeof(x); \
467 } while (0)
468
469 switch (param) {
470 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
471 RET((uint64_t []) { 3 });
472 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
473 if (obj_class >= NVE4_COMPUTE_CLASS) {
474 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
475 } else {
476 RET(((uint64_t []) { 65535, 65535, 65535 }));
477 }
478 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
479 RET(((uint64_t []) { 1024, 1024, 64 }));
480 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
481 RET((uint64_t []) { 1024 });
482 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
483 if (obj_class >= NVE4_COMPUTE_CLASS) {
484 RET((uint64_t []) { 1024 });
485 } else {
486 RET((uint64_t []) { 512 });
487 }
488 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
489 RET((uint64_t []) { 1ULL << 40 });
490 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
491 switch (obj_class) {
492 case GM200_COMPUTE_CLASS:
493 RET((uint64_t []) { 96 << 10 });
494 break;
495 case GM107_COMPUTE_CLASS:
496 RET((uint64_t []) { 64 << 10 });
497 break;
498 default:
499 RET((uint64_t []) { 48 << 10 });
500 break;
501 }
502 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
503 RET((uint64_t []) { 512 << 10 });
504 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
505 RET((uint64_t []) { 4096 });
506 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
507 RET((uint32_t []) { 32 });
508 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
509 RET((uint64_t []) { 1ULL << 40 });
510 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
511 RET((uint32_t []) { 0 });
512 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
513 RET((uint32_t []) { screen->mp_count_compute });
514 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
515 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
516 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
517 RET((uint32_t []) { 64 });
518 default:
519 return 0;
520 }
521
522 #undef RET
523 }
524
525 static void
526 nvc0_screen_destroy(struct pipe_screen *pscreen)
527 {
528 struct nvc0_screen *screen = nvc0_screen(pscreen);
529
530 if (!nouveau_drm_screen_unref(&screen->base))
531 return;
532
533 if (screen->base.fence.current) {
534 struct nouveau_fence *current = NULL;
535
536 /* nouveau_fence_wait will create a new current fence, so wait on the
537 * _current_ one, and remove both.
538 */
539 nouveau_fence_ref(screen->base.fence.current, &current);
540 nouveau_fence_wait(current, NULL);
541 nouveau_fence_ref(NULL, &current);
542 nouveau_fence_ref(NULL, &screen->base.fence.current);
543 }
544 if (screen->base.pushbuf)
545 screen->base.pushbuf->user_priv = NULL;
546
547 if (screen->blitter)
548 nvc0_blitter_destroy(screen);
549 if (screen->pm.prog) {
550 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
551 nvc0_program_destroy(NULL, screen->pm.prog);
552 FREE(screen->pm.prog);
553 }
554
555 nouveau_bo_ref(NULL, &screen->text);
556 nouveau_bo_ref(NULL, &screen->uniform_bo);
557 nouveau_bo_ref(NULL, &screen->tls);
558 nouveau_bo_ref(NULL, &screen->txc);
559 nouveau_bo_ref(NULL, &screen->fence.bo);
560 nouveau_bo_ref(NULL, &screen->poly_cache);
561
562 nouveau_heap_destroy(&screen->lib_code);
563 nouveau_heap_destroy(&screen->text_heap);
564
565 FREE(screen->default_tsc);
566 FREE(screen->tic.entries);
567
568 nouveau_object_del(&screen->eng3d);
569 nouveau_object_del(&screen->eng2d);
570 nouveau_object_del(&screen->m2mf);
571 nouveau_object_del(&screen->compute);
572 nouveau_object_del(&screen->nvsw);
573
574 nouveau_screen_fini(&screen->base);
575
576 FREE(screen);
577 }
578
579 static int
580 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
581 unsigned size, const uint32_t *data)
582 {
583 struct nouveau_pushbuf *push = screen->base.pushbuf;
584
585 size /= 4;
586
587 assert((pos + size) <= 0x800);
588
589 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
590 PUSH_DATA (push, (m - 0x3800) / 8);
591 PUSH_DATA (push, pos);
592 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
593 PUSH_DATA (push, pos);
594 PUSH_DATAp(push, data, size);
595
596 return pos + size;
597 }
598
599 static void
600 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
601 {
602 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
603 PUSH_DATA (push, 0xff);
604 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
605 PUSH_DATA (push, 0xff);
606 PUSH_DATA (push, 0xff);
607 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
608 PUSH_DATA (push, 0xff);
609 PUSH_DATA (push, 0xff);
610 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
611 PUSH_DATA (push, 0x3f);
612
613 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
614 PUSH_DATA (push, (3 << 16) | 3);
615 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
616 PUSH_DATA (push, (2 << 16) | 2);
617
618 if (obj_class < GM107_3D_CLASS) {
619 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
620 PUSH_DATA (push, 0);
621 }
622 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
623 PUSH_DATA (push, 0x10);
624 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
625 PUSH_DATA (push, 0x10);
626 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
627 PUSH_DATA (push, 0x10);
628 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
629 PUSH_DATA (push, 0x10);
630 PUSH_DATA (push, 0x10);
631 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
632 PUSH_DATA (push, 0x10);
633 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
634 PUSH_DATA (push, 0xe);
635
636 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
637 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
638 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
639 PUSH_DATA (push, 0);
640 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
641 PUSH_DATA (push, 3);
642
643 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
644 PUSH_DATA (push, 0x3fffff);
645 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
646 PUSH_DATA (push, 1);
647 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
648 PUSH_DATA (push, 1);
649
650 if (obj_class < GM107_3D_CLASS) {
651 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
652 PUSH_DATA (push, 3);
653
654 if (obj_class >= NVE4_3D_CLASS) {
655 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
656 PUSH_DATA (push, 1);
657 }
658 }
659
660 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
661 * are supposed to do */
662 }
663
664 static void
665 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
666 {
667 struct nvc0_screen *screen = nvc0_screen(pscreen);
668 struct nouveau_pushbuf *push = screen->base.pushbuf;
669
670 /* we need to do it after possible flush in MARK_RING */
671 *sequence = ++screen->base.fence.sequence;
672
673 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
674 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
675 PUSH_DATAh(push, screen->fence.bo->offset);
676 PUSH_DATA (push, screen->fence.bo->offset);
677 PUSH_DATA (push, *sequence);
678 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
679 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
680 }
681
682 static u32
683 nvc0_screen_fence_update(struct pipe_screen *pscreen)
684 {
685 struct nvc0_screen *screen = nvc0_screen(pscreen);
686 return screen->fence.map[0];
687 }
688
689 static int
690 nvc0_screen_init_compute(struct nvc0_screen *screen)
691 {
692 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
693
694 switch (screen->base.device->chipset & ~0xf) {
695 case 0xc0:
696 case 0xd0:
697 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
698 case 0xe0:
699 case 0xf0:
700 case 0x100:
701 case 0x110:
702 case 0x120:
703 case 0x130:
704 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
705 default:
706 return -1;
707 }
708 }
709
710 static int
711 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
712 uint32_t lpos, uint32_t lneg, uint32_t cstack)
713 {
714 struct nouveau_bo *bo = NULL;
715 int ret;
716 uint64_t size = (lpos + lneg) * 32 + cstack;
717
718 if (size >= (1 << 20)) {
719 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
720 return -1;
721 }
722
723 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
724 size = align(size, 0x8000);
725 size *= screen->mp_count;
726
727 size = align(size, 1 << 17);
728
729 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
730 NULL, &bo);
731 if (ret)
732 return ret;
733 nouveau_bo_ref(NULL, &screen->tls);
734 screen->tls = bo;
735 return 0;
736 }
737
738 int
739 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
740 {
741 struct nouveau_pushbuf *push = screen->base.pushbuf;
742 struct nouveau_bo *bo;
743 int ret;
744
745 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
746 1 << 17, size, NULL, &bo);
747 if (ret)
748 return ret;
749
750 nouveau_bo_ref(NULL, &screen->text);
751 screen->text = bo;
752
753 nouveau_heap_destroy(&screen->lib_code);
754 nouveau_heap_destroy(&screen->text_heap);
755
756 /* XXX: getting a page fault at the end of the code buffer every few
757 * launches, don't use the last 256 bytes to work around them - prefetch ?
758 */
759 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
760
761 /* update the code segment setup */
762 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
763 PUSH_DATAh(push, screen->text->offset);
764 PUSH_DATA (push, screen->text->offset);
765 if (screen->compute) {
766 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
767 PUSH_DATAh(push, screen->text->offset);
768 PUSH_DATA (push, screen->text->offset);
769 }
770
771 return 0;
772 }
773
774 #define FAIL_SCREEN_INIT(str, err) \
775 do { \
776 NOUVEAU_ERR(str, err); \
777 goto fail; \
778 } while(0)
779
780 struct nouveau_screen *
781 nvc0_screen_create(struct nouveau_device *dev)
782 {
783 struct nvc0_screen *screen;
784 struct pipe_screen *pscreen;
785 struct nouveau_object *chan;
786 struct nouveau_pushbuf *push;
787 uint64_t value;
788 uint32_t obj_class;
789 uint32_t flags;
790 int ret;
791 unsigned i;
792
793 switch (dev->chipset & ~0xf) {
794 case 0xc0:
795 case 0xd0:
796 case 0xe0:
797 case 0xf0:
798 case 0x100:
799 case 0x110:
800 case 0x120:
801 case 0x130:
802 break;
803 default:
804 return NULL;
805 }
806
807 screen = CALLOC_STRUCT(nvc0_screen);
808 if (!screen)
809 return NULL;
810 pscreen = &screen->base.base;
811 pscreen->destroy = nvc0_screen_destroy;
812
813 ret = nouveau_screen_init(&screen->base, dev);
814 if (ret)
815 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
816 chan = screen->base.channel;
817 push = screen->base.pushbuf;
818 push->user_priv = screen;
819 push->rsvd_kick = 5;
820
821 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
822 PIPE_BIND_SHADER_BUFFER |
823 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
824 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
825 screen->base.sysmem_bindings |=
826 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
827
828 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
829 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
830 screen->base.vidmem_bindings = 0;
831 }
832
833 pscreen->context_create = nvc0_create;
834 pscreen->is_format_supported = nvc0_screen_is_format_supported;
835 pscreen->get_param = nvc0_screen_get_param;
836 pscreen->get_shader_param = nvc0_screen_get_shader_param;
837 pscreen->get_paramf = nvc0_screen_get_paramf;
838 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
839 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
840
841 nvc0_screen_init_resource_functions(pscreen);
842
843 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
844 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
845
846 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
847 if (screen->base.drm->version >= 0x01000202)
848 flags |= NOUVEAU_BO_COHERENT;
849
850 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
851 if (ret)
852 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
853 nouveau_bo_map(screen->fence.bo, 0, NULL);
854 screen->fence.map = screen->fence.bo->map;
855 screen->base.fence.emit = nvc0_screen_fence_emit;
856 screen->base.fence.update = nvc0_screen_fence_update;
857
858
859 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
860 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
861 if (ret)
862 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
863
864 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
865 PUSH_DATA (push, screen->nvsw->handle);
866
867 switch (dev->chipset & ~0xf) {
868 case 0x130:
869 case 0x120:
870 case 0x110:
871 case 0x100:
872 case 0xf0:
873 obj_class = NVF0_P2MF_CLASS;
874 break;
875 case 0xe0:
876 obj_class = NVE4_P2MF_CLASS;
877 break;
878 default:
879 obj_class = NVC0_M2MF_CLASS;
880 break;
881 }
882 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
883 &screen->m2mf);
884 if (ret)
885 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
886
887 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
888 PUSH_DATA (push, screen->m2mf->oclass);
889 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
890 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
891 PUSH_DATA (push, 0xa0b5);
892 }
893
894 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
895 &screen->eng2d);
896 if (ret)
897 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
898
899 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
900 PUSH_DATA (push, screen->eng2d->oclass);
901 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
902 PUSH_DATA (push, 0);
903 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
904 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
905 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
906 PUSH_DATA (push, 0);
907 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
908 PUSH_DATA (push, 0);
909 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
910 PUSH_DATA (push, 0x3f);
911 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
912 PUSH_DATA (push, 1);
913 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
914 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
915
916 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
917 PUSH_DATAh(push, screen->fence.bo->offset + 16);
918 PUSH_DATA (push, screen->fence.bo->offset + 16);
919
920 switch (dev->chipset & ~0xf) {
921 case 0x130:
922 switch (dev->chipset) {
923 case 0x130:
924 case 0x13b:
925 obj_class = GP100_3D_CLASS;
926 break;
927 default:
928 obj_class = GP102_3D_CLASS;
929 break;
930 }
931 break;
932 case 0x120:
933 obj_class = GM200_3D_CLASS;
934 break;
935 case 0x110:
936 obj_class = GM107_3D_CLASS;
937 break;
938 case 0x100:
939 case 0xf0:
940 obj_class = NVF0_3D_CLASS;
941 break;
942 case 0xe0:
943 switch (dev->chipset) {
944 case 0xea:
945 obj_class = NVEA_3D_CLASS;
946 break;
947 default:
948 obj_class = NVE4_3D_CLASS;
949 break;
950 }
951 break;
952 case 0xd0:
953 obj_class = NVC8_3D_CLASS;
954 break;
955 case 0xc0:
956 default:
957 switch (dev->chipset) {
958 case 0xc8:
959 obj_class = NVC8_3D_CLASS;
960 break;
961 case 0xc1:
962 obj_class = NVC1_3D_CLASS;
963 break;
964 default:
965 obj_class = NVC0_3D_CLASS;
966 break;
967 }
968 break;
969 }
970 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
971 &screen->eng3d);
972 if (ret)
973 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
974 screen->base.class_3d = obj_class;
975
976 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
977 PUSH_DATA (push, screen->eng3d->oclass);
978
979 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
980 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
981
982 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
983 /* kill shaders after about 1 second (at 100 MHz) */
984 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
985 PUSH_DATA (push, 0x17);
986 }
987
988 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
989 screen->base.drm->version >= 0x01000101);
990 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
991 for (i = 0; i < 8; ++i)
992 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
993
994 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
995 PUSH_DATA (push, 1);
996
997 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
998 PUSH_DATA (push, 0);
999 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1000 PUSH_DATA (push, 0);
1001 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1002 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1003 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1004 PUSH_DATA (push, 0);
1005 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1006 PUSH_DATA (push, 1);
1007 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1008 PUSH_DATA (push, 1);
1009 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1010 PUSH_DATA (push, 1);
1011 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1012 PUSH_DATA (push, 0);
1013 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1014 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1015 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1016 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1017 } else {
1018 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1019 PUSH_DATA (push, 15);
1020 }
1021 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1022 PUSH_DATA (push, 8); /* 128 */
1023 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1024 PUSH_DATA (push, 1);
1025 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1026 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1027 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1028 }
1029
1030 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1031
1032 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1033 if (ret)
1034 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1035
1036 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1037 &screen->uniform_bo);
1038 if (ret)
1039 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1040
1041 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1042
1043 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1044 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1045 PUSH_DATA (push, 256);
1046 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1047 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1048 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1049 PUSH_DATA (push, 0);
1050 PUSH_DATAf(push, 0.0f);
1051 PUSH_DATAf(push, 0.0f);
1052 PUSH_DATAf(push, 0.0f);
1053 PUSH_DATAf(push, 0.0f);
1054 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1055 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1056 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1057
1058 if (screen->base.drm->version >= 0x01000101) {
1059 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1060 if (ret)
1061 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1062 } else {
1063 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1064 value = (8 << 8) | 4;
1065 else
1066 value = (16 << 8) | 4;
1067 }
1068 screen->gpc_count = value & 0x000000ff;
1069 screen->mp_count = value >> 8;
1070 screen->mp_count_compute = screen->mp_count;
1071
1072 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1073 if (ret)
1074 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1075
1076 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1077 PUSH_DATAh(push, screen->tls->offset);
1078 PUSH_DATA (push, screen->tls->offset);
1079 PUSH_DATA (push, screen->tls->size >> 32);
1080 PUSH_DATA (push, screen->tls->size);
1081 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1082 PUSH_DATA (push, 0);
1083 /* Reduce likelihood of collision with real buffers by placing the hole at
1084 * the top of the 4G area. This will have to be dealt with for real
1085 * eventually by blocking off that area from the VM.
1086 */
1087 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1088 PUSH_DATA (push, 0xff << 24);
1089
1090 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1091 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1092 &screen->poly_cache);
1093 if (ret)
1094 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1095
1096 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1097 PUSH_DATAh(push, screen->poly_cache->offset);
1098 PUSH_DATA (push, screen->poly_cache->offset);
1099 PUSH_DATA (push, 3);
1100 }
1101
1102 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1103 &screen->txc);
1104 if (ret)
1105 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1106
1107 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1108 PUSH_DATAh(push, screen->txc->offset);
1109 PUSH_DATA (push, screen->txc->offset);
1110 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1111 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1112 screen->tic.maxwell = true;
1113 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1114 screen->tic.maxwell =
1115 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1116 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1117 }
1118 }
1119
1120 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1121 PUSH_DATAh(push, screen->txc->offset + 65536);
1122 PUSH_DATA (push, screen->txc->offset + 65536);
1123 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1124
1125 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1126 PUSH_DATA (push, 0);
1127 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1128 PUSH_DATA (push, 0);
1129 PUSH_DATA (push, 0);
1130 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1131 PUSH_DATA (push, 0x3f);
1132
1133 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1134 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1135 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1136 for (i = 0; i < 8 * 2; ++i)
1137 PUSH_DATA(push, 0);
1138 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1139 PUSH_DATA (push, 0);
1140 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1141 PUSH_DATA (push, 0);
1142
1143 /* neither scissors, viewport nor stencil mask should affect clears */
1144 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1145 PUSH_DATA (push, 0);
1146
1147 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1148 PUSH_DATA (push, 1);
1149 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1150 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1151 PUSH_DATAf(push, 0.0f);
1152 PUSH_DATAf(push, 1.0f);
1153 }
1154 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1155 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1156
1157 /* We use scissors instead of exact view volume clipping,
1158 * so they're always enabled.
1159 */
1160 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1161 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1162 PUSH_DATA (push, 1);
1163 PUSH_DATA (push, 8192 << 16);
1164 PUSH_DATA (push, 8192 << 16);
1165 }
1166
1167 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1168
1169 i = 0;
1170 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1171 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1172 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1173 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1174 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1175 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1176 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1177 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1178 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1179 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1180 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1181 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1182 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1183
1184 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1185 PUSH_DATA (push, 1);
1186 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1187 PUSH_DATA (push, 1);
1188 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1189 PUSH_DATA (push, 0x40);
1190 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1191 PUSH_DATA (push, 0);
1192 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1193 PUSH_DATA (push, 0x30);
1194 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1195 PUSH_DATA (push, 3);
1196 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1197 PUSH_DATA (push, 0x20);
1198 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1199 PUSH_DATA (push, 0x00);
1200 screen->save_state.patch_vertices = 3;
1201
1202 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1203 PUSH_DATA (push, 0);
1204 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1205 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1206
1207 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1208
1209 if (nvc0_screen_init_compute(screen))
1210 goto fail;
1211
1212 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1213 for (i = 0; i < 5; ++i) {
1214 /* TIC and TSC entries for each unit (nve4+ only) */
1215 /* auxiliary constants (6 user clip planes, base instance id) */
1216 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1217 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1218 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1219 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1220 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1221 PUSH_DATA (push, (15 << 4) | 1);
1222 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1223 unsigned j;
1224 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1225 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1226 for (j = 0; j < 8; ++j)
1227 PUSH_DATA(push, j);
1228 } else {
1229 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1230 PUSH_DATA (push, 0x54);
1231 }
1232
1233 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1234 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1235 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1236 PUSH_DATA (push, 0); /* 0 */
1237 PUSH_DATA (push, 0);
1238 PUSH_DATA (push, 1); /* 1 */
1239 PUSH_DATA (push, 0);
1240 PUSH_DATA (push, 0); /* 2 */
1241 PUSH_DATA (push, 1);
1242 PUSH_DATA (push, 1); /* 3 */
1243 PUSH_DATA (push, 1);
1244 PUSH_DATA (push, 2); /* 4 */
1245 PUSH_DATA (push, 0);
1246 PUSH_DATA (push, 3); /* 5 */
1247 PUSH_DATA (push, 0);
1248 PUSH_DATA (push, 2); /* 6 */
1249 PUSH_DATA (push, 1);
1250 PUSH_DATA (push, 3); /* 7 */
1251 PUSH_DATA (push, 1);
1252 }
1253 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1254 PUSH_DATA (push, 0);
1255
1256 PUSH_KICK (push);
1257
1258 screen->tic.entries = CALLOC(4096, sizeof(void *));
1259 screen->tsc.entries = screen->tic.entries + 2048;
1260
1261 if (!nvc0_blitter_create(screen))
1262 goto fail;
1263
1264 screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1265 screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1266
1267 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1268
1269 return &screen->base;
1270
1271 fail:
1272 screen->base.base.context_create = NULL;
1273 return &screen->base;
1274 }
1275
1276 int
1277 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1278 {
1279 int i = screen->tic.next;
1280
1281 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1282 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1283
1284 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1285
1286 if (screen->tic.entries[i])
1287 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1288
1289 screen->tic.entries[i] = entry;
1290 return i;
1291 }
1292
1293 int
1294 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1295 {
1296 int i = screen->tsc.next;
1297
1298 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1299 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1300
1301 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1302
1303 if (screen->tsc.entries[i])
1304 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1305
1306 screen->tsc.entries[i] = entry;
1307 return i;
1308 }