src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/nvc0_graph_macros.h"
  36
  37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  39 #endif
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    if (sample_count > 8)
  49       return FALSE;
  50    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  51       return FALSE;
  52
  53    if (!util_format_is_supported(format, bindings))
  54       return FALSE;
  55
  56    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  57       if (util_format_get_blocksizebits(format) == 3 * 32)
  58          return FALSE;
  59
  60    /* transfers & shared are always supported */
  61    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  62                  PIPE_BIND_TRANSFER_WRITE |
  63                  PIPE_BIND_SHARED);
  64
  65    return (nvc0_format_table[format].usage & bindings) == bindings;
  66 }
  67
  68 static int
  69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  70 {
  71    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  72
  73    switch (param) {
  74    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  75    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  76       return 15;
  77    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  78       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  79    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  80       return 2048;
  81    case PIPE_CAP_MIN_TEXEL_OFFSET:
  82       return -8;
  83    case PIPE_CAP_MAX_TEXEL_OFFSET:
  84       return 7;
  85    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  86    case PIPE_CAP_TEXTURE_SWIZZLE:
  87    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  88    case PIPE_CAP_NPOT_TEXTURES:
  89    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  90    case PIPE_CAP_ANISOTROPIC_FILTER:
  91    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  92    case PIPE_CAP_CUBE_MAP_ARRAY:
  93    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  94    case PIPE_CAP_TEXTURE_MULTISAMPLE:
  95       return 1;
  96    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  97       return 65536;
  98    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  99       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 100    case PIPE_CAP_TWO_SIDED_STENCIL:
 101    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 102    case PIPE_CAP_POINT_SPRITE:
 103    case PIPE_CAP_TGSI_TEXCOORD:
 104       return 1;
 105    case PIPE_CAP_SM3:
 106       return 1;
 107    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 108       return 330;
 109    case PIPE_CAP_MAX_RENDER_TARGETS:
 110       return 8;
 111    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 112       return 1;
 113    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 114    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 115    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 116       return 1;
 117    case PIPE_CAP_QUERY_TIMESTAMP:
 118    case PIPE_CAP_QUERY_TIME_ELAPSED:
 119    case PIPE_CAP_OCCLUSION_QUERY:
 120    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 121    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 122       return 1;
 123    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 124       return 4;
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127       return 128;
 128    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 129    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 130       return 1024;
 131    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 132    case PIPE_CAP_INDEP_BLEND_ENABLE:
 133    case PIPE_CAP_INDEP_BLEND_FUNC:
 134       return 1;
 135    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 136    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 137       return 1;
 138    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 139    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 140       return 0;
 141    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 142       return 0;
 143    case PIPE_CAP_PRIMITIVE_RESTART:
 144    case PIPE_CAP_TGSI_INSTANCEID:
 145    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 146    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 147    case PIPE_CAP_CONDITIONAL_RENDER:
 148    case PIPE_CAP_TEXTURE_BARRIER:
 149    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 150    case PIPE_CAP_START_INSTANCE:
 151       return 1;
 152    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 153       return 0; /* state trackers will know better */
 154    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 155    case PIPE_CAP_USER_INDEX_BUFFERS:
 156    case PIPE_CAP_USER_VERTEX_BUFFERS:
 157       return 1;
 158    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 159       return 256;
 160    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 161       return 1; /* 256 for binding as RT, but that's not possible in GL */
 162    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 163       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 164    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 165    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 166    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 167       return 0;
 168    case PIPE_CAP_COMPUTE:
 169       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 170    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 171       return 1;
 172    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 173       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 174    case PIPE_CAP_ENDIANNESS:
 175       return PIPE_ENDIAN_LITTLE;
 176    case PIPE_CAP_TGSI_VS_LAYER:
 177    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 178    case PIPE_CAP_TEXTURE_GATHER_SM5:
 179    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 180       return 0;
 181    case PIPE_CAP_MAX_VIEWPORTS:
 182       return 1;
 183    default:
 184       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 185       return 0;
 186    }
 187 }
 188
 189 static int
 190 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 191                              enum pipe_shader_cap param)
 192 {
 193    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 194
 195    switch (shader) {
 196    case PIPE_SHADER_VERTEX:
 197       /*
 198    case PIPE_SHADER_TESSELLATION_CONTROL:
 199    case PIPE_SHADER_TESSELLATION_EVALUATION:
 200       */
 201    case PIPE_SHADER_GEOMETRY:
 202    case PIPE_SHADER_FRAGMENT:
 203       break;
 204    case PIPE_SHADER_COMPUTE:
 205       if (class_3d < NVE4_3D_CLASS)
 206          return 0;
 207       break;
 208    default:
 209       return 0;
 210    }
 211
 212    switch (param) {
 213    case PIPE_SHADER_CAP_PREFERRED_IR:
 214       return PIPE_SHADER_IR_TGSI;
 215    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 216    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 217    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 218    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 219       return 16384;
 220    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 221       return 16;
 222    case PIPE_SHADER_CAP_MAX_INPUTS:
 223       if (shader == PIPE_SHADER_VERTEX)
 224          return 32;
 225       /* NOTE: These only count our slots for GENERIC varyings.
 226        * The address space may be larger, but the actual hard limit seems to be
 227        * less than what the address space layout permits, so don't add TEXCOORD,
 228        * COLOR, etc. here.
 229        */
 230       if (shader == PIPE_SHADER_FRAGMENT)
 231          return 0x1f0 / 16;
 232       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 233        * and excludes 0x60 per-patch inputs.
 234        */
 235       return 0x200 / 16;
 236    case PIPE_SHADER_CAP_MAX_CONSTS:
 237       return 65536 / 16;
 238    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 239       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 240          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 241       return NVC0_MAX_PIPE_CONSTBUFS;
 242    case PIPE_SHADER_CAP_MAX_ADDRS:
 243       return 1;
 244    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 245    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 246       return shader != PIPE_SHADER_FRAGMENT;
 247    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 248    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 249       return 1;
 250    case PIPE_SHADER_CAP_MAX_PREDS:
 251       return 0;
 252    case PIPE_SHADER_CAP_MAX_TEMPS:
 253       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 254    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 255       return 1;
 256    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 257       return 0;
 258    case PIPE_SHADER_CAP_SUBROUTINES:
 259       return 1;
 260    case PIPE_SHADER_CAP_INTEGERS:
 261       return 1;
 262    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 263       return 16; /* would be 32 in linked (OpenGL-style) mode */
 264    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 265       return 16; /* XXX not sure if more are really safe */
 266    default:
 267       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 268       return 0;
 269    }
 270 }
 271
 272 static float
 273 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 274 {
 275    switch (param) {
 276    case PIPE_CAPF_MAX_LINE_WIDTH:
 277    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 278       return 10.0f;
 279    case PIPE_CAPF_MAX_POINT_WIDTH:
 280       return 63.0f;
 281    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 282       return 63.375f;
 283    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 284       return 16.0f;
 285    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 286       return 15.0f;
 287    default:
 288       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 289       return 0.0f;
 290    }
 291 }
 292
 293 static int
 294 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 295                               enum pipe_compute_cap param, void *data)
 296 {
 297    uint64_t *data64 = (uint64_t *)data;
 298    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
 299
 300    switch (param) {
 301    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 302       data64[0] = 3;
 303       return 8;
 304    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 305       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
 306       data64[1] = 65535;
 307       data64[2] = 65535;
 308       return 24;
 309    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 310       data64[0] = 1024;
 311       data64[1] = 1024;
 312       data64[2] = 64;
 313       return 24;
 314    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 315       data64[0] = 1024;
 316       return 8;
 317    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 318       data64[0] = (uint64_t)1 << 40;
 319       return 8;
 320    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 321       data64[0] = 48 << 10;
 322       return 8;
 323    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 324       data64[0] = 512 << 10;
 325       return 8;
 326    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 327       data64[0] = 4096;
 328       return 8;
 329    default:
 330       return 0;
 331    }
 332 }
 333
 334 static void
 335 nvc0_screen_destroy(struct pipe_screen *pscreen)
 336 {
 337    struct nvc0_screen *screen = nvc0_screen(pscreen);
 338
 339    if (!nouveau_drm_screen_unref(&screen->base))
 340       return;
 341
 342    if (screen->base.fence.current) {
 343       struct nouveau_fence *current = NULL;
 344
 345       /* nouveau_fence_wait will create a new current fence, so wait on the
 346        * _current_ one, and remove both.
 347        */
 348       nouveau_fence_ref(screen->base.fence.current, &current);
 349       nouveau_fence_wait(current);
 350       nouveau_fence_ref(NULL, &current);
 351       nouveau_fence_ref(NULL, &screen->base.fence.current);
 352    }
 353    if (screen->base.pushbuf)
 354       screen->base.pushbuf->user_priv = NULL;
 355
 356    if (screen->blitter)
 357       nvc0_blitter_destroy(screen);
 358    if (screen->pm.prog) {
 359       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 360       nvc0_program_destroy(NULL, screen->pm.prog);
 361    }
 362
 363    nouveau_bo_ref(NULL, &screen->text);
 364    nouveau_bo_ref(NULL, &screen->uniform_bo);
 365    nouveau_bo_ref(NULL, &screen->tls);
 366    nouveau_bo_ref(NULL, &screen->txc);
 367    nouveau_bo_ref(NULL, &screen->fence.bo);
 368    nouveau_bo_ref(NULL, &screen->poly_cache);
 369    nouveau_bo_ref(NULL, &screen->parm);
 370
 371    nouveau_heap_destroy(&screen->lib_code);
 372    nouveau_heap_destroy(&screen->text_heap);
 373
 374    FREE(screen->tic.entries);
 375
 376    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 377
 378    nouveau_object_del(&screen->eng3d);
 379    nouveau_object_del(&screen->eng2d);
 380    nouveau_object_del(&screen->m2mf);
 381    nouveau_object_del(&screen->compute);
 382    nouveau_object_del(&screen->nvsw);
 383
 384    nouveau_screen_fini(&screen->base);
 385
 386    FREE(screen);
 387 }
 388
 389 static int
 390 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 391                      unsigned size, const uint32_t *data)
 392 {
 393    struct nouveau_pushbuf *push = screen->base.pushbuf;
 394
 395    size /= 4;
 396
 397    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 398    PUSH_DATA (push, (m - 0x3800) / 8);
 399    PUSH_DATA (push, pos);
 400    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 401    PUSH_DATA (push, pos);
 402    PUSH_DATAp(push, data, size);
 403
 404    return pos + size;
 405 }
 406
 407 static void
 408 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 409 {
 410    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 411    PUSH_DATA (push, 0xff);
 412    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 413    PUSH_DATA (push, 0xff);
 414    PUSH_DATA (push, 0xff);
 415    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 416    PUSH_DATA (push, 0xff);
 417    PUSH_DATA (push, 0xff);
 418    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 419    PUSH_DATA (push, 0x3f);
 420
 421    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 422    PUSH_DATA (push, (3 << 16) | 3);
 423    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 424    PUSH_DATA (push, (2 << 16) | 2);
 425    BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
 426    PUSH_DATA (push, 1);
 427
 428    BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 429    PUSH_DATA (push, 0);
 430    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 431    PUSH_DATA (push, 0x10);
 432    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 433    PUSH_DATA (push, 0x10);
 434    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 435    PUSH_DATA (push, 0x10);
 436    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 437    PUSH_DATA (push, 0x10);
 438    PUSH_DATA (push, 0x10);
 439    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 440    PUSH_DATA (push, 0x10);
 441    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 442    PUSH_DATA (push, 0xe);
 443
 444    BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
 445    PUSH_DATA (push, 1 << 12);
 446    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 447    PUSH_DATA (push, 0);
 448    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 449    PUSH_DATA (push, 3);
 450
 451    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 452    PUSH_DATA (push, 0x3fffff);
 453    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 454    PUSH_DATA (push, 1);
 455    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 456    PUSH_DATA (push, 1);
 457    BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 458    PUSH_DATA (push, 3);
 459
 460    if (obj_class >= NVE4_3D_CLASS) {
 461       BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 462       PUSH_DATA (push, 1);
 463    }
 464
 465    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 466     * are supposed to do */
 467 }
 468
 469 static void
 470 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 471 {
 472    struct nvc0_screen *screen = nvc0_screen(pscreen);
 473    struct nouveau_pushbuf *push = screen->base.pushbuf;
 474
 475    /* we need to do it after possible flush in MARK_RING */
 476    *sequence = ++screen->base.fence.sequence;
 477
 478    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
 479    PUSH_DATAh(push, screen->fence.bo->offset);
 480    PUSH_DATA (push, screen->fence.bo->offset);
 481    PUSH_DATA (push, *sequence);
 482    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 483               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 484 }
 485
 486 static u32
 487 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 488 {
 489    struct nvc0_screen *screen = nvc0_screen(pscreen);
 490    return screen->fence.map[0];
 491 }
 492
 493 static int
 494 nvc0_screen_init_compute(struct nvc0_screen *screen)
 495 {
 496    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 497
 498    switch (screen->base.device->chipset & ~0xf) {
 499    case 0xc0:
 500    case 0xd0:
 501       /* Using COMPUTE has weird effects on 3D state, we need to
 502        * investigate this further before enabling it by default.
 503        */
 504       if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
 505          return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 506       return 0;
 507    case 0xe0:
 508    case 0xf0:
 509    case 0x100:
 510       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 511    default:
 512       return -1;
 513    }
 514 }
 515
 516 boolean
 517 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 518                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 519 {
 520    struct nouveau_bo *bo = NULL;
 521    int ret;
 522    uint64_t size = (lpos + lneg) * 32 + cstack;
 523
 524    if (size >= (1 << 20)) {
 525       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 526       return FALSE;
 527    }
 528
 529    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 530    size  = align(size, 0x8000);
 531    size *= screen->mp_count;
 532
 533    size = align(size, 1 << 17);
 534
 535    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
 536                         NULL, &bo);
 537    if (ret) {
 538       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 539       return FALSE;
 540    }
 541    nouveau_bo_ref(NULL, &screen->tls);
 542    screen->tls = bo;
 543    return TRUE;
 544 }
 545
 546 #define FAIL_SCREEN_INIT(str, err)                    \
 547    do {                                               \
 548       NOUVEAU_ERR(str, err);                          \
 549       nvc0_screen_destroy(pscreen);                   \
 550       return NULL;                                    \
 551    } while(0)
 552
 553 struct pipe_screen *
 554 nvc0_screen_create(struct nouveau_device *dev)
 555 {
 556    struct nvc0_screen *screen;
 557    struct pipe_screen *pscreen;
 558    struct nouveau_object *chan;
 559    struct nouveau_pushbuf *push;
 560    uint64_t value;
 561    uint32_t obj_class;
 562    int ret;
 563    unsigned i;
 564    union nouveau_bo_config mm_config;
 565
 566    switch (dev->chipset & ~0xf) {
 567    case 0xc0:
 568    case 0xd0:
 569    case 0xe0:
 570    case 0xf0:
 571    case 0x100:
 572       break;
 573    default:
 574       return NULL;
 575    }
 576
 577    screen = CALLOC_STRUCT(nvc0_screen);
 578    if (!screen)
 579       return NULL;
 580    pscreen = &screen->base.base;
 581
 582    ret = nouveau_screen_init(&screen->base, dev);
 583    if (ret) {
 584       nvc0_screen_destroy(pscreen);
 585       return NULL;
 586    }
 587    chan = screen->base.channel;
 588    push = screen->base.pushbuf;
 589    push->user_priv = screen;
 590    push->rsvd_kick = 5;
 591
 592    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 593       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 594    screen->base.sysmem_bindings |=
 595       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 596
 597    pscreen->destroy = nvc0_screen_destroy;
 598    pscreen->context_create = nvc0_create;
 599    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 600    pscreen->get_param = nvc0_screen_get_param;
 601    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 602    pscreen->get_paramf = nvc0_screen_get_paramf;
 603    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 604
 605    nvc0_screen_init_resource_functions(pscreen);
 606
 607    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 608    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 609
 610    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
 611                         &screen->fence.bo);
 612    if (ret)
 613       goto fail;
 614    nouveau_bo_map(screen->fence.bo, 0, NULL);
 615    screen->fence.map = screen->fence.bo->map;
 616    screen->base.fence.emit = nvc0_screen_fence_emit;
 617    screen->base.fence.update = nvc0_screen_fence_update;
 618
 619
 620    ret = nouveau_object_new(chan,
 621                             (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
 622                             NULL, 0, &screen->nvsw);
 623    if (ret)
 624       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 625
 626
 627    switch (dev->chipset & ~0xf) {
 628    case 0x100:
 629    case 0xf0:
 630       obj_class = NVF0_P2MF_CLASS;
 631       break;
 632    case 0xe0:
 633       obj_class = NVE4_P2MF_CLASS;
 634       break;
 635    default:
 636       obj_class = NVC0_M2MF_CLASS;
 637       break;
 638    }
 639    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 640                             &screen->m2mf);
 641    if (ret)
 642       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 643
 644    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 645    PUSH_DATA (push, screen->m2mf->oclass);
 646    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 647       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 648       PUSH_DATA (push, 0xa0b5);
 649    }
 650
 651    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 652                             &screen->eng2d);
 653    if (ret)
 654       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 655
 656    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 657    PUSH_DATA (push, screen->eng2d->oclass);
 658    BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
 659    PUSH_DATA (push, 0);
 660    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 661    PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
 662    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 663    PUSH_DATA (push, 0);
 664    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 665    PUSH_DATA (push, 0);
 666    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 667    PUSH_DATA (push, 0x3f);
 668    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 669    PUSH_DATA (push, 1);
 670
 671    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 672    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 673    PUSH_DATA (push, screen->fence.bo->offset + 16);
 674
 675    switch (dev->chipset & ~0xf) {
 676    case 0x100:
 677    case 0xf0:
 678       obj_class = NVF0_3D_CLASS;
 679       break;
 680    case 0xe0:
 681       obj_class = NVE4_3D_CLASS;
 682       break;
 683    case 0xd0:
 684       obj_class = NVC8_3D_CLASS;
 685       break;
 686    case 0xc0:
 687    default:
 688       switch (dev->chipset) {
 689       case 0xc8:
 690          obj_class = NVC8_3D_CLASS;
 691          break;
 692       case 0xc1:
 693          obj_class = NVC1_3D_CLASS;
 694          break;
 695       default:
 696          obj_class = NVC0_3D_CLASS;
 697          break;
 698       }
 699       break;
 700    }
 701    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 702                             &screen->eng3d);
 703    if (ret)
 704       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 705    screen->base.class_3d = obj_class;
 706
 707    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 708    PUSH_DATA (push, screen->eng3d->oclass);
 709
 710    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 711    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 712
 713    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 714       /* kill shaders after about 1 second (at 100 MHz) */
 715       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 716       PUSH_DATA (push, 0x17);
 717    }
 718
 719    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
 720    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 721    for (i = 0; i < 8; ++i)
 722            PUSH_DATA(push, dev->drm_version >= 0x01000101);
 723
 724    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 725    PUSH_DATA (push, 1);
 726
 727    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 728    PUSH_DATA (push, 0);
 729    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 730    PUSH_DATA (push, 0);
 731    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 732    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 733    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 734    PUSH_DATA (push, 0);
 735    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 736    PUSH_DATA (push, 1);
 737    BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
 738    PUSH_DATA (push, 0);
 739    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 740    PUSH_DATA (push, 1);
 741    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 742    PUSH_DATA (push, 0);
 743    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 744       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 745       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 746    } else {
 747       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 748       PUSH_DATA (push, 15);
 749    }
 750    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 751    PUSH_DATA (push, 8); /* 128 */
 752    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 753    PUSH_DATA (push, 1);
 754    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 755       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 756       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 757    }
 758
 759    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 760
 761    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 762                         &screen->text);
 763    if (ret)
 764       goto fail;
 765
 766    /* XXX: getting a page fault at the end of the code buffer every few
 767     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 768     */
 769    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 770
 771    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
 772                         &screen->uniform_bo);
 773    if (ret)
 774       goto fail;
 775
 776    PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 777
 778    for (i = 0; i < 5; ++i) {
 779       /* TIC and TSC entries for each unit (nve4+ only) */
 780       /* auxiliary constants (6 user clip planes, base instance id) */
 781       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 782       PUSH_DATA (push, 512);
 783       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 784       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 785       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 786       PUSH_DATA (push, (15 << 4) | 1);
 787       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 788          unsigned j;
 789          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 790          PUSH_DATA (push, 0);
 791          for (j = 0; j < 8; ++j)
 792             PUSH_DATA(push, j);
 793       } else {
 794          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 795          PUSH_DATA (push, 0x54);
 796       }
 797    }
 798    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 799    PUSH_DATA (push, 0);
 800
 801    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 802    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 803    PUSH_DATA (push, 256);
 804    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 805    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 806    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 807    PUSH_DATA (push, 0);
 808    PUSH_DATAf(push, 0.0f);
 809    PUSH_DATAf(push, 0.0f);
 810    PUSH_DATAf(push, 0.0f);
 811    PUSH_DATAf(push, 0.0f);
 812    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 813    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 814    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 815
 816    if (dev->drm_version >= 0x01000101) {
 817       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 818       if (ret) {
 819          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 820          goto fail;
 821       }
 822    } else {
 823       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 824          value = (8 << 8) | 4;
 825       else
 826          value = (16 << 8) | 4;
 827    }
 828    screen->mp_count = value >> 8;
 829    screen->mp_count_compute = screen->mp_count;
 830
 831    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 832
 833    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 834    PUSH_DATAh(push, screen->text->offset);
 835    PUSH_DATA (push, screen->text->offset);
 836    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 837    PUSH_DATAh(push, screen->tls->offset);
 838    PUSH_DATA (push, screen->tls->offset);
 839    PUSH_DATA (push, screen->tls->size >> 32);
 840    PUSH_DATA (push, screen->tls->size);
 841    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 842    PUSH_DATA (push, 0);
 843    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 844    PUSH_DATA (push, 0);
 845
 846    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 847                         &screen->poly_cache);
 848    if (ret)
 849       goto fail;
 850
 851    BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 852    PUSH_DATAh(push, screen->poly_cache->offset);
 853    PUSH_DATA (push, screen->poly_cache->offset);
 854    PUSH_DATA (push, 3);
 855
 856    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
 857                         &screen->txc);
 858    if (ret)
 859       goto fail;
 860
 861    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 862    PUSH_DATAh(push, screen->txc->offset);
 863    PUSH_DATA (push, screen->txc->offset);
 864    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 865
 866    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 867    PUSH_DATAh(push, screen->txc->offset + 65536);
 868    PUSH_DATA (push, screen->txc->offset + 65536);
 869    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 870
 871    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 872    PUSH_DATA (push, 0);
 873    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 874    PUSH_DATA (push, 0);
 875    PUSH_DATA (push, 0);
 876    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 877    PUSH_DATA (push, 0x3f);
 878
 879    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 880    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 881    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 882    for (i = 0; i < 8 * 2; ++i)
 883       PUSH_DATA(push, 0);
 884    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 885    PUSH_DATA (push, 0);
 886    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 887    PUSH_DATA (push, 0);
 888
 889    /* neither scissors, viewport nor stencil mask should affect clears */
 890    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 891    PUSH_DATA (push, 0);
 892
 893    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 894    PUSH_DATA (push, 1);
 895    BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
 896    PUSH_DATAf(push, 0.0f);
 897    PUSH_DATAf(push, 1.0f);
 898    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 899    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 900
 901    /* We use scissors instead of exact view volume clipping,
 902     * so they're always enabled.
 903     */
 904    BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
 905    PUSH_DATA (push, 1);
 906    PUSH_DATA (push, 8192 << 16);
 907    PUSH_DATA (push, 8192 << 16);
 908
 909 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 910
 911    i = 0;
 912    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
 913    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
 914    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 915    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
 916    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
 917    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 918    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 919
 920    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
 921    PUSH_DATA (push, 1);
 922    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
 923    PUSH_DATA (push, 1);
 924    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 925    PUSH_DATA (push, 0x40);
 926    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
 927    PUSH_DATA (push, 0);
 928    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 929    PUSH_DATA (push, 0x30);
 930    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
 931    PUSH_DATA (push, 3);
 932    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
 933    PUSH_DATA (push, 0x20);
 934    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
 935    PUSH_DATA (push, 0x00);
 936
 937    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
 938    PUSH_DATA (push, 0);
 939    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
 940    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
 941
 942    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
 943
 944    if (nvc0_screen_init_compute(screen))
 945       goto fail;
 946
 947    PUSH_KICK (push);
 948
 949    screen->tic.entries = CALLOC(4096, sizeof(void *));
 950    screen->tsc.entries = screen->tic.entries + 2048;
 951
 952    mm_config.nvc0.tile_mode = 0;
 953    mm_config.nvc0.memtype = 0xfe0;
 954    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
 955
 956    if (!nvc0_blitter_create(screen))
 957       goto fail;
 958
 959    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 960
 961    return pscreen;
 962
 963 fail:
 964    nvc0_screen_destroy(pscreen);
 965    return NULL;
 966 }
 967
 968 int
 969 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 970 {
 971    int i = screen->tic.next;
 972
 973    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 974       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 975
 976    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 977
 978    if (screen->tic.entries[i])
 979       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 980
 981    screen->tic.entries[i] = entry;
 982    return i;
 983 }
 984
 985 int
 986 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 987 {
 988    int i = screen->tsc.next;
 989
 990    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 991       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 992
 993    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 994
 995    if (screen->tsc.entries[i])
 996       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 997
 998    screen->tsc.entries[i] = entry;
 999    return i;
1000 }