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nvc0: add ARB_shader_draw_parameters support
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 if (sample_count > 8)
48 return false;
49 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
50 return false;
51
52 if (!util_format_is_supported(format, bindings))
53 return false;
54
55 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
56 if (util_format_get_blocksizebits(format) == 3 * 32)
57 return false;
58
59 /* transfers & shared are always supported */
60 bindings &= ~(PIPE_BIND_TRANSFER_READ |
61 PIPE_BIND_TRANSFER_WRITE |
62 PIPE_BIND_SHARED);
63
64 return (nvc0_format_table[format].usage & bindings) == bindings;
65 }
66
67 static int
68 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
69 {
70 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
71 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
72
73 switch (param) {
74 /* non-boolean caps */
75 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
76 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
77 return 15;
78 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
79 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
80 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
81 return 2048;
82 case PIPE_CAP_MIN_TEXEL_OFFSET:
83 return -8;
84 case PIPE_CAP_MAX_TEXEL_OFFSET:
85 return 7;
86 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
87 return -32;
88 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
89 return 31;
90 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
91 return 128 * 1024 * 1024;
92 case PIPE_CAP_GLSL_FEATURE_LEVEL:
93 return 410;
94 case PIPE_CAP_MAX_RENDER_TARGETS:
95 return 8;
96 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
97 return 1;
98 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
99 return 4;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
101 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
102 return 128;
103 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
104 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
105 return 1024;
106 case PIPE_CAP_MAX_VERTEX_STREAMS:
107 return 4;
108 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
109 return 2048;
110 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
111 return 256;
112 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
113 return 1; /* 256 for binding as RT, but that's not possible in GL */
114 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
115 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
116 case PIPE_CAP_MAX_VIEWPORTS:
117 return NVC0_MAX_VIEWPORTS;
118 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
119 return 4;
120 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
121 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
122 case PIPE_CAP_ENDIANNESS:
123 return PIPE_ENDIAN_LITTLE;
124 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
125 return 30;
126
127 /* supported caps */
128 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
129 case PIPE_CAP_TEXTURE_SWIZZLE:
130 case PIPE_CAP_TEXTURE_SHADOW_MAP:
131 case PIPE_CAP_NPOT_TEXTURES:
132 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
133 case PIPE_CAP_ANISOTROPIC_FILTER:
134 case PIPE_CAP_SEAMLESS_CUBE_MAP:
135 case PIPE_CAP_CUBE_MAP_ARRAY:
136 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
137 case PIPE_CAP_TEXTURE_MULTISAMPLE:
138 case PIPE_CAP_TWO_SIDED_STENCIL:
139 case PIPE_CAP_DEPTH_CLIP_DISABLE:
140 case PIPE_CAP_POINT_SPRITE:
141 case PIPE_CAP_TGSI_TEXCOORD:
142 case PIPE_CAP_SM3:
143 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
144 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
145 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
146 case PIPE_CAP_QUERY_TIMESTAMP:
147 case PIPE_CAP_QUERY_TIME_ELAPSED:
148 case PIPE_CAP_OCCLUSION_QUERY:
149 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
150 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
151 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
152 case PIPE_CAP_INDEP_BLEND_ENABLE:
153 case PIPE_CAP_INDEP_BLEND_FUNC:
154 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
155 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
156 case PIPE_CAP_PRIMITIVE_RESTART:
157 case PIPE_CAP_TGSI_INSTANCEID:
158 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
159 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
160 case PIPE_CAP_CONDITIONAL_RENDER:
161 case PIPE_CAP_TEXTURE_BARRIER:
162 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
163 case PIPE_CAP_START_INSTANCE:
164 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
165 case PIPE_CAP_DRAW_INDIRECT:
166 case PIPE_CAP_USER_CONSTANT_BUFFERS:
167 case PIPE_CAP_USER_INDEX_BUFFERS:
168 case PIPE_CAP_USER_VERTEX_BUFFERS:
169 case PIPE_CAP_TEXTURE_QUERY_LOD:
170 case PIPE_CAP_SAMPLE_SHADING:
171 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
172 case PIPE_CAP_TEXTURE_GATHER_SM5:
173 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
174 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
175 case PIPE_CAP_SAMPLER_VIEW_TARGET:
176 case PIPE_CAP_CLIP_HALFZ:
177 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
178 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
179 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
180 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
181 case PIPE_CAP_DEPTH_BOUNDS_TEST:
182 case PIPE_CAP_TGSI_TXQS:
183 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
184 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
185 case PIPE_CAP_SHAREABLE_SHADERS:
186 case PIPE_CAP_CLEAR_TEXTURE:
187 case PIPE_CAP_DRAW_PARAMETERS:
188 return 1;
189 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
190 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
191 case PIPE_CAP_COMPUTE:
192 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
193 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
194 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
195
196 /* unsupported caps */
197 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
198 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
199 case PIPE_CAP_SHADER_STENCIL_EXPORT:
200 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
201 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
202 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
203 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
204 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
205 case PIPE_CAP_FAKE_SW_MSAA:
206 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
207 case PIPE_CAP_VERTEXID_NOBASE:
208 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
209 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
210 return 0;
211
212 case PIPE_CAP_VENDOR_ID:
213 return 0x10de;
214 case PIPE_CAP_DEVICE_ID: {
215 uint64_t device_id;
216 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
217 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
218 return -1;
219 }
220 return device_id;
221 }
222 case PIPE_CAP_ACCELERATED:
223 return 1;
224 case PIPE_CAP_VIDEO_MEMORY:
225 return dev->vram_size >> 20;
226 case PIPE_CAP_UMA:
227 return 0;
228 }
229
230 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
231 return 0;
232 }
233
234 static int
235 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
236 enum pipe_shader_cap param)
237 {
238 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
239
240 switch (shader) {
241 case PIPE_SHADER_VERTEX:
242 case PIPE_SHADER_GEOMETRY:
243 case PIPE_SHADER_FRAGMENT:
244 break;
245 case PIPE_SHADER_TESS_CTRL:
246 case PIPE_SHADER_TESS_EVAL:
247 if (class_3d >= GM107_3D_CLASS)
248 return 0;
249 break;
250 case PIPE_SHADER_COMPUTE:
251 if (class_3d > NVE4_3D_CLASS)
252 return 0;
253 break;
254 default:
255 return 0;
256 }
257
258 switch (param) {
259 case PIPE_SHADER_CAP_PREFERRED_IR:
260 return PIPE_SHADER_IR_TGSI;
261 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
262 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
263 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
264 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
265 return 16384;
266 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
267 return 16;
268 case PIPE_SHADER_CAP_MAX_INPUTS:
269 if (shader == PIPE_SHADER_VERTEX)
270 return 32;
271 /* NOTE: These only count our slots for GENERIC varyings.
272 * The address space may be larger, but the actual hard limit seems to be
273 * less than what the address space layout permits, so don't add TEXCOORD,
274 * COLOR, etc. here.
275 */
276 if (shader == PIPE_SHADER_FRAGMENT)
277 return 0x1f0 / 16;
278 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
279 * and excludes 0x60 per-patch inputs.
280 */
281 return 0x200 / 16;
282 case PIPE_SHADER_CAP_MAX_OUTPUTS:
283 return 32;
284 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
285 return 65536;
286 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
287 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
288 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
289 return NVC0_MAX_PIPE_CONSTBUFS;
290 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
291 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
292 return shader != PIPE_SHADER_FRAGMENT;
293 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
294 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
295 return 1;
296 case PIPE_SHADER_CAP_MAX_PREDS:
297 return 0;
298 case PIPE_SHADER_CAP_MAX_TEMPS:
299 return NVC0_CAP_MAX_PROGRAM_TEMPS;
300 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
301 return 1;
302 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
303 return 0;
304 case PIPE_SHADER_CAP_SUBROUTINES:
305 return 1;
306 case PIPE_SHADER_CAP_INTEGERS:
307 return 1;
308 case PIPE_SHADER_CAP_DOUBLES:
309 return 1;
310 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
311 return 1;
312 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
313 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
314 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
315 return 0;
316 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
317 return 16; /* would be 32 in linked (OpenGL-style) mode */
318 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
319 return 16; /* XXX not sure if more are really safe */
320 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
321 return 32;
322 default:
323 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
324 return 0;
325 }
326 }
327
328 static float
329 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
330 {
331 switch (param) {
332 case PIPE_CAPF_MAX_LINE_WIDTH:
333 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
334 return 10.0f;
335 case PIPE_CAPF_MAX_POINT_WIDTH:
336 return 63.0f;
337 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
338 return 63.375f;
339 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
340 return 16.0f;
341 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
342 return 15.0f;
343 case PIPE_CAPF_GUARD_BAND_LEFT:
344 case PIPE_CAPF_GUARD_BAND_TOP:
345 return 0.0f;
346 case PIPE_CAPF_GUARD_BAND_RIGHT:
347 case PIPE_CAPF_GUARD_BAND_BOTTOM:
348 return 0.0f; /* that or infinity */
349 }
350
351 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
352 return 0.0f;
353 }
354
355 static int
356 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
357 enum pipe_compute_cap param, void *data)
358 {
359 struct nvc0_screen *screen = nvc0_screen(pscreen);
360 const uint16_t obj_class = screen->compute->oclass;
361
362 #define RET(x) do { \
363 if (data) \
364 memcpy(data, x, sizeof(x)); \
365 return sizeof(x); \
366 } while (0)
367
368 switch (param) {
369 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
370 RET((uint64_t []) { 3 });
371 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
372 if (obj_class >= NVE4_COMPUTE_CLASS) {
373 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
374 } else {
375 RET(((uint64_t []) { 65535, 65535, 65535 }));
376 }
377 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
378 RET(((uint64_t []) { 1024, 1024, 64 }));
379 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
380 RET((uint64_t []) { 1024 });
381 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
382 RET((uint64_t []) { 1ULL << 40 });
383 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
384 RET((uint64_t []) { 48 << 10 });
385 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
386 RET((uint64_t []) { 512 << 10 });
387 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
388 RET((uint64_t []) { 4096 });
389 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
390 RET((uint32_t []) { 32 });
391 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
392 RET((uint64_t []) { 1ULL << 40 });
393 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
394 RET((uint32_t []) { 0 });
395 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
396 RET((uint32_t []) { screen->mp_count_compute });
397 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
398 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
399 default:
400 return 0;
401 }
402
403 #undef RET
404 }
405
406 static void
407 nvc0_screen_destroy(struct pipe_screen *pscreen)
408 {
409 struct nvc0_screen *screen = nvc0_screen(pscreen);
410
411 if (!nouveau_drm_screen_unref(&screen->base))
412 return;
413
414 if (screen->base.fence.current) {
415 struct nouveau_fence *current = NULL;
416
417 /* nouveau_fence_wait will create a new current fence, so wait on the
418 * _current_ one, and remove both.
419 */
420 nouveau_fence_ref(screen->base.fence.current, &current);
421 nouveau_fence_wait(current, NULL);
422 nouveau_fence_ref(NULL, &current);
423 nouveau_fence_ref(NULL, &screen->base.fence.current);
424 }
425 if (screen->base.pushbuf)
426 screen->base.pushbuf->user_priv = NULL;
427
428 if (screen->blitter)
429 nvc0_blitter_destroy(screen);
430 if (screen->pm.prog) {
431 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
432 nvc0_program_destroy(NULL, screen->pm.prog);
433 FREE(screen->pm.prog);
434 }
435
436 nouveau_bo_ref(NULL, &screen->text);
437 nouveau_bo_ref(NULL, &screen->uniform_bo);
438 nouveau_bo_ref(NULL, &screen->tls);
439 nouveau_bo_ref(NULL, &screen->txc);
440 nouveau_bo_ref(NULL, &screen->fence.bo);
441 nouveau_bo_ref(NULL, &screen->poly_cache);
442 nouveau_bo_ref(NULL, &screen->parm);
443
444 nouveau_heap_destroy(&screen->lib_code);
445 nouveau_heap_destroy(&screen->text_heap);
446
447 FREE(screen->tic.entries);
448
449 nouveau_object_del(&screen->eng3d);
450 nouveau_object_del(&screen->eng2d);
451 nouveau_object_del(&screen->m2mf);
452 nouveau_object_del(&screen->compute);
453 nouveau_object_del(&screen->nvsw);
454
455 nouveau_screen_fini(&screen->base);
456
457 FREE(screen);
458 }
459
460 static int
461 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
462 unsigned size, const uint32_t *data)
463 {
464 struct nouveau_pushbuf *push = screen->base.pushbuf;
465
466 size /= 4;
467
468 assert((pos + size) <= 0x800);
469
470 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
471 PUSH_DATA (push, (m - 0x3800) / 8);
472 PUSH_DATA (push, pos);
473 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
474 PUSH_DATA (push, pos);
475 PUSH_DATAp(push, data, size);
476
477 return pos + size;
478 }
479
480 static void
481 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
482 {
483 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
484 PUSH_DATA (push, 0xff);
485 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
486 PUSH_DATA (push, 0xff);
487 PUSH_DATA (push, 0xff);
488 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
489 PUSH_DATA (push, 0xff);
490 PUSH_DATA (push, 0xff);
491 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
492 PUSH_DATA (push, 0x3f);
493
494 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
495 PUSH_DATA (push, (3 << 16) | 3);
496 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
497 PUSH_DATA (push, (2 << 16) | 2);
498
499 if (obj_class < GM107_3D_CLASS) {
500 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
501 PUSH_DATA (push, 0);
502 }
503 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
504 PUSH_DATA (push, 0x10);
505 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
506 PUSH_DATA (push, 0x10);
507 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
508 PUSH_DATA (push, 0x10);
509 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
510 PUSH_DATA (push, 0x10);
511 PUSH_DATA (push, 0x10);
512 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
513 PUSH_DATA (push, 0x10);
514 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
515 PUSH_DATA (push, 0xe);
516
517 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
518 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
519 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
520 PUSH_DATA (push, 0);
521 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
522 PUSH_DATA (push, 3);
523
524 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
525 PUSH_DATA (push, 0x3fffff);
526 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
527 PUSH_DATA (push, 1);
528 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
529 PUSH_DATA (push, 1);
530
531 if (obj_class < GM107_3D_CLASS) {
532 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
533 PUSH_DATA (push, 3);
534
535 if (obj_class >= NVE4_3D_CLASS) {
536 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
537 PUSH_DATA (push, 1);
538 }
539 }
540
541 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
542 * are supposed to do */
543 }
544
545 static void
546 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
547 {
548 struct nvc0_screen *screen = nvc0_screen(pscreen);
549 struct nouveau_pushbuf *push = screen->base.pushbuf;
550
551 /* we need to do it after possible flush in MARK_RING */
552 *sequence = ++screen->base.fence.sequence;
553
554 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
555 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
556 PUSH_DATAh(push, screen->fence.bo->offset);
557 PUSH_DATA (push, screen->fence.bo->offset);
558 PUSH_DATA (push, *sequence);
559 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
560 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
561 }
562
563 static u32
564 nvc0_screen_fence_update(struct pipe_screen *pscreen)
565 {
566 struct nvc0_screen *screen = nvc0_screen(pscreen);
567 return screen->fence.map[0];
568 }
569
570 static int
571 nvc0_screen_init_compute(struct nvc0_screen *screen)
572 {
573 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
574
575 switch (screen->base.device->chipset & ~0xf) {
576 case 0xc0:
577 case 0xd0:
578 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
579 case 0xe0:
580 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
581 case 0xf0:
582 case 0x100:
583 case 0x110:
584 return 0;
585 default:
586 return -1;
587 }
588 }
589
590 bool
591 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
592 uint32_t lpos, uint32_t lneg, uint32_t cstack)
593 {
594 struct nouveau_bo *bo = NULL;
595 int ret;
596 uint64_t size = (lpos + lneg) * 32 + cstack;
597
598 if (size >= (1 << 20)) {
599 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
600 return false;
601 }
602
603 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
604 size = align(size, 0x8000);
605 size *= screen->mp_count;
606
607 size = align(size, 1 << 17);
608
609 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
610 NULL, &bo);
611 if (ret) {
612 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
613 return false;
614 }
615 nouveau_bo_ref(NULL, &screen->tls);
616 screen->tls = bo;
617 return true;
618 }
619
620 #define FAIL_SCREEN_INIT(str, err) \
621 do { \
622 NOUVEAU_ERR(str, err); \
623 goto fail; \
624 } while(0)
625
626 struct nouveau_screen *
627 nvc0_screen_create(struct nouveau_device *dev)
628 {
629 struct nvc0_screen *screen;
630 struct pipe_screen *pscreen;
631 struct nouveau_object *chan;
632 struct nouveau_pushbuf *push;
633 uint64_t value;
634 uint32_t obj_class;
635 uint32_t flags;
636 int ret;
637 unsigned i;
638
639 switch (dev->chipset & ~0xf) {
640 case 0xc0:
641 case 0xd0:
642 case 0xe0:
643 case 0xf0:
644 case 0x100:
645 case 0x110:
646 break;
647 default:
648 return NULL;
649 }
650
651 screen = CALLOC_STRUCT(nvc0_screen);
652 if (!screen)
653 return NULL;
654 pscreen = &screen->base.base;
655 pscreen->destroy = nvc0_screen_destroy;
656
657 ret = nouveau_screen_init(&screen->base, dev);
658 if (ret) {
659 nvc0_screen_destroy(pscreen);
660 return NULL;
661 }
662 chan = screen->base.channel;
663 push = screen->base.pushbuf;
664 push->user_priv = screen;
665 push->rsvd_kick = 5;
666
667 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
668 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
669 PIPE_BIND_COMMAND_ARGS_BUFFER;
670 screen->base.sysmem_bindings |=
671 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
672
673 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
674 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
675 screen->base.vidmem_bindings = 0;
676 }
677
678 pscreen->context_create = nvc0_create;
679 pscreen->is_format_supported = nvc0_screen_is_format_supported;
680 pscreen->get_param = nvc0_screen_get_param;
681 pscreen->get_shader_param = nvc0_screen_get_shader_param;
682 pscreen->get_paramf = nvc0_screen_get_paramf;
683 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
684 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
685
686 nvc0_screen_init_resource_functions(pscreen);
687
688 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
689 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
690
691 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
692 if (screen->base.drm->version >= 0x01000202)
693 flags |= NOUVEAU_BO_COHERENT;
694
695 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
696 if (ret)
697 goto fail;
698 nouveau_bo_map(screen->fence.bo, 0, NULL);
699 screen->fence.map = screen->fence.bo->map;
700 screen->base.fence.emit = nvc0_screen_fence_emit;
701 screen->base.fence.update = nvc0_screen_fence_update;
702
703
704 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
705 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
706 if (ret)
707 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
708
709 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
710 PUSH_DATA (push, screen->nvsw->handle);
711
712 switch (dev->chipset & ~0xf) {
713 case 0x110:
714 case 0x100:
715 case 0xf0:
716 obj_class = NVF0_P2MF_CLASS;
717 break;
718 case 0xe0:
719 obj_class = NVE4_P2MF_CLASS;
720 break;
721 default:
722 obj_class = NVC0_M2MF_CLASS;
723 break;
724 }
725 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
726 &screen->m2mf);
727 if (ret)
728 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
729
730 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
731 PUSH_DATA (push, screen->m2mf->oclass);
732 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
733 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
734 PUSH_DATA (push, 0xa0b5);
735 }
736
737 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
738 &screen->eng2d);
739 if (ret)
740 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
741
742 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
743 PUSH_DATA (push, screen->eng2d->oclass);
744 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
745 PUSH_DATA (push, 0);
746 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
747 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
748 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
749 PUSH_DATA (push, 0);
750 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
751 PUSH_DATA (push, 0);
752 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
753 PUSH_DATA (push, 0x3f);
754 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
755 PUSH_DATA (push, 1);
756 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
757 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
758
759 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
760 PUSH_DATAh(push, screen->fence.bo->offset + 16);
761 PUSH_DATA (push, screen->fence.bo->offset + 16);
762
763 switch (dev->chipset & ~0xf) {
764 case 0x110:
765 obj_class = GM107_3D_CLASS;
766 break;
767 case 0x100:
768 case 0xf0:
769 obj_class = NVF0_3D_CLASS;
770 break;
771 case 0xe0:
772 switch (dev->chipset) {
773 case 0xea:
774 obj_class = NVEA_3D_CLASS;
775 break;
776 default:
777 obj_class = NVE4_3D_CLASS;
778 break;
779 }
780 break;
781 case 0xd0:
782 obj_class = NVC8_3D_CLASS;
783 break;
784 case 0xc0:
785 default:
786 switch (dev->chipset) {
787 case 0xc8:
788 obj_class = NVC8_3D_CLASS;
789 break;
790 case 0xc1:
791 obj_class = NVC1_3D_CLASS;
792 break;
793 default:
794 obj_class = NVC0_3D_CLASS;
795 break;
796 }
797 break;
798 }
799 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
800 &screen->eng3d);
801 if (ret)
802 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
803 screen->base.class_3d = obj_class;
804
805 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
806 PUSH_DATA (push, screen->eng3d->oclass);
807
808 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
809 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
810
811 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
812 /* kill shaders after about 1 second (at 100 MHz) */
813 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
814 PUSH_DATA (push, 0x17);
815 }
816
817 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
818 screen->base.drm->version >= 0x01000101);
819 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
820 for (i = 0; i < 8; ++i)
821 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
822
823 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
824 PUSH_DATA (push, 1);
825
826 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
827 PUSH_DATA (push, 0);
828 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
829 PUSH_DATA (push, 0);
830 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
831 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
832 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
833 PUSH_DATA (push, 0);
834 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
835 PUSH_DATA (push, 1);
836 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
837 PUSH_DATA (push, 1);
838 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
839 PUSH_DATA (push, 1);
840 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
841 PUSH_DATA (push, 0);
842 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
843 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
844 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
845 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
846 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
847 } else {
848 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
849 PUSH_DATA (push, 15);
850 }
851 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
852 PUSH_DATA (push, 8); /* 128 */
853 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
854 PUSH_DATA (push, 1);
855 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
856 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
857 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
858 }
859
860 nvc0_magic_3d_init(push, screen->eng3d->oclass);
861
862 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
863 &screen->text);
864 if (ret)
865 goto fail;
866
867 /* XXX: getting a page fault at the end of the code buffer every few
868 * launches, don't use the last 256 bytes to work around them - prefetch ?
869 */
870 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
871
872 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
873 &screen->uniform_bo);
874 if (ret)
875 goto fail;
876
877 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
878
879 for (i = 0; i < 5; ++i) {
880 /* TIC and TSC entries for each unit (nve4+ only) */
881 /* auxiliary constants (6 user clip planes, base instance id) */
882 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
883 PUSH_DATA (push, 512);
884 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
885 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
886 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
887 PUSH_DATA (push, (15 << 4) | 1);
888 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
889 unsigned j;
890 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
891 PUSH_DATA (push, 0);
892 for (j = 0; j < 8; ++j)
893 PUSH_DATA(push, j);
894 } else {
895 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
896 PUSH_DATA (push, 0x54);
897 }
898 }
899 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
900 PUSH_DATA (push, 0);
901
902 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
903 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
904 PUSH_DATA (push, 256);
905 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
906 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
907 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
908 PUSH_DATA (push, 0);
909 PUSH_DATAf(push, 0.0f);
910 PUSH_DATAf(push, 0.0f);
911 PUSH_DATAf(push, 0.0f);
912 PUSH_DATAf(push, 0.0f);
913 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
914 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
915 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
916
917 if (screen->base.drm->version >= 0x01000101) {
918 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
919 if (ret) {
920 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
921 goto fail;
922 }
923 } else {
924 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
925 value = (8 << 8) | 4;
926 else
927 value = (16 << 8) | 4;
928 }
929 screen->gpc_count = value & 0x000000ff;
930 screen->mp_count = value >> 8;
931 screen->mp_count_compute = screen->mp_count;
932
933 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
934
935 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
936 PUSH_DATAh(push, screen->text->offset);
937 PUSH_DATA (push, screen->text->offset);
938 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
939 PUSH_DATAh(push, screen->tls->offset);
940 PUSH_DATA (push, screen->tls->offset);
941 PUSH_DATA (push, screen->tls->size >> 32);
942 PUSH_DATA (push, screen->tls->size);
943 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
944 PUSH_DATA (push, 0);
945 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
946 PUSH_DATA (push, 0);
947
948 if (screen->eng3d->oclass < GM107_3D_CLASS) {
949 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
950 &screen->poly_cache);
951 if (ret)
952 goto fail;
953
954 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
955 PUSH_DATAh(push, screen->poly_cache->offset);
956 PUSH_DATA (push, screen->poly_cache->offset);
957 PUSH_DATA (push, 3);
958 }
959
960 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
961 &screen->txc);
962 if (ret)
963 goto fail;
964
965 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
966 PUSH_DATAh(push, screen->txc->offset);
967 PUSH_DATA (push, screen->txc->offset);
968 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
969
970 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
971 PUSH_DATAh(push, screen->txc->offset + 65536);
972 PUSH_DATA (push, screen->txc->offset + 65536);
973 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
974
975 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
976 PUSH_DATA (push, 0);
977 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
978 PUSH_DATA (push, 0);
979 PUSH_DATA (push, 0);
980 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
981 PUSH_DATA (push, 0x3f);
982
983 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
984 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
985 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
986 for (i = 0; i < 8 * 2; ++i)
987 PUSH_DATA(push, 0);
988 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
989 PUSH_DATA (push, 0);
990 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
991 PUSH_DATA (push, 0);
992
993 /* neither scissors, viewport nor stencil mask should affect clears */
994 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
995 PUSH_DATA (push, 0);
996
997 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
998 PUSH_DATA (push, 1);
999 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1000 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1001 PUSH_DATAf(push, 0.0f);
1002 PUSH_DATAf(push, 1.0f);
1003 }
1004 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1005 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1006
1007 /* We use scissors instead of exact view volume clipping,
1008 * so they're always enabled.
1009 */
1010 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1011 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1012 PUSH_DATA (push, 1);
1013 PUSH_DATA (push, 8192 << 16);
1014 PUSH_DATA (push, 8192 << 16);
1015 }
1016
1017 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1018
1019 i = 0;
1020 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1021 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1022 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1023 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1024 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1025 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1026 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1027 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1028 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1029
1030 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1031 PUSH_DATA (push, 1);
1032 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1033 PUSH_DATA (push, 1);
1034 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1035 PUSH_DATA (push, 0x40);
1036 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1037 PUSH_DATA (push, 0);
1038 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1039 PUSH_DATA (push, 0x30);
1040 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1041 PUSH_DATA (push, 3);
1042 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1043 PUSH_DATA (push, 0x20);
1044 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1045 PUSH_DATA (push, 0x00);
1046 screen->save_state.patch_vertices = 3;
1047
1048 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1049 PUSH_DATA (push, 0);
1050 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1051 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1052
1053 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1054
1055 if (nvc0_screen_init_compute(screen))
1056 goto fail;
1057
1058 PUSH_KICK (push);
1059
1060 screen->tic.entries = CALLOC(4096, sizeof(void *));
1061 screen->tsc.entries = screen->tic.entries + 2048;
1062
1063 if (!nvc0_blitter_create(screen))
1064 goto fail;
1065
1066 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1067
1068 return &screen->base;
1069
1070 fail:
1071 screen->base.base.context_create = NULL;
1072 return &screen->base;
1073 }
1074
1075 int
1076 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1077 {
1078 int i = screen->tic.next;
1079
1080 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1081 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1082
1083 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1084
1085 if (screen->tic.entries[i])
1086 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1087
1088 screen->tic.entries[i] = entry;
1089 return i;
1090 }
1091
1092 int
1093 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1094 {
1095 int i = screen->tsc.next;
1096
1097 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1098 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1099
1100 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1101
1102 if (screen->tsc.entries[i])
1103 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1104
1105 screen->tsc.entries[i] = entry;
1106 return i;
1107 }