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gallium: add support for programmable sample locations
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/mme/com9097.mme.h"
36 #include "nvc0/mme/com90c0.mme.h"
37
38 #include "nv50/g80_texture.xml.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 const struct util_format_description *desc = util_format_description(format);
48
49 if (sample_count > 8)
50 return false;
51 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
52 return false;
53
54 /* Short-circuit the rest of the logic -- this is used by the state tracker
55 * to determine valid MS levels in a no-attachments scenario.
56 */
57 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
58 return true;
59
60 if (!util_format_is_supported(format, bindings))
61 return false;
62
63 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
64 if (util_format_get_blocksizebits(format) == 3 * 32)
65 return false;
66
67 if (bindings & PIPE_BIND_LINEAR)
68 if (util_format_is_depth_or_stencil(format) ||
69 (target != PIPE_TEXTURE_1D &&
70 target != PIPE_TEXTURE_2D &&
71 target != PIPE_TEXTURE_RECT) ||
72 sample_count > 1)
73 return false;
74
75 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
76 */
77 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
78 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
79 /* The claim is that this should work on GM107 but it doesn't. Need to
80 * test further and figure out if it's a nouveau issue or a HW one.
81 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
82 */
83 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
84 return false;
85
86 /* shared is always supported */
87 bindings &= ~(PIPE_BIND_LINEAR |
88 PIPE_BIND_SHARED);
89
90 if (bindings & PIPE_BIND_SHADER_IMAGE) {
91 if (sample_count > 0 &&
92 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
93 /* MS images are currently unsupported on Maxwell because they have to
94 * be handled explicitly. */
95 return false;
96 }
97
98 if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
99 nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
100 /* This should work on Fermi, but for currently unknown reasons it
101 * does not and results in breaking reads from pbos. */
102 return false;
103 }
104 }
105
106 return (( nvc0_format_table[format].usage |
107 nvc0_vertex_format[format].usage) & bindings) == bindings;
108 }
109
110 static int
111 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
112 {
113 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
114 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
115
116 switch (param) {
117 /* non-boolean caps */
118 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
119 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
120 return 15;
121 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
122 return 12;
123 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
124 return 2048;
125 case PIPE_CAP_MIN_TEXEL_OFFSET:
126 return -8;
127 case PIPE_CAP_MAX_TEXEL_OFFSET:
128 return 7;
129 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
130 return -32;
131 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
132 return 31;
133 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
134 return 128 * 1024 * 1024;
135 case PIPE_CAP_GLSL_FEATURE_LEVEL:
136 return 430;
137 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
138 return 140;
139 case PIPE_CAP_MAX_RENDER_TARGETS:
140 return 8;
141 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
142 return 1;
143 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
144 return 4;
145 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
146 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
147 return 128;
148 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
149 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
150 return 1024;
151 case PIPE_CAP_MAX_VERTEX_STREAMS:
152 return 4;
153 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
154 return 2048;
155 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
156 return 256;
157 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
158 if (class_3d < GM107_3D_CLASS)
159 return 256; /* IMAGE bindings require alignment to 256 */
160 return 16;
161 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
162 return 16;
163 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
164 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
165 case PIPE_CAP_MAX_VIEWPORTS:
166 return NVC0_MAX_VIEWPORTS;
167 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
168 return 4;
169 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
170 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
171 case PIPE_CAP_ENDIANNESS:
172 return PIPE_ENDIAN_LITTLE;
173 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
174 return 30;
175 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
176 return NVC0_MAX_WINDOW_RECTANGLES;
177 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
178 return class_3d >= GM200_3D_CLASS ? 8 : 0;
179
180 /* supported caps */
181 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
182 case PIPE_CAP_TEXTURE_SWIZZLE:
183 case PIPE_CAP_NPOT_TEXTURES:
184 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
185 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
186 case PIPE_CAP_ANISOTROPIC_FILTER:
187 case PIPE_CAP_SEAMLESS_CUBE_MAP:
188 case PIPE_CAP_CUBE_MAP_ARRAY:
189 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
190 case PIPE_CAP_TEXTURE_MULTISAMPLE:
191 case PIPE_CAP_DEPTH_CLIP_DISABLE:
192 case PIPE_CAP_POINT_SPRITE:
193 case PIPE_CAP_TGSI_TEXCOORD:
194 case PIPE_CAP_SM3:
195 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
196 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
197 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
198 case PIPE_CAP_QUERY_TIMESTAMP:
199 case PIPE_CAP_QUERY_TIME_ELAPSED:
200 case PIPE_CAP_OCCLUSION_QUERY:
201 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
202 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
203 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
204 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
205 case PIPE_CAP_INDEP_BLEND_ENABLE:
206 case PIPE_CAP_INDEP_BLEND_FUNC:
207 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
208 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
209 case PIPE_CAP_PRIMITIVE_RESTART:
210 case PIPE_CAP_TGSI_INSTANCEID:
211 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
212 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
213 case PIPE_CAP_CONDITIONAL_RENDER:
214 case PIPE_CAP_TEXTURE_BARRIER:
215 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
216 case PIPE_CAP_START_INSTANCE:
217 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
218 case PIPE_CAP_DRAW_INDIRECT:
219 case PIPE_CAP_USER_VERTEX_BUFFERS:
220 case PIPE_CAP_TEXTURE_QUERY_LOD:
221 case PIPE_CAP_SAMPLE_SHADING:
222 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
223 case PIPE_CAP_TEXTURE_GATHER_SM5:
224 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
225 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
226 case PIPE_CAP_SAMPLER_VIEW_TARGET:
227 case PIPE_CAP_CLIP_HALFZ:
228 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
229 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
230 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
231 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
232 case PIPE_CAP_DEPTH_BOUNDS_TEST:
233 case PIPE_CAP_TGSI_TXQS:
234 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
235 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
236 case PIPE_CAP_SHAREABLE_SHADERS:
237 case PIPE_CAP_CLEAR_TEXTURE:
238 case PIPE_CAP_DRAW_PARAMETERS:
239 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
240 case PIPE_CAP_MULTI_DRAW_INDIRECT:
241 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
242 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
243 case PIPE_CAP_QUERY_BUFFER_OBJECT:
244 case PIPE_CAP_INVALIDATE_BUFFER:
245 case PIPE_CAP_STRING_MARKER:
246 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
247 case PIPE_CAP_CULL_DISTANCE:
248 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
249 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
250 case PIPE_CAP_TGSI_VOTE:
251 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
252 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
253 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
254 case PIPE_CAP_DOUBLES:
255 case PIPE_CAP_INT64:
256 case PIPE_CAP_TGSI_TEX_TXF_LZ:
257 case PIPE_CAP_TGSI_CLOCK:
258 case PIPE_CAP_COMPUTE:
259 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
260 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
261 case PIPE_CAP_QUERY_SO_OVERFLOW:
262 return 1;
263 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
264 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
265 case PIPE_CAP_TGSI_FS_FBFETCH:
266 return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
267 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
268 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
269 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
270 case PIPE_CAP_POST_DEPTH_COVERAGE:
271 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
272 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
273 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
274 return class_3d >= GM200_3D_CLASS;
275 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
276 return class_3d >= GP100_3D_CLASS;
277 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
278 case PIPE_CAP_TGSI_BALLOT:
279 case PIPE_CAP_BINDLESS_TEXTURE:
280 return class_3d >= NVE4_3D_CLASS;
281
282 /* unsupported caps */
283 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
284 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
285 case PIPE_CAP_SHADER_STENCIL_EXPORT:
286 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
287 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
288 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
289 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
290 case PIPE_CAP_FAKE_SW_MSAA:
291 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
292 case PIPE_CAP_VERTEXID_NOBASE:
293 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
294 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
295 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
296 case PIPE_CAP_GENERATE_MIPMAP:
297 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
298 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
299 case PIPE_CAP_QUERY_MEMORY_INFO:
300 case PIPE_CAP_PCI_GROUP:
301 case PIPE_CAP_PCI_BUS:
302 case PIPE_CAP_PCI_DEVICE:
303 case PIPE_CAP_PCI_FUNCTION:
304 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
305 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
306 case PIPE_CAP_NATIVE_FENCE_FD:
307 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
308 case PIPE_CAP_INT64_DIVMOD:
309 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
310 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
311 case PIPE_CAP_MEMOBJ:
312 case PIPE_CAP_LOAD_CONSTBUF:
313 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
314 case PIPE_CAP_TILE_RASTER_ORDER:
315 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
316 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
317 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
318 case PIPE_CAP_FENCE_SIGNAL:
319 case PIPE_CAP_CONSTBUF0_FLAGS:
320 case PIPE_CAP_PACKED_UNIFORMS:
321 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
322 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
323 return 0;
324
325 case PIPE_CAP_VENDOR_ID:
326 return 0x10de;
327 case PIPE_CAP_DEVICE_ID: {
328 uint64_t device_id;
329 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
330 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
331 return -1;
332 }
333 return device_id;
334 }
335 case PIPE_CAP_ACCELERATED:
336 return 1;
337 case PIPE_CAP_VIDEO_MEMORY:
338 return dev->vram_size >> 20;
339 case PIPE_CAP_UMA:
340 return 0;
341 }
342
343 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
344 return 0;
345 }
346
347 static int
348 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
349 enum pipe_shader_type shader,
350 enum pipe_shader_cap param)
351 {
352 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
353
354 switch (shader) {
355 case PIPE_SHADER_VERTEX:
356 case PIPE_SHADER_GEOMETRY:
357 case PIPE_SHADER_FRAGMENT:
358 case PIPE_SHADER_COMPUTE:
359 case PIPE_SHADER_TESS_CTRL:
360 case PIPE_SHADER_TESS_EVAL:
361 break;
362 default:
363 return 0;
364 }
365
366 switch (param) {
367 case PIPE_SHADER_CAP_PREFERRED_IR:
368 return PIPE_SHADER_IR_TGSI;
369 case PIPE_SHADER_CAP_SUPPORTED_IRS:
370 return 1 << PIPE_SHADER_IR_TGSI;
371 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
372 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
373 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
374 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
375 return 16384;
376 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
377 return 16;
378 case PIPE_SHADER_CAP_MAX_INPUTS:
379 if (shader == PIPE_SHADER_VERTEX)
380 return 32;
381 /* NOTE: These only count our slots for GENERIC varyings.
382 * The address space may be larger, but the actual hard limit seems to be
383 * less than what the address space layout permits, so don't add TEXCOORD,
384 * COLOR, etc. here.
385 */
386 if (shader == PIPE_SHADER_FRAGMENT)
387 return 0x1f0 / 16;
388 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
389 * and excludes 0x60 per-patch inputs.
390 */
391 return 0x200 / 16;
392 case PIPE_SHADER_CAP_MAX_OUTPUTS:
393 return 32;
394 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
395 return 65536;
396 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
397 return NVC0_MAX_PIPE_CONSTBUFS;
398 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
399 return shader != PIPE_SHADER_FRAGMENT;
400 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
401 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
402 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
403 return 1;
404 case PIPE_SHADER_CAP_MAX_TEMPS:
405 return NVC0_CAP_MAX_PROGRAM_TEMPS;
406 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
407 return 1;
408 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
409 return 1;
410 case PIPE_SHADER_CAP_SUBROUTINES:
411 return 1;
412 case PIPE_SHADER_CAP_INTEGERS:
413 return 1;
414 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
415 return 1;
416 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
417 return 1;
418 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
419 return 1;
420 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
421 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
422 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
423 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
424 case PIPE_SHADER_CAP_INT64_ATOMICS:
425 case PIPE_SHADER_CAP_FP16:
426 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
427 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
428 return 0;
429 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
430 return NVC0_MAX_BUFFERS;
431 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
432 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
433 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
434 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
435 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
436 return 32;
437 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
438 if (class_3d >= NVE4_3D_CLASS)
439 return NVC0_MAX_IMAGES;
440 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
441 return NVC0_MAX_IMAGES;
442 return 0;
443 default:
444 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
445 return 0;
446 }
447 }
448
449 static float
450 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
451 {
452 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
453
454 switch (param) {
455 case PIPE_CAPF_MAX_LINE_WIDTH:
456 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
457 return 10.0f;
458 case PIPE_CAPF_MAX_POINT_WIDTH:
459 return 63.0f;
460 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
461 return 63.375f;
462 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
463 return 16.0f;
464 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
465 return 15.0f;
466 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
467 return 0.0f;
468 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
469 return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
470 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
471 return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
472 }
473
474 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
475 return 0.0f;
476 }
477
478 static int
479 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
480 enum pipe_shader_ir ir_type,
481 enum pipe_compute_cap param, void *data)
482 {
483 struct nvc0_screen *screen = nvc0_screen(pscreen);
484 const uint16_t obj_class = screen->compute->oclass;
485
486 #define RET(x) do { \
487 if (data) \
488 memcpy(data, x, sizeof(x)); \
489 return sizeof(x); \
490 } while (0)
491
492 switch (param) {
493 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
494 RET((uint64_t []) { 3 });
495 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
496 if (obj_class >= NVE4_COMPUTE_CLASS) {
497 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
498 } else {
499 RET(((uint64_t []) { 65535, 65535, 65535 }));
500 }
501 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
502 RET(((uint64_t []) { 1024, 1024, 64 }));
503 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
504 RET((uint64_t []) { 1024 });
505 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
506 if (obj_class >= NVE4_COMPUTE_CLASS) {
507 RET((uint64_t []) { 1024 });
508 } else {
509 RET((uint64_t []) { 512 });
510 }
511 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
512 RET((uint64_t []) { 1ULL << 40 });
513 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
514 switch (obj_class) {
515 case GM200_COMPUTE_CLASS:
516 RET((uint64_t []) { 96 << 10 });
517 break;
518 case GM107_COMPUTE_CLASS:
519 RET((uint64_t []) { 64 << 10 });
520 break;
521 default:
522 RET((uint64_t []) { 48 << 10 });
523 break;
524 }
525 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
526 RET((uint64_t []) { 512 << 10 });
527 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
528 RET((uint64_t []) { 4096 });
529 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
530 RET((uint32_t []) { 32 });
531 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
532 RET((uint64_t []) { 1ULL << 40 });
533 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
534 RET((uint32_t []) { 0 });
535 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
536 RET((uint32_t []) { screen->mp_count_compute });
537 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
538 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
539 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
540 RET((uint32_t []) { 64 });
541 default:
542 return 0;
543 }
544
545 #undef RET
546 }
547
548 static void
549 nvc0_screen_destroy(struct pipe_screen *pscreen)
550 {
551 struct nvc0_screen *screen = nvc0_screen(pscreen);
552
553 if (!nouveau_drm_screen_unref(&screen->base))
554 return;
555
556 if (screen->base.fence.current) {
557 struct nouveau_fence *current = NULL;
558
559 /* nouveau_fence_wait will create a new current fence, so wait on the
560 * _current_ one, and remove both.
561 */
562 nouveau_fence_ref(screen->base.fence.current, &current);
563 nouveau_fence_wait(current, NULL);
564 nouveau_fence_ref(NULL, &current);
565 nouveau_fence_ref(NULL, &screen->base.fence.current);
566 }
567 if (screen->base.pushbuf)
568 screen->base.pushbuf->user_priv = NULL;
569
570 if (screen->blitter)
571 nvc0_blitter_destroy(screen);
572 if (screen->pm.prog) {
573 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
574 nvc0_program_destroy(NULL, screen->pm.prog);
575 FREE(screen->pm.prog);
576 }
577
578 nouveau_bo_ref(NULL, &screen->text);
579 nouveau_bo_ref(NULL, &screen->uniform_bo);
580 nouveau_bo_ref(NULL, &screen->tls);
581 nouveau_bo_ref(NULL, &screen->txc);
582 nouveau_bo_ref(NULL, &screen->fence.bo);
583 nouveau_bo_ref(NULL, &screen->poly_cache);
584
585 nouveau_heap_destroy(&screen->lib_code);
586 nouveau_heap_destroy(&screen->text_heap);
587
588 FREE(screen->default_tsc);
589 FREE(screen->tic.entries);
590
591 nouveau_object_del(&screen->eng3d);
592 nouveau_object_del(&screen->eng2d);
593 nouveau_object_del(&screen->m2mf);
594 nouveau_object_del(&screen->compute);
595 nouveau_object_del(&screen->nvsw);
596
597 nouveau_screen_fini(&screen->base);
598
599 FREE(screen);
600 }
601
602 static int
603 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
604 unsigned size, const uint32_t *data)
605 {
606 struct nouveau_pushbuf *push = screen->base.pushbuf;
607
608 size /= 4;
609
610 assert((pos + size) <= 0x800);
611
612 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
613 PUSH_DATA (push, (m - 0x3800) / 8);
614 PUSH_DATA (push, pos);
615 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
616 PUSH_DATA (push, pos);
617 PUSH_DATAp(push, data, size);
618
619 return pos + size;
620 }
621
622 static void
623 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
624 {
625 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
626 PUSH_DATA (push, 0xff);
627 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
628 PUSH_DATA (push, 0xff);
629 PUSH_DATA (push, 0xff);
630 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
631 PUSH_DATA (push, 0xff);
632 PUSH_DATA (push, 0xff);
633 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
634 PUSH_DATA (push, 0x3f);
635
636 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
637 PUSH_DATA (push, (3 << 16) | 3);
638 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
639 PUSH_DATA (push, (2 << 16) | 2);
640
641 if (obj_class < GM107_3D_CLASS) {
642 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
643 PUSH_DATA (push, 0);
644 }
645 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
646 PUSH_DATA (push, 0x10);
647 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
648 PUSH_DATA (push, 0x10);
649 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
650 PUSH_DATA (push, 0x10);
651 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
652 PUSH_DATA (push, 0x10);
653 PUSH_DATA (push, 0x10);
654 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
655 PUSH_DATA (push, 0x10);
656 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
657 PUSH_DATA (push, 0xe);
658
659 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
660 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
661 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
662 PUSH_DATA (push, 0);
663 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
664 PUSH_DATA (push, 3);
665
666 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
667 PUSH_DATA (push, 0x3fffff);
668 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
669 PUSH_DATA (push, 1);
670 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
671 PUSH_DATA (push, 1);
672
673 if (obj_class < GM107_3D_CLASS) {
674 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
675 PUSH_DATA (push, 3);
676
677 if (obj_class >= NVE4_3D_CLASS) {
678 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
679 PUSH_DATA (push, 1);
680 }
681 }
682
683 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
684 * are supposed to do */
685 }
686
687 static void
688 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
689 {
690 struct nvc0_screen *screen = nvc0_screen(pscreen);
691 struct nouveau_pushbuf *push = screen->base.pushbuf;
692
693 /* we need to do it after possible flush in MARK_RING */
694 *sequence = ++screen->base.fence.sequence;
695
696 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
697 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
698 PUSH_DATAh(push, screen->fence.bo->offset);
699 PUSH_DATA (push, screen->fence.bo->offset);
700 PUSH_DATA (push, *sequence);
701 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
702 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
703 }
704
705 static u32
706 nvc0_screen_fence_update(struct pipe_screen *pscreen)
707 {
708 struct nvc0_screen *screen = nvc0_screen(pscreen);
709 return screen->fence.map[0];
710 }
711
712 static int
713 nvc0_screen_init_compute(struct nvc0_screen *screen)
714 {
715 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
716
717 switch (screen->base.device->chipset & ~0xf) {
718 case 0xc0:
719 case 0xd0:
720 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
721 case 0xe0:
722 case 0xf0:
723 case 0x100:
724 case 0x110:
725 case 0x120:
726 case 0x130:
727 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
728 default:
729 return -1;
730 }
731 }
732
733 static int
734 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
735 uint32_t lpos, uint32_t lneg, uint32_t cstack)
736 {
737 struct nouveau_bo *bo = NULL;
738 int ret;
739 uint64_t size = (lpos + lneg) * 32 + cstack;
740
741 if (size >= (1 << 20)) {
742 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
743 return -1;
744 }
745
746 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
747 size = align(size, 0x8000);
748 size *= screen->mp_count;
749
750 size = align(size, 1 << 17);
751
752 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
753 NULL, &bo);
754 if (ret)
755 return ret;
756
757 /* Make sure that the pushbuf has acquired a reference to the old tls
758 * segment, as it may have commands that will reference it.
759 */
760 if (screen->tls)
761 PUSH_REFN(screen->base.pushbuf, screen->tls,
762 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
763 nouveau_bo_ref(NULL, &screen->tls);
764 screen->tls = bo;
765 return 0;
766 }
767
768 int
769 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
770 {
771 struct nouveau_pushbuf *push = screen->base.pushbuf;
772 struct nouveau_bo *bo;
773 int ret;
774
775 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
776 1 << 17, size, NULL, &bo);
777 if (ret)
778 return ret;
779
780 /* Make sure that the pushbuf has acquired a reference to the old text
781 * segment, as it may have commands that will reference it.
782 */
783 if (screen->text)
784 PUSH_REFN(push, screen->text,
785 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
786 nouveau_bo_ref(NULL, &screen->text);
787 screen->text = bo;
788
789 nouveau_heap_destroy(&screen->lib_code);
790 nouveau_heap_destroy(&screen->text_heap);
791
792 /* XXX: getting a page fault at the end of the code buffer every few
793 * launches, don't use the last 256 bytes to work around them - prefetch ?
794 */
795 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
796
797 /* update the code segment setup */
798 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
799 PUSH_DATAh(push, screen->text->offset);
800 PUSH_DATA (push, screen->text->offset);
801 if (screen->compute) {
802 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
803 PUSH_DATAh(push, screen->text->offset);
804 PUSH_DATA (push, screen->text->offset);
805 }
806
807 return 0;
808 }
809
810 #define FAIL_SCREEN_INIT(str, err) \
811 do { \
812 NOUVEAU_ERR(str, err); \
813 goto fail; \
814 } while(0)
815
816 struct nouveau_screen *
817 nvc0_screen_create(struct nouveau_device *dev)
818 {
819 struct nvc0_screen *screen;
820 struct pipe_screen *pscreen;
821 struct nouveau_object *chan;
822 struct nouveau_pushbuf *push;
823 uint64_t value;
824 uint32_t obj_class;
825 uint32_t flags;
826 int ret;
827 unsigned i;
828
829 switch (dev->chipset & ~0xf) {
830 case 0xc0:
831 case 0xd0:
832 case 0xe0:
833 case 0xf0:
834 case 0x100:
835 case 0x110:
836 case 0x120:
837 case 0x130:
838 break;
839 default:
840 return NULL;
841 }
842
843 screen = CALLOC_STRUCT(nvc0_screen);
844 if (!screen)
845 return NULL;
846 pscreen = &screen->base.base;
847 pscreen->destroy = nvc0_screen_destroy;
848
849 ret = nouveau_screen_init(&screen->base, dev);
850 if (ret)
851 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
852 chan = screen->base.channel;
853 push = screen->base.pushbuf;
854 push->user_priv = screen;
855 push->rsvd_kick = 5;
856
857 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
858 PIPE_BIND_SHADER_BUFFER |
859 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
860 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
861 screen->base.sysmem_bindings |=
862 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
863
864 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
865 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
866 screen->base.vidmem_bindings = 0;
867 }
868
869 pscreen->context_create = nvc0_create;
870 pscreen->is_format_supported = nvc0_screen_is_format_supported;
871 pscreen->get_param = nvc0_screen_get_param;
872 pscreen->get_shader_param = nvc0_screen_get_shader_param;
873 pscreen->get_paramf = nvc0_screen_get_paramf;
874 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
875 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
876
877 nvc0_screen_init_resource_functions(pscreen);
878
879 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
880 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
881
882 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
883 if (screen->base.drm->version >= 0x01000202)
884 flags |= NOUVEAU_BO_COHERENT;
885
886 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
887 if (ret)
888 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
889 nouveau_bo_map(screen->fence.bo, 0, NULL);
890 screen->fence.map = screen->fence.bo->map;
891 screen->base.fence.emit = nvc0_screen_fence_emit;
892 screen->base.fence.update = nvc0_screen_fence_update;
893
894
895 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
896 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
897 if (ret)
898 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
899
900 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
901 PUSH_DATA (push, screen->nvsw->handle);
902
903 switch (dev->chipset & ~0xf) {
904 case 0x130:
905 case 0x120:
906 case 0x110:
907 case 0x100:
908 case 0xf0:
909 obj_class = NVF0_P2MF_CLASS;
910 break;
911 case 0xe0:
912 obj_class = NVE4_P2MF_CLASS;
913 break;
914 default:
915 obj_class = NVC0_M2MF_CLASS;
916 break;
917 }
918 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
919 &screen->m2mf);
920 if (ret)
921 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
922
923 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
924 PUSH_DATA (push, screen->m2mf->oclass);
925 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
926 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
927 PUSH_DATA (push, 0xa0b5);
928 }
929
930 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
931 &screen->eng2d);
932 if (ret)
933 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
934
935 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
936 PUSH_DATA (push, screen->eng2d->oclass);
937 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
938 PUSH_DATA (push, 0);
939 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
940 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
941 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
942 PUSH_DATA (push, 0);
943 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
944 PUSH_DATA (push, 0);
945 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
946 PUSH_DATA (push, 0x3f);
947 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
948 PUSH_DATA (push, 1);
949 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
950 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
951
952 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
953 PUSH_DATAh(push, screen->fence.bo->offset + 16);
954 PUSH_DATA (push, screen->fence.bo->offset + 16);
955
956 switch (dev->chipset & ~0xf) {
957 case 0x130:
958 switch (dev->chipset) {
959 case 0x130:
960 case 0x13b:
961 obj_class = GP100_3D_CLASS;
962 break;
963 default:
964 obj_class = GP102_3D_CLASS;
965 break;
966 }
967 break;
968 case 0x120:
969 obj_class = GM200_3D_CLASS;
970 break;
971 case 0x110:
972 obj_class = GM107_3D_CLASS;
973 break;
974 case 0x100:
975 case 0xf0:
976 obj_class = NVF0_3D_CLASS;
977 break;
978 case 0xe0:
979 switch (dev->chipset) {
980 case 0xea:
981 obj_class = NVEA_3D_CLASS;
982 break;
983 default:
984 obj_class = NVE4_3D_CLASS;
985 break;
986 }
987 break;
988 case 0xd0:
989 obj_class = NVC8_3D_CLASS;
990 break;
991 case 0xc0:
992 default:
993 switch (dev->chipset) {
994 case 0xc8:
995 obj_class = NVC8_3D_CLASS;
996 break;
997 case 0xc1:
998 obj_class = NVC1_3D_CLASS;
999 break;
1000 default:
1001 obj_class = NVC0_3D_CLASS;
1002 break;
1003 }
1004 break;
1005 }
1006 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1007 &screen->eng3d);
1008 if (ret)
1009 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1010 screen->base.class_3d = obj_class;
1011
1012 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1013 PUSH_DATA (push, screen->eng3d->oclass);
1014
1015 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1016 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1017
1018 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1019 /* kill shaders after about 1 second (at 100 MHz) */
1020 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1021 PUSH_DATA (push, 0x17);
1022 }
1023
1024 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1025 screen->base.drm->version >= 0x01000101);
1026 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1027 for (i = 0; i < 8; ++i)
1028 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1029
1030 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1031 PUSH_DATA (push, 1);
1032
1033 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1034 PUSH_DATA (push, 0);
1035 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1036 PUSH_DATA (push, 0);
1037 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1038 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1039 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1040 PUSH_DATA (push, 0);
1041 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1042 PUSH_DATA (push, 1);
1043 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1044 PUSH_DATA (push, 1);
1045 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1046 PUSH_DATA (push, 1);
1047 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1048 PUSH_DATA (push, 0);
1049 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1050 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1051 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1052 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1053 } else {
1054 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1055 PUSH_DATA (push, 15);
1056 }
1057 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1058 PUSH_DATA (push, 8); /* 128 */
1059 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1060 PUSH_DATA (push, 1);
1061 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1062 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1063 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1064 }
1065
1066 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1067
1068 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1069 if (ret)
1070 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1071
1072 /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1073 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1074 &screen->uniform_bo);
1075 if (ret)
1076 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1077
1078 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1079
1080 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1081 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1082 PUSH_DATA (push, 256);
1083 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1084 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1085 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1086 PUSH_DATA (push, 0);
1087 PUSH_DATAf(push, 0.0f);
1088 PUSH_DATAf(push, 0.0f);
1089 PUSH_DATAf(push, 0.0f);
1090 PUSH_DATAf(push, 0.0f);
1091 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1092 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1093 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1094
1095 if (screen->base.drm->version >= 0x01000101) {
1096 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1097 if (ret)
1098 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1099 } else {
1100 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1101 value = (8 << 8) | 4;
1102 else
1103 value = (16 << 8) | 4;
1104 }
1105 screen->gpc_count = value & 0x000000ff;
1106 screen->mp_count = value >> 8;
1107 screen->mp_count_compute = screen->mp_count;
1108
1109 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1110 if (ret)
1111 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1112
1113 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1114 PUSH_DATAh(push, screen->tls->offset);
1115 PUSH_DATA (push, screen->tls->offset);
1116 PUSH_DATA (push, screen->tls->size >> 32);
1117 PUSH_DATA (push, screen->tls->size);
1118 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1119 PUSH_DATA (push, 0);
1120 /* Reduce likelihood of collision with real buffers by placing the hole at
1121 * the top of the 4G area. This will have to be dealt with for real
1122 * eventually by blocking off that area from the VM.
1123 */
1124 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1125 PUSH_DATA (push, 0xff << 24);
1126
1127 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1128 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1129 &screen->poly_cache);
1130 if (ret)
1131 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1132
1133 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1134 PUSH_DATAh(push, screen->poly_cache->offset);
1135 PUSH_DATA (push, screen->poly_cache->offset);
1136 PUSH_DATA (push, 3);
1137 }
1138
1139 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1140 &screen->txc);
1141 if (ret)
1142 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1143
1144 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1145 PUSH_DATAh(push, screen->txc->offset);
1146 PUSH_DATA (push, screen->txc->offset);
1147 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1148 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1149 screen->tic.maxwell = true;
1150 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1151 screen->tic.maxwell =
1152 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1153 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1154 }
1155 }
1156
1157 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1158 PUSH_DATAh(push, screen->txc->offset + 65536);
1159 PUSH_DATA (push, screen->txc->offset + 65536);
1160 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1161
1162 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1163 PUSH_DATA (push, 0);
1164 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1165 PUSH_DATA (push, 0);
1166 PUSH_DATA (push, 0);
1167 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1168 PUSH_DATA (push, 0x3f);
1169
1170 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1171 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1172 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1173 for (i = 0; i < 8 * 2; ++i)
1174 PUSH_DATA(push, 0);
1175 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1176 PUSH_DATA (push, 0);
1177 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1178 PUSH_DATA (push, 0);
1179
1180 /* neither scissors, viewport nor stencil mask should affect clears */
1181 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1182 PUSH_DATA (push, 0);
1183
1184 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1185 PUSH_DATA (push, 1);
1186 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1187 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1188 PUSH_DATAf(push, 0.0f);
1189 PUSH_DATAf(push, 1.0f);
1190 }
1191 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1192 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1193
1194 /* We use scissors instead of exact view volume clipping,
1195 * so they're always enabled.
1196 */
1197 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1198 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1199 PUSH_DATA (push, 1);
1200 PUSH_DATA (push, 8192 << 16);
1201 PUSH_DATA (push, 8192 << 16);
1202 }
1203
1204 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1205
1206 i = 0;
1207 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1208 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1209 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1210 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1211 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1212 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1213 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1214 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1215 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1216 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1217 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1218 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1219 MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1220 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1221
1222 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1223 PUSH_DATA (push, 1);
1224 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1225 PUSH_DATA (push, 1);
1226 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1227 PUSH_DATA (push, 0x40);
1228 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1229 PUSH_DATA (push, 0);
1230 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1231 PUSH_DATA (push, 0x30);
1232 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1233 PUSH_DATA (push, 3);
1234 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1235 PUSH_DATA (push, 0x20);
1236 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1237 PUSH_DATA (push, 0x00);
1238 screen->save_state.patch_vertices = 3;
1239
1240 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1241 PUSH_DATA (push, 0);
1242 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1243 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1244
1245 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1246
1247 if (nvc0_screen_init_compute(screen))
1248 goto fail;
1249
1250 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1251 for (i = 0; i < 5; ++i) {
1252 /* TIC and TSC entries for each unit (nve4+ only) */
1253 /* auxiliary constants (6 user clip planes, base instance id) */
1254 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1255 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1256 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1257 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1258 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1259 PUSH_DATA (push, (15 << 4) | 1);
1260 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1261 unsigned j;
1262 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1263 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1264 for (j = 0; j < 8; ++j)
1265 PUSH_DATA(push, j);
1266 } else {
1267 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1268 PUSH_DATA (push, 0x54);
1269 }
1270
1271 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1272 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1273 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1274 PUSH_DATA (push, 0); /* 0 */
1275 PUSH_DATA (push, 0);
1276 PUSH_DATA (push, 1); /* 1 */
1277 PUSH_DATA (push, 0);
1278 PUSH_DATA (push, 0); /* 2 */
1279 PUSH_DATA (push, 1);
1280 PUSH_DATA (push, 1); /* 3 */
1281 PUSH_DATA (push, 1);
1282 PUSH_DATA (push, 2); /* 4 */
1283 PUSH_DATA (push, 0);
1284 PUSH_DATA (push, 3); /* 5 */
1285 PUSH_DATA (push, 0);
1286 PUSH_DATA (push, 2); /* 6 */
1287 PUSH_DATA (push, 1);
1288 PUSH_DATA (push, 3); /* 7 */
1289 PUSH_DATA (push, 1);
1290 }
1291 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1292 PUSH_DATA (push, 0);
1293
1294 PUSH_KICK (push);
1295
1296 screen->tic.entries = CALLOC(
1297 NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1298 sizeof(void *));
1299 screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1300 screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1301
1302 if (!nvc0_blitter_create(screen))
1303 goto fail;
1304
1305 screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1306 screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1307
1308 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1309
1310 return &screen->base;
1311
1312 fail:
1313 screen->base.base.context_create = NULL;
1314 return &screen->base;
1315 }
1316
1317 int
1318 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1319 {
1320 int i = screen->tic.next;
1321
1322 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1323 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1324
1325 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1326
1327 if (screen->tic.entries[i])
1328 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1329
1330 screen->tic.entries[i] = entry;
1331 return i;
1332 }
1333
1334 int
1335 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1336 {
1337 int i = screen->tsc.next;
1338
1339 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1340 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1341
1342 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1343
1344 if (screen->tsc.entries[i])
1345 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1346
1347 screen->tsc.entries[i] = entry;
1348 return i;
1349 }