2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <nouveau_drm.h>
25 #include "util/u_format.h"
26 #include "util/u_format_s3tc.h"
27 #include "pipe/p_screen.h"
29 #include "vl/vl_decoder.h"
30 #include "vl/vl_video_buffer.h"
32 #include "nouveau_vp3_video.h"
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_screen.h"
37 #include "nvc0/mme/com9097.mme.h"
40 nvc0_screen_is_format_supported(struct pipe_screen
*pscreen
,
41 enum pipe_format format
,
42 enum pipe_texture_target target
,
43 unsigned sample_count
,
48 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
51 if (!util_format_is_supported(format
, bindings
))
54 if ((bindings
& PIPE_BIND_SAMPLER_VIEW
) && (target
!= PIPE_BUFFER
))
55 if (util_format_get_blocksizebits(format
) == 3 * 32)
58 /* transfers & shared are always supported */
59 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
60 PIPE_BIND_TRANSFER_WRITE
|
63 return (nvc0_format_table
[format
].usage
& bindings
) == bindings
;
67 nvc0_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
69 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
70 struct nouveau_device
*dev
= nouveau_screen(pscreen
)->device
;
73 /* non-boolean caps */
74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
78 return (class_3d
>= NVE4_3D_CLASS
) ? 13 : 12;
79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
81 case PIPE_CAP_MIN_TEXEL_OFFSET
:
83 case PIPE_CAP_MAX_TEXEL_OFFSET
:
85 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
87 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
89 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
91 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
93 case PIPE_CAP_MAX_RENDER_TARGETS
:
95 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
97 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
99 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
100 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
102 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
103 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
105 case PIPE_CAP_MAX_VERTEX_STREAMS
:
107 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
109 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
111 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
112 return 1; /* 256 for binding as RT, but that's not possible in GL */
113 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
114 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
115 case PIPE_CAP_MAX_VIEWPORTS
:
116 return NVC0_MAX_VIEWPORTS
;
117 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
119 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
120 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50
;
121 case PIPE_CAP_ENDIANNESS
:
122 return PIPE_ENDIAN_LITTLE
;
125 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
126 case PIPE_CAP_TEXTURE_SWIZZLE
:
127 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
128 case PIPE_CAP_NPOT_TEXTURES
:
129 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
130 case PIPE_CAP_ANISOTROPIC_FILTER
:
131 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
132 case PIPE_CAP_CUBE_MAP_ARRAY
:
133 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
134 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
135 case PIPE_CAP_TWO_SIDED_STENCIL
:
136 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
137 case PIPE_CAP_POINT_SPRITE
:
138 case PIPE_CAP_TGSI_TEXCOORD
:
140 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
141 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
142 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
143 case PIPE_CAP_QUERY_TIMESTAMP
:
144 case PIPE_CAP_QUERY_TIME_ELAPSED
:
145 case PIPE_CAP_OCCLUSION_QUERY
:
146 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
147 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
148 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
149 case PIPE_CAP_INDEP_BLEND_ENABLE
:
150 case PIPE_CAP_INDEP_BLEND_FUNC
:
151 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
152 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
153 case PIPE_CAP_PRIMITIVE_RESTART
:
154 case PIPE_CAP_TGSI_INSTANCEID
:
155 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
156 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
157 case PIPE_CAP_CONDITIONAL_RENDER
:
158 case PIPE_CAP_TEXTURE_BARRIER
:
159 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
160 case PIPE_CAP_START_INSTANCE
:
161 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
162 case PIPE_CAP_DRAW_INDIRECT
:
163 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
164 case PIPE_CAP_USER_INDEX_BUFFERS
:
165 case PIPE_CAP_USER_VERTEX_BUFFERS
:
166 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
167 case PIPE_CAP_TEXTURE_QUERY_LOD
:
168 case PIPE_CAP_SAMPLE_SHADING
:
169 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
170 case PIPE_CAP_TEXTURE_GATHER_SM5
:
171 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
172 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
173 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
175 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
176 return (class_3d
>= NVE4_3D_CLASS
) ? 1 : 0;
177 case PIPE_CAP_COMPUTE
:
178 return (class_3d
== NVE4_3D_CLASS
) ? 1 : 0;
180 /* unsupported caps */
181 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
182 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
183 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
184 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
185 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
186 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
187 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
188 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
189 case PIPE_CAP_FAKE_SW_MSAA
:
190 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
191 case PIPE_CAP_CLIP_HALFZ
:
194 case PIPE_CAP_VENDOR_ID
:
196 case PIPE_CAP_DEVICE_ID
: {
198 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
199 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
204 case PIPE_CAP_ACCELERATED
:
206 case PIPE_CAP_VIDEO_MEMORY
:
207 return dev
->vram_size
>> 20;
212 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
217 nvc0_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
218 enum pipe_shader_cap param
)
220 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
223 case PIPE_SHADER_VERTEX
:
225 case PIPE_SHADER_TESSELLATION_CONTROL:
226 case PIPE_SHADER_TESSELLATION_EVALUATION:
228 case PIPE_SHADER_GEOMETRY
:
229 case PIPE_SHADER_FRAGMENT
:
231 case PIPE_SHADER_COMPUTE
:
232 if (class_3d
!= NVE4_3D_CLASS
)
240 case PIPE_SHADER_CAP_PREFERRED_IR
:
241 return PIPE_SHADER_IR_TGSI
;
242 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
243 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
244 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
245 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
247 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
249 case PIPE_SHADER_CAP_MAX_INPUTS
:
250 if (shader
== PIPE_SHADER_VERTEX
)
252 /* NOTE: These only count our slots for GENERIC varyings.
253 * The address space may be larger, but the actual hard limit seems to be
254 * less than what the address space layout permits, so don't add TEXCOORD,
257 if (shader
== PIPE_SHADER_FRAGMENT
)
259 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
260 * and excludes 0x60 per-patch inputs.
263 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
265 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
267 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
268 if (shader
== PIPE_SHADER_COMPUTE
&& class_3d
>= NVE4_3D_CLASS
)
269 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE
;
270 return NVC0_MAX_PIPE_CONSTBUFS
;
271 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
272 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
273 return shader
!= PIPE_SHADER_FRAGMENT
;
274 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
275 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
277 case PIPE_SHADER_CAP_MAX_PREDS
:
279 case PIPE_SHADER_CAP_MAX_TEMPS
:
280 return NVC0_CAP_MAX_PROGRAM_TEMPS
;
281 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
283 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
285 case PIPE_SHADER_CAP_SUBROUTINES
:
287 case PIPE_SHADER_CAP_INTEGERS
:
289 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
290 return 16; /* would be 32 in linked (OpenGL-style) mode */
291 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
292 return 16; /* XXX not sure if more are really safe */
294 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
300 nvc0_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
303 case PIPE_CAPF_MAX_LINE_WIDTH
:
304 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
306 case PIPE_CAPF_MAX_POINT_WIDTH
:
308 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
310 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
312 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
314 case PIPE_CAPF_GUARD_BAND_LEFT
:
315 case PIPE_CAPF_GUARD_BAND_TOP
:
317 case PIPE_CAPF_GUARD_BAND_RIGHT
:
318 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
319 return 0.0f
; /* that or infinity */
322 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param
);
327 nvc0_screen_get_compute_param(struct pipe_screen
*pscreen
,
328 enum pipe_compute_cap param
, void *data
)
330 uint64_t *data64
= (uint64_t *)data
;
331 const uint16_t obj_class
= nvc0_screen(pscreen
)->compute
->oclass
;
334 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
337 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
338 data64
[0] = (obj_class
>= NVE4_COMPUTE_CLASS
) ? 0x7fffffff : 65535;
342 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
347 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
350 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
: /* g[] */
351 data64
[0] = (uint64_t)1 << 40;
353 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
: /* s[] */
354 data64
[0] = 48 << 10;
356 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
: /* l[] */
357 data64
[0] = 512 << 10;
359 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
: /* c[], arbitrary limit */
368 nvc0_screen_destroy(struct pipe_screen
*pscreen
)
370 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
372 if (!nouveau_drm_screen_unref(&screen
->base
))
375 if (screen
->base
.fence
.current
) {
376 struct nouveau_fence
*current
= NULL
;
378 /* nouveau_fence_wait will create a new current fence, so wait on the
379 * _current_ one, and remove both.
381 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
382 nouveau_fence_wait(current
);
383 nouveau_fence_ref(NULL
, ¤t
);
384 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
386 if (screen
->base
.pushbuf
)
387 screen
->base
.pushbuf
->user_priv
= NULL
;
390 nvc0_blitter_destroy(screen
);
391 if (screen
->pm
.prog
) {
392 screen
->pm
.prog
->code
= NULL
; /* hardcoded, don't FREE */
393 nvc0_program_destroy(NULL
, screen
->pm
.prog
);
396 nouveau_bo_ref(NULL
, &screen
->text
);
397 nouveau_bo_ref(NULL
, &screen
->uniform_bo
);
398 nouveau_bo_ref(NULL
, &screen
->tls
);
399 nouveau_bo_ref(NULL
, &screen
->txc
);
400 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
401 nouveau_bo_ref(NULL
, &screen
->poly_cache
);
402 nouveau_bo_ref(NULL
, &screen
->parm
);
404 nouveau_heap_destroy(&screen
->lib_code
);
405 nouveau_heap_destroy(&screen
->text_heap
);
407 FREE(screen
->tic
.entries
);
409 nouveau_mm_destroy(screen
->mm_VRAM_fe0
);
411 nouveau_object_del(&screen
->eng3d
);
412 nouveau_object_del(&screen
->eng2d
);
413 nouveau_object_del(&screen
->m2mf
);
414 nouveau_object_del(&screen
->compute
);
415 nouveau_object_del(&screen
->nvsw
);
417 nouveau_screen_fini(&screen
->base
);
423 nvc0_graph_set_macro(struct nvc0_screen
*screen
, uint32_t m
, unsigned pos
,
424 unsigned size
, const uint32_t *data
)
426 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
430 assert((pos
+ size
) <= 0x800);
432 BEGIN_NVC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_ID
), 2);
433 PUSH_DATA (push
, (m
- 0x3800) / 8);
434 PUSH_DATA (push
, pos
);
435 BEGIN_1IC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS
), size
+ 1);
436 PUSH_DATA (push
, pos
);
437 PUSH_DATAp(push
, data
, size
);
443 nvc0_magic_3d_init(struct nouveau_pushbuf
*push
, uint16_t obj_class
)
445 BEGIN_NVC0(push
, SUBC_3D(0x10cc), 1);
446 PUSH_DATA (push
, 0xff);
447 BEGIN_NVC0(push
, SUBC_3D(0x10e0), 2);
448 PUSH_DATA (push
, 0xff);
449 PUSH_DATA (push
, 0xff);
450 BEGIN_NVC0(push
, SUBC_3D(0x10ec), 2);
451 PUSH_DATA (push
, 0xff);
452 PUSH_DATA (push
, 0xff);
453 BEGIN_NVC0(push
, SUBC_3D(0x074c), 1);
454 PUSH_DATA (push
, 0x3f);
456 BEGIN_NVC0(push
, SUBC_3D(0x16a8), 1);
457 PUSH_DATA (push
, (3 << 16) | 3);
458 BEGIN_NVC0(push
, SUBC_3D(0x1794), 1);
459 PUSH_DATA (push
, (2 << 16) | 2);
461 if (obj_class
< GM107_3D_CLASS
) {
462 BEGIN_NVC0(push
, SUBC_3D(0x12ac), 1);
465 BEGIN_NVC0(push
, SUBC_3D(0x0218), 1);
466 PUSH_DATA (push
, 0x10);
467 BEGIN_NVC0(push
, SUBC_3D(0x10fc), 1);
468 PUSH_DATA (push
, 0x10);
469 BEGIN_NVC0(push
, SUBC_3D(0x1290), 1);
470 PUSH_DATA (push
, 0x10);
471 BEGIN_NVC0(push
, SUBC_3D(0x12d8), 2);
472 PUSH_DATA (push
, 0x10);
473 PUSH_DATA (push
, 0x10);
474 BEGIN_NVC0(push
, SUBC_3D(0x1140), 1);
475 PUSH_DATA (push
, 0x10);
476 BEGIN_NVC0(push
, SUBC_3D(0x1610), 1);
477 PUSH_DATA (push
, 0xe);
479 BEGIN_NVC0(push
, SUBC_3D(0x164c), 1);
480 PUSH_DATA (push
, 1 << 12);
481 BEGIN_NVC0(push
, SUBC_3D(0x030c), 1);
483 BEGIN_NVC0(push
, SUBC_3D(0x0300), 1);
486 BEGIN_NVC0(push
, SUBC_3D(0x02d0), 1);
487 PUSH_DATA (push
, 0x3fffff);
488 BEGIN_NVC0(push
, SUBC_3D(0x0fdc), 1);
490 BEGIN_NVC0(push
, SUBC_3D(0x19c0), 1);
493 if (obj_class
< GM107_3D_CLASS
) {
494 BEGIN_NVC0(push
, SUBC_3D(0x075c), 1);
497 if (obj_class
>= NVE4_3D_CLASS
) {
498 BEGIN_NVC0(push
, SUBC_3D(0x07fc), 1);
503 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
504 * are supposed to do */
508 nvc0_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
510 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
511 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
513 /* we need to do it after possible flush in MARK_RING */
514 *sequence
= ++screen
->base
.fence
.sequence
;
516 BEGIN_NVC0(push
, NVC0_3D(QUERY_ADDRESS_HIGH
), 4);
517 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
518 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
519 PUSH_DATA (push
, *sequence
);
520 PUSH_DATA (push
, NVC0_3D_QUERY_GET_FENCE
| NVC0_3D_QUERY_GET_SHORT
|
521 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT
));
525 nvc0_screen_fence_update(struct pipe_screen
*pscreen
)
527 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
528 return screen
->fence
.map
[0];
532 nvc0_screen_init_compute(struct nvc0_screen
*screen
)
534 screen
->base
.base
.get_compute_param
= nvc0_screen_get_compute_param
;
536 switch (screen
->base
.device
->chipset
& ~0xf) {
539 /* Using COMPUTE has weird effects on 3D state, we need to
540 * investigate this further before enabling it by default.
542 if (debug_get_bool_option("NVC0_COMPUTE", FALSE
))
543 return nvc0_screen_compute_setup(screen
, screen
->base
.pushbuf
);
546 return nve4_screen_compute_setup(screen
, screen
->base
.pushbuf
);
557 nvc0_screen_resize_tls_area(struct nvc0_screen
*screen
,
558 uint32_t lpos
, uint32_t lneg
, uint32_t cstack
)
560 struct nouveau_bo
*bo
= NULL
;
562 uint64_t size
= (lpos
+ lneg
) * 32 + cstack
;
564 if (size
>= (1 << 20)) {
565 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64
"\n", size
);
569 size
*= (screen
->base
.device
->chipset
>= 0xe0) ? 64 : 48; /* max warps */
570 size
= align(size
, 0x8000);
571 size
*= screen
->mp_count
;
573 size
= align(size
, 1 << 17);
575 ret
= nouveau_bo_new(screen
->base
.device
, NOUVEAU_BO_VRAM
, 1 << 17, size
,
578 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64
"\n", size
);
581 nouveau_bo_ref(NULL
, &screen
->tls
);
586 #define FAIL_SCREEN_INIT(str, err) \
588 NOUVEAU_ERR(str, err); \
589 nvc0_screen_destroy(pscreen); \
594 nvc0_screen_create(struct nouveau_device
*dev
)
596 struct nvc0_screen
*screen
;
597 struct pipe_screen
*pscreen
;
598 struct nouveau_object
*chan
;
599 struct nouveau_pushbuf
*push
;
604 union nouveau_bo_config mm_config
;
606 switch (dev
->chipset
& ~0xf) {
618 screen
= CALLOC_STRUCT(nvc0_screen
);
621 pscreen
= &screen
->base
.base
;
623 ret
= nouveau_screen_init(&screen
->base
, dev
);
625 nvc0_screen_destroy(pscreen
);
628 chan
= screen
->base
.channel
;
629 push
= screen
->base
.pushbuf
;
630 push
->user_priv
= screen
;
633 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
634 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
|
635 PIPE_BIND_COMMAND_ARGS_BUFFER
;
636 screen
->base
.sysmem_bindings
|=
637 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
639 pscreen
->destroy
= nvc0_screen_destroy
;
640 pscreen
->context_create
= nvc0_create
;
641 pscreen
->is_format_supported
= nvc0_screen_is_format_supported
;
642 pscreen
->get_param
= nvc0_screen_get_param
;
643 pscreen
->get_shader_param
= nvc0_screen_get_shader_param
;
644 pscreen
->get_paramf
= nvc0_screen_get_paramf
;
645 pscreen
->get_driver_query_info
= nvc0_screen_get_driver_query_info
;
647 nvc0_screen_init_resource_functions(pscreen
);
649 screen
->base
.base
.get_video_param
= nouveau_vp3_screen_get_video_param
;
650 screen
->base
.base
.is_video_format_supported
= nouveau_vp3_screen_video_supported
;
652 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
, 0, 4096, NULL
,
656 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
657 screen
->fence
.map
= screen
->fence
.bo
->map
;
658 screen
->base
.fence
.emit
= nvc0_screen_fence_emit
;
659 screen
->base
.fence
.update
= nvc0_screen_fence_update
;
662 ret
= nouveau_object_new(chan
,
663 (dev
->chipset
< 0xe0) ? 0x1f906e : 0x906e, 0x906e,
664 NULL
, 0, &screen
->nvsw
);
666 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret
);
669 switch (dev
->chipset
& ~0xf) {
673 obj_class
= NVF0_P2MF_CLASS
;
676 obj_class
= NVE4_P2MF_CLASS
;
679 obj_class
= NVC0_M2MF_CLASS
;
682 ret
= nouveau_object_new(chan
, 0xbeef323f, obj_class
, NULL
, 0,
685 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret
);
687 BEGIN_NVC0(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
688 PUSH_DATA (push
, screen
->m2mf
->oclass
);
689 if (screen
->m2mf
->oclass
== NVE4_P2MF_CLASS
) {
690 BEGIN_NVC0(push
, SUBC_COPY(NV01_SUBCHAN_OBJECT
), 1);
691 PUSH_DATA (push
, 0xa0b5);
694 ret
= nouveau_object_new(chan
, 0xbeef902d, NVC0_2D_CLASS
, NULL
, 0,
697 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret
);
699 BEGIN_NVC0(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
700 PUSH_DATA (push
, screen
->eng2d
->oclass
);
701 BEGIN_NVC0(push
, NVC0_2D(SINGLE_GPC
), 1);
703 BEGIN_NVC0(push
, NVC0_2D(OPERATION
), 1);
704 PUSH_DATA (push
, NVC0_2D_OPERATION_SRCCOPY
);
705 BEGIN_NVC0(push
, NVC0_2D(CLIP_ENABLE
), 1);
707 BEGIN_NVC0(push
, NVC0_2D(COLOR_KEY_ENABLE
), 1);
709 BEGIN_NVC0(push
, SUBC_2D(0x0884), 1);
710 PUSH_DATA (push
, 0x3f);
711 BEGIN_NVC0(push
, SUBC_2D(0x0888), 1);
713 BEGIN_NVC0(push
, NVC0_2D(COND_MODE
), 1);
714 PUSH_DATA (push
, NVC0_2D_COND_MODE_ALWAYS
);
716 BEGIN_NVC0(push
, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH
), 2);
717 PUSH_DATAh(push
, screen
->fence
.bo
->offset
+ 16);
718 PUSH_DATA (push
, screen
->fence
.bo
->offset
+ 16);
720 switch (dev
->chipset
& ~0xf) {
722 obj_class
= GM107_3D_CLASS
;
726 obj_class
= NVF0_3D_CLASS
;
729 switch (dev
->chipset
) {
731 obj_class
= NVEA_3D_CLASS
;
734 obj_class
= NVE4_3D_CLASS
;
739 obj_class
= NVC8_3D_CLASS
;
743 switch (dev
->chipset
) {
745 obj_class
= NVC8_3D_CLASS
;
748 obj_class
= NVC1_3D_CLASS
;
751 obj_class
= NVC0_3D_CLASS
;
756 ret
= nouveau_object_new(chan
, 0xbeef003d, obj_class
, NULL
, 0,
759 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret
);
760 screen
->base
.class_3d
= obj_class
;
762 BEGIN_NVC0(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
763 PUSH_DATA (push
, screen
->eng3d
->oclass
);
765 BEGIN_NVC0(push
, NVC0_3D(COND_MODE
), 1);
766 PUSH_DATA (push
, NVC0_3D_COND_MODE_ALWAYS
);
768 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE
)) {
769 /* kill shaders after about 1 second (at 100 MHz) */
770 BEGIN_NVC0(push
, NVC0_3D(WATCHDOG_TIMER
), 1);
771 PUSH_DATA (push
, 0x17);
774 IMMED_NVC0(push
, NVC0_3D(ZETA_COMP_ENABLE
), dev
->drm_version
>= 0x01000101);
775 BEGIN_NVC0(push
, NVC0_3D(RT_COMP_ENABLE(0)), 8);
776 for (i
= 0; i
< 8; ++i
)
777 PUSH_DATA(push
, dev
->drm_version
>= 0x01000101);
779 BEGIN_NVC0(push
, NVC0_3D(RT_CONTROL
), 1);
782 BEGIN_NVC0(push
, NVC0_3D(CSAA_ENABLE
), 1);
784 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_ENABLE
), 1);
786 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_MODE
), 1);
787 PUSH_DATA (push
, NVC0_3D_MULTISAMPLE_MODE_MS1
);
788 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_CTRL
), 1);
790 BEGIN_NVC0(push
, NVC0_3D(LINE_WIDTH_SEPARATE
), 1);
792 BEGIN_NVC0(push
, NVC0_3D(LINE_LAST_PIXEL
), 1);
794 BEGIN_NVC0(push
, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS
), 1);
796 BEGIN_NVC0(push
, NVC0_3D(BLEND_SEPARATE_ALPHA
), 1);
798 BEGIN_NVC0(push
, NVC0_3D(BLEND_ENABLE_COMMON
), 1);
800 if (screen
->eng3d
->oclass
< NVE4_3D_CLASS
) {
801 BEGIN_NVC0(push
, NVC0_3D(TEX_MISC
), 1);
802 PUSH_DATA (push
, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP
);
804 BEGIN_NVC0(push
, NVE4_3D(TEX_CB_INDEX
), 1);
805 PUSH_DATA (push
, 15);
807 BEGIN_NVC0(push
, NVC0_3D(CALL_LIMIT_LOG
), 1);
808 PUSH_DATA (push
, 8); /* 128 */
809 BEGIN_NVC0(push
, NVC0_3D(ZCULL_STATCTRS_ENABLE
), 1);
811 if (screen
->eng3d
->oclass
>= NVC1_3D_CLASS
) {
812 BEGIN_NVC0(push
, NVC0_3D(CACHE_SPLIT
), 1);
813 PUSH_DATA (push
, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1
);
816 nvc0_magic_3d_init(push
, screen
->eng3d
->oclass
);
818 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17, 1 << 20, NULL
,
823 /* XXX: getting a page fault at the end of the code buffer every few
824 * launches, don't use the last 256 bytes to work around them - prefetch ?
826 nouveau_heap_init(&screen
->text_heap
, 0, (1 << 20) - 0x100);
828 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 12, 6 << 16, NULL
,
829 &screen
->uniform_bo
);
833 PUSH_REFN (push
, screen
->uniform_bo
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
835 for (i
= 0; i
< 5; ++i
) {
836 /* TIC and TSC entries for each unit (nve4+ only) */
837 /* auxiliary constants (6 user clip planes, base instance id) */
838 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
839 PUSH_DATA (push
, 512);
840 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (i
<< 9));
841 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (i
<< 9));
842 BEGIN_NVC0(push
, NVC0_3D(CB_BIND(i
)), 1);
843 PUSH_DATA (push
, (15 << 4) | 1);
844 if (screen
->eng3d
->oclass
>= NVE4_3D_CLASS
) {
846 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 9);
848 for (j
= 0; j
< 8; ++j
)
851 BEGIN_NVC0(push
, NVC0_3D(TEX_LIMITS(i
)), 1);
852 PUSH_DATA (push
, 0x54);
855 BEGIN_NVC0(push
, NVC0_3D(LINKED_TSC
), 1);
858 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
859 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
860 PUSH_DATA (push
, 256);
861 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
862 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
863 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 5);
865 PUSH_DATAf(push
, 0.0f
);
866 PUSH_DATAf(push
, 0.0f
);
867 PUSH_DATAf(push
, 0.0f
);
868 PUSH_DATAf(push
, 0.0f
);
869 BEGIN_NVC0(push
, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH
), 2);
870 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
871 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
873 if (dev
->drm_version
>= 0x01000101) {
874 ret
= nouveau_getparam(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
876 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
880 if (dev
->chipset
>= 0xe0 && dev
->chipset
< 0xf0)
881 value
= (8 << 8) | 4;
883 value
= (16 << 8) | 4;
885 screen
->mp_count
= value
>> 8;
886 screen
->mp_count_compute
= screen
->mp_count
;
888 nvc0_screen_resize_tls_area(screen
, 128 * 16, 0, 0x200);
890 BEGIN_NVC0(push
, NVC0_3D(CODE_ADDRESS_HIGH
), 2);
891 PUSH_DATAh(push
, screen
->text
->offset
);
892 PUSH_DATA (push
, screen
->text
->offset
);
893 BEGIN_NVC0(push
, NVC0_3D(TEMP_ADDRESS_HIGH
), 4);
894 PUSH_DATAh(push
, screen
->tls
->offset
);
895 PUSH_DATA (push
, screen
->tls
->offset
);
896 PUSH_DATA (push
, screen
->tls
->size
>> 32);
897 PUSH_DATA (push
, screen
->tls
->size
);
898 BEGIN_NVC0(push
, NVC0_3D(WARP_TEMP_ALLOC
), 1);
900 BEGIN_NVC0(push
, NVC0_3D(LOCAL_BASE
), 1);
903 if (screen
->eng3d
->oclass
< GM107_3D_CLASS
) {
904 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17, 1 << 20, NULL
,
905 &screen
->poly_cache
);
909 BEGIN_NVC0(push
, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH
), 3);
910 PUSH_DATAh(push
, screen
->poly_cache
->offset
);
911 PUSH_DATA (push
, screen
->poly_cache
->offset
);
915 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17, 1 << 17, NULL
,
920 BEGIN_NVC0(push
, NVC0_3D(TIC_ADDRESS_HIGH
), 3);
921 PUSH_DATAh(push
, screen
->txc
->offset
);
922 PUSH_DATA (push
, screen
->txc
->offset
);
923 PUSH_DATA (push
, NVC0_TIC_MAX_ENTRIES
- 1);
925 BEGIN_NVC0(push
, NVC0_3D(TSC_ADDRESS_HIGH
), 3);
926 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
927 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
928 PUSH_DATA (push
, NVC0_TSC_MAX_ENTRIES
- 1);
930 BEGIN_NVC0(push
, NVC0_3D(SCREEN_Y_CONTROL
), 1);
932 BEGIN_NVC0(push
, NVC0_3D(WINDOW_OFFSET_X
), 2);
935 BEGIN_NVC0(push
, NVC0_3D(ZCULL_REGION
), 1); /* deactivate ZCULL */
936 PUSH_DATA (push
, 0x3f);
938 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_MODE
), 1);
939 PUSH_DATA (push
, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
940 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
941 for (i
= 0; i
< 8 * 2; ++i
)
943 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_EN
), 1);
945 BEGIN_NVC0(push
, NVC0_3D(CLIPID_ENABLE
), 1);
948 /* neither scissors, viewport nor stencil mask should affect clears */
949 BEGIN_NVC0(push
, NVC0_3D(CLEAR_FLAGS
), 1);
952 BEGIN_NVC0(push
, NVC0_3D(VIEWPORT_TRANSFORM_EN
), 1);
954 for (i
= 0; i
< NVC0_MAX_VIEWPORTS
; i
++) {
955 BEGIN_NVC0(push
, NVC0_3D(DEPTH_RANGE_NEAR(i
)), 2);
956 PUSH_DATAf(push
, 0.0f
);
957 PUSH_DATAf(push
, 1.0f
);
959 BEGIN_NVC0(push
, NVC0_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
960 PUSH_DATA (push
, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
);
962 /* We use scissors instead of exact view volume clipping,
963 * so they're always enabled.
965 for (i
= 0; i
< NVC0_MAX_VIEWPORTS
; i
++) {
966 BEGIN_NVC0(push
, NVC0_3D(SCISSOR_ENABLE(i
)), 3);
968 PUSH_DATA (push
, 8192 << 16);
969 PUSH_DATA (push
, 8192 << 16);
972 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
975 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE
, mme9097_per_instance_bf
);
976 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES
, mme9097_blend_enables
);
977 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT
, mme9097_vertex_array_select
);
978 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT
, mme9097_tep_select
);
979 MK_MACRO(NVC0_3D_MACRO_GP_SELECT
, mme9097_gp_select
);
980 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT
, mme9097_poly_mode_front
);
981 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK
, mme9097_poly_mode_back
);
982 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT
, mme9097_draw_arrays_indirect
);
983 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT
, mme9097_draw_elts_indirect
);
985 BEGIN_NVC0(push
, NVC0_3D(RASTERIZE_ENABLE
), 1);
987 BEGIN_NVC0(push
, NVC0_3D(RT_SEPARATE_FRAG_DATA
), 1);
989 BEGIN_NVC0(push
, NVC0_3D(MACRO_GP_SELECT
), 1);
990 PUSH_DATA (push
, 0x40);
991 BEGIN_NVC0(push
, NVC0_3D(LAYER
), 1);
993 BEGIN_NVC0(push
, NVC0_3D(MACRO_TEP_SELECT
), 1);
994 PUSH_DATA (push
, 0x30);
995 BEGIN_NVC0(push
, NVC0_3D(PATCH_VERTICES
), 1);
997 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(2)), 1);
998 PUSH_DATA (push
, 0x20);
999 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(0)), 1);
1000 PUSH_DATA (push
, 0x00);
1002 BEGIN_NVC0(push
, NVC0_3D(POINT_COORD_REPLACE
), 1);
1003 PUSH_DATA (push
, 0);
1004 BEGIN_NVC0(push
, NVC0_3D(POINT_RASTER_RULES
), 1);
1005 PUSH_DATA (push
, NVC0_3D_POINT_RASTER_RULES_OGL
);
1007 IMMED_NVC0(push
, NVC0_3D(EDGEFLAG
), 1);
1009 if (nvc0_screen_init_compute(screen
))
1014 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
1015 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
1017 mm_config
.nvc0
.tile_mode
= 0;
1018 mm_config
.nvc0
.memtype
= 0xfe0;
1019 screen
->mm_VRAM_fe0
= nouveau_mm_create(dev
, NOUVEAU_BO_VRAM
, &mm_config
);
1021 if (!nvc0_blitter_create(screen
))
1024 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, FALSE
);
1029 nvc0_screen_destroy(pscreen
);
1034 nvc0_screen_tic_alloc(struct nvc0_screen
*screen
, void *entry
)
1036 int i
= screen
->tic
.next
;
1038 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
1039 i
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
1041 screen
->tic
.next
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
1043 if (screen
->tic
.entries
[i
])
1044 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
1046 screen
->tic
.entries
[i
] = entry
;
1051 nvc0_screen_tsc_alloc(struct nvc0_screen
*screen
, void *entry
)
1053 int i
= screen
->tsc
.next
;
1055 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
1056 i
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
1058 screen
->tsc
.next
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
1060 if (screen
->tsc
.entries
[i
])
1061 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
1063 screen
->tsc
.entries
[i
] = entry
;