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gallium: remove PIPE_BIND_TRANSFER_READ/WRITE
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 const struct util_format_description *desc = util_format_description(format);
49
50 if (sample_count > 8)
51 return false;
52 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
53 return false;
54
55 /* Short-circuit the rest of the logic -- this is used by the state tracker
56 * to determine valid MS levels in a no-attachments scenario.
57 */
58 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
59 return true;
60
61 if (!util_format_is_supported(format, bindings))
62 return false;
63
64 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
65 if (util_format_get_blocksizebits(format) == 3 * 32)
66 return false;
67
68 if (bindings & PIPE_BIND_LINEAR)
69 if (util_format_is_depth_or_stencil(format) ||
70 (target != PIPE_TEXTURE_1D &&
71 target != PIPE_TEXTURE_2D &&
72 target != PIPE_TEXTURE_RECT) ||
73 sample_count > 1)
74 return false;
75
76 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
77 */
78 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
79 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
80 /* The claim is that this should work on GM107 but it doesn't. Need to
81 * test further and figure out if it's a nouveau issue or a HW one.
82 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
83 */
84 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
85 return false;
86
87 /* shared is always supported */
88 bindings &= ~(PIPE_BIND_LINEAR |
89 PIPE_BIND_SHARED);
90
91 if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
92 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
93 /* MS images are currently unsupported on Maxwell because they have to
94 * be handled explicitly. */
95 return false;
96 }
97
98 return (( nvc0_format_table[format].usage |
99 nvc0_vertex_format[format].usage) & bindings) == bindings;
100 }
101
102 static int
103 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
104 {
105 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
106 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
107
108 switch (param) {
109 /* non-boolean caps */
110 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
111 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
112 return 15;
113 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
114 return 12;
115 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
116 return 2048;
117 case PIPE_CAP_MIN_TEXEL_OFFSET:
118 return -8;
119 case PIPE_CAP_MAX_TEXEL_OFFSET:
120 return 7;
121 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
122 return -32;
123 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
124 return 31;
125 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
126 return 128 * 1024 * 1024;
127 case PIPE_CAP_GLSL_FEATURE_LEVEL:
128 if (class_3d <= NVF0_3D_CLASS)
129 return 430;
130 return 410;
131 case PIPE_CAP_MAX_RENDER_TARGETS:
132 return 8;
133 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
134 return 1;
135 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
136 return 4;
137 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
138 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
139 return 128;
140 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
141 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
142 return 1024;
143 case PIPE_CAP_MAX_VERTEX_STREAMS:
144 return 4;
145 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
146 return 2048;
147 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
148 return 256;
149 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
150 return 16; /* 256 for binding as RT, but that's not possible in GL */
151 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
152 return 16;
153 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
154 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
155 case PIPE_CAP_MAX_VIEWPORTS:
156 return NVC0_MAX_VIEWPORTS;
157 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
158 return 4;
159 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
160 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
161 case PIPE_CAP_ENDIANNESS:
162 return PIPE_ENDIAN_LITTLE;
163 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
164 return 30;
165 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
166 return NVC0_MAX_WINDOW_RECTANGLES;
167
168 /* supported caps */
169 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
170 case PIPE_CAP_TEXTURE_SWIZZLE:
171 case PIPE_CAP_TEXTURE_SHADOW_MAP:
172 case PIPE_CAP_NPOT_TEXTURES:
173 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
174 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
175 case PIPE_CAP_ANISOTROPIC_FILTER:
176 case PIPE_CAP_SEAMLESS_CUBE_MAP:
177 case PIPE_CAP_CUBE_MAP_ARRAY:
178 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
179 case PIPE_CAP_TEXTURE_MULTISAMPLE:
180 case PIPE_CAP_TWO_SIDED_STENCIL:
181 case PIPE_CAP_DEPTH_CLIP_DISABLE:
182 case PIPE_CAP_POINT_SPRITE:
183 case PIPE_CAP_TGSI_TEXCOORD:
184 case PIPE_CAP_SM3:
185 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
186 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
187 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
188 case PIPE_CAP_QUERY_TIMESTAMP:
189 case PIPE_CAP_QUERY_TIME_ELAPSED:
190 case PIPE_CAP_OCCLUSION_QUERY:
191 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
192 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
193 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
194 case PIPE_CAP_INDEP_BLEND_ENABLE:
195 case PIPE_CAP_INDEP_BLEND_FUNC:
196 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
197 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
198 case PIPE_CAP_PRIMITIVE_RESTART:
199 case PIPE_CAP_TGSI_INSTANCEID:
200 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
201 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
202 case PIPE_CAP_CONDITIONAL_RENDER:
203 case PIPE_CAP_TEXTURE_BARRIER:
204 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
205 case PIPE_CAP_START_INSTANCE:
206 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
207 case PIPE_CAP_DRAW_INDIRECT:
208 case PIPE_CAP_USER_CONSTANT_BUFFERS:
209 case PIPE_CAP_USER_INDEX_BUFFERS:
210 case PIPE_CAP_USER_VERTEX_BUFFERS:
211 case PIPE_CAP_TEXTURE_QUERY_LOD:
212 case PIPE_CAP_SAMPLE_SHADING:
213 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
214 case PIPE_CAP_TEXTURE_GATHER_SM5:
215 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
216 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
217 case PIPE_CAP_SAMPLER_VIEW_TARGET:
218 case PIPE_CAP_CLIP_HALFZ:
219 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
220 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
221 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
222 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
223 case PIPE_CAP_DEPTH_BOUNDS_TEST:
224 case PIPE_CAP_TGSI_TXQS:
225 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
226 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
227 case PIPE_CAP_SHAREABLE_SHADERS:
228 case PIPE_CAP_CLEAR_TEXTURE:
229 case PIPE_CAP_DRAW_PARAMETERS:
230 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
231 case PIPE_CAP_MULTI_DRAW_INDIRECT:
232 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
233 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
234 case PIPE_CAP_QUERY_BUFFER_OBJECT:
235 case PIPE_CAP_INVALIDATE_BUFFER:
236 case PIPE_CAP_STRING_MARKER:
237 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
238 case PIPE_CAP_CULL_DISTANCE:
239 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
240 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
241 case PIPE_CAP_TGSI_VOTE:
242 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
243 return 1;
244 case PIPE_CAP_COMPUTE:
245 return (class_3d < GP100_3D_CLASS);
246 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
247 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
248 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
249 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
250
251 /* unsupported caps */
252 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
253 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
254 case PIPE_CAP_SHADER_STENCIL_EXPORT:
255 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
256 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
257 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
258 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
259 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
260 case PIPE_CAP_FAKE_SW_MSAA:
261 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
262 case PIPE_CAP_VERTEXID_NOBASE:
263 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
264 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
265 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
266 case PIPE_CAP_GENERATE_MIPMAP:
267 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
268 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
269 case PIPE_CAP_QUERY_MEMORY_INFO:
270 case PIPE_CAP_PCI_GROUP:
271 case PIPE_CAP_PCI_BUS:
272 case PIPE_CAP_PCI_DEVICE:
273 case PIPE_CAP_PCI_FUNCTION:
274 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
275 return 0;
276
277 case PIPE_CAP_VENDOR_ID:
278 return 0x10de;
279 case PIPE_CAP_DEVICE_ID: {
280 uint64_t device_id;
281 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
282 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
283 return -1;
284 }
285 return device_id;
286 }
287 case PIPE_CAP_ACCELERATED:
288 return 1;
289 case PIPE_CAP_VIDEO_MEMORY:
290 return dev->vram_size >> 20;
291 case PIPE_CAP_UMA:
292 return 0;
293 }
294
295 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
296 return 0;
297 }
298
299 static int
300 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
301 enum pipe_shader_cap param)
302 {
303 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
304
305 switch (shader) {
306 case PIPE_SHADER_VERTEX:
307 case PIPE_SHADER_GEOMETRY:
308 case PIPE_SHADER_FRAGMENT:
309 case PIPE_SHADER_COMPUTE:
310 case PIPE_SHADER_TESS_CTRL:
311 case PIPE_SHADER_TESS_EVAL:
312 break;
313 default:
314 return 0;
315 }
316
317 switch (param) {
318 case PIPE_SHADER_CAP_PREFERRED_IR:
319 return PIPE_SHADER_IR_TGSI;
320 case PIPE_SHADER_CAP_SUPPORTED_IRS:
321 return 1 << PIPE_SHADER_IR_TGSI;
322 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
323 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
324 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
325 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
326 return 16384;
327 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
328 return 16;
329 case PIPE_SHADER_CAP_MAX_INPUTS:
330 if (shader == PIPE_SHADER_VERTEX)
331 return 32;
332 /* NOTE: These only count our slots for GENERIC varyings.
333 * The address space may be larger, but the actual hard limit seems to be
334 * less than what the address space layout permits, so don't add TEXCOORD,
335 * COLOR, etc. here.
336 */
337 if (shader == PIPE_SHADER_FRAGMENT)
338 return 0x1f0 / 16;
339 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
340 * and excludes 0x60 per-patch inputs.
341 */
342 return 0x200 / 16;
343 case PIPE_SHADER_CAP_MAX_OUTPUTS:
344 return 32;
345 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
346 return 65536;
347 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
348 return NVC0_MAX_PIPE_CONSTBUFS;
349 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
350 return shader != PIPE_SHADER_FRAGMENT;
351 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
352 return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
353 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
354 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
355 return 1;
356 case PIPE_SHADER_CAP_MAX_PREDS:
357 return 0;
358 case PIPE_SHADER_CAP_MAX_TEMPS:
359 return NVC0_CAP_MAX_PROGRAM_TEMPS;
360 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
361 return 1;
362 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
363 return 1;
364 case PIPE_SHADER_CAP_SUBROUTINES:
365 return 1;
366 case PIPE_SHADER_CAP_INTEGERS:
367 return 1;
368 case PIPE_SHADER_CAP_DOUBLES:
369 return 1;
370 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
371 return 1;
372 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
373 return 1;
374 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
375 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
376 return 0;
377 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
378 return NVC0_MAX_BUFFERS;
379 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
380 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
381 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
382 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
383 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
384 return 32;
385 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
386 if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
387 return NVC0_MAX_IMAGES;
388 if (class_3d < NVE4_3D_CLASS)
389 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
390 return NVC0_MAX_IMAGES;
391 return 0;
392 default:
393 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
394 return 0;
395 }
396 }
397
398 static float
399 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
400 {
401 switch (param) {
402 case PIPE_CAPF_MAX_LINE_WIDTH:
403 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
404 return 10.0f;
405 case PIPE_CAPF_MAX_POINT_WIDTH:
406 return 63.0f;
407 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
408 return 63.375f;
409 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
410 return 16.0f;
411 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
412 return 15.0f;
413 case PIPE_CAPF_GUARD_BAND_LEFT:
414 case PIPE_CAPF_GUARD_BAND_TOP:
415 return 0.0f;
416 case PIPE_CAPF_GUARD_BAND_RIGHT:
417 case PIPE_CAPF_GUARD_BAND_BOTTOM:
418 return 0.0f; /* that or infinity */
419 }
420
421 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
422 return 0.0f;
423 }
424
425 static int
426 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
427 enum pipe_shader_ir ir_type,
428 enum pipe_compute_cap param, void *data)
429 {
430 struct nvc0_screen *screen = nvc0_screen(pscreen);
431 const uint16_t obj_class = screen->compute->oclass;
432
433 #define RET(x) do { \
434 if (data) \
435 memcpy(data, x, sizeof(x)); \
436 return sizeof(x); \
437 } while (0)
438
439 switch (param) {
440 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
441 RET((uint64_t []) { 3 });
442 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
443 if (obj_class >= NVE4_COMPUTE_CLASS) {
444 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
445 } else {
446 RET(((uint64_t []) { 65535, 65535, 65535 }));
447 }
448 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
449 RET(((uint64_t []) { 1024, 1024, 64 }));
450 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
451 RET((uint64_t []) { 1024 });
452 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
453 RET((uint64_t []) { 1ULL << 40 });
454 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
455 switch (obj_class) {
456 case GM200_COMPUTE_CLASS:
457 RET((uint64_t []) { 96 << 10 });
458 break;
459 case GM107_COMPUTE_CLASS:
460 RET((uint64_t []) { 64 << 10 });
461 break;
462 default:
463 RET((uint64_t []) { 48 << 10 });
464 break;
465 }
466 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
467 RET((uint64_t []) { 512 << 10 });
468 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
469 RET((uint64_t []) { 4096 });
470 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
471 RET((uint32_t []) { 32 });
472 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
473 RET((uint64_t []) { 1ULL << 40 });
474 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
475 RET((uint32_t []) { 0 });
476 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
477 RET((uint32_t []) { screen->mp_count_compute });
478 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
479 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
480 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
481 RET((uint32_t []) { 64 });
482 default:
483 return 0;
484 }
485
486 #undef RET
487 }
488
489 static void
490 nvc0_screen_destroy(struct pipe_screen *pscreen)
491 {
492 struct nvc0_screen *screen = nvc0_screen(pscreen);
493
494 if (!nouveau_drm_screen_unref(&screen->base))
495 return;
496
497 if (screen->base.fence.current) {
498 struct nouveau_fence *current = NULL;
499
500 /* nouveau_fence_wait will create a new current fence, so wait on the
501 * _current_ one, and remove both.
502 */
503 nouveau_fence_ref(screen->base.fence.current, &current);
504 nouveau_fence_wait(current, NULL);
505 nouveau_fence_ref(NULL, &current);
506 nouveau_fence_ref(NULL, &screen->base.fence.current);
507 }
508 if (screen->base.pushbuf)
509 screen->base.pushbuf->user_priv = NULL;
510
511 if (screen->blitter)
512 nvc0_blitter_destroy(screen);
513 if (screen->pm.prog) {
514 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
515 nvc0_program_destroy(NULL, screen->pm.prog);
516 FREE(screen->pm.prog);
517 }
518
519 nouveau_bo_ref(NULL, &screen->text);
520 nouveau_bo_ref(NULL, &screen->uniform_bo);
521 nouveau_bo_ref(NULL, &screen->tls);
522 nouveau_bo_ref(NULL, &screen->txc);
523 nouveau_bo_ref(NULL, &screen->fence.bo);
524 nouveau_bo_ref(NULL, &screen->poly_cache);
525
526 nouveau_heap_destroy(&screen->lib_code);
527 nouveau_heap_destroy(&screen->text_heap);
528
529 FREE(screen->tic.entries);
530
531 nouveau_object_del(&screen->eng3d);
532 nouveau_object_del(&screen->eng2d);
533 nouveau_object_del(&screen->m2mf);
534 nouveau_object_del(&screen->compute);
535 nouveau_object_del(&screen->nvsw);
536
537 nouveau_screen_fini(&screen->base);
538
539 FREE(screen);
540 }
541
542 static int
543 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
544 unsigned size, const uint32_t *data)
545 {
546 struct nouveau_pushbuf *push = screen->base.pushbuf;
547
548 size /= 4;
549
550 assert((pos + size) <= 0x800);
551
552 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
553 PUSH_DATA (push, (m - 0x3800) / 8);
554 PUSH_DATA (push, pos);
555 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
556 PUSH_DATA (push, pos);
557 PUSH_DATAp(push, data, size);
558
559 return pos + size;
560 }
561
562 static void
563 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
564 {
565 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
566 PUSH_DATA (push, 0xff);
567 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
568 PUSH_DATA (push, 0xff);
569 PUSH_DATA (push, 0xff);
570 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
571 PUSH_DATA (push, 0xff);
572 PUSH_DATA (push, 0xff);
573 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
574 PUSH_DATA (push, 0x3f);
575
576 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
577 PUSH_DATA (push, (3 << 16) | 3);
578 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
579 PUSH_DATA (push, (2 << 16) | 2);
580
581 if (obj_class < GM107_3D_CLASS) {
582 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
583 PUSH_DATA (push, 0);
584 }
585 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
586 PUSH_DATA (push, 0x10);
587 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
588 PUSH_DATA (push, 0x10);
589 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
590 PUSH_DATA (push, 0x10);
591 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
592 PUSH_DATA (push, 0x10);
593 PUSH_DATA (push, 0x10);
594 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
595 PUSH_DATA (push, 0x10);
596 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
597 PUSH_DATA (push, 0xe);
598
599 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
600 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
601 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
602 PUSH_DATA (push, 0);
603 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
604 PUSH_DATA (push, 3);
605
606 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
607 PUSH_DATA (push, 0x3fffff);
608 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
609 PUSH_DATA (push, 1);
610 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
611 PUSH_DATA (push, 1);
612
613 if (obj_class < GM107_3D_CLASS) {
614 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
615 PUSH_DATA (push, 3);
616
617 if (obj_class >= NVE4_3D_CLASS) {
618 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
619 PUSH_DATA (push, 1);
620 }
621 }
622
623 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
624 * are supposed to do */
625 }
626
627 static void
628 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
629 {
630 struct nvc0_screen *screen = nvc0_screen(pscreen);
631 struct nouveau_pushbuf *push = screen->base.pushbuf;
632
633 /* we need to do it after possible flush in MARK_RING */
634 *sequence = ++screen->base.fence.sequence;
635
636 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
637 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
638 PUSH_DATAh(push, screen->fence.bo->offset);
639 PUSH_DATA (push, screen->fence.bo->offset);
640 PUSH_DATA (push, *sequence);
641 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
642 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
643 }
644
645 static u32
646 nvc0_screen_fence_update(struct pipe_screen *pscreen)
647 {
648 struct nvc0_screen *screen = nvc0_screen(pscreen);
649 return screen->fence.map[0];
650 }
651
652 static int
653 nvc0_screen_init_compute(struct nvc0_screen *screen)
654 {
655 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
656
657 switch (screen->base.device->chipset & ~0xf) {
658 case 0xc0:
659 case 0xd0:
660 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
661 case 0xe0:
662 case 0xf0:
663 case 0x100:
664 case 0x110:
665 case 0x120:
666 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
667 case 0x130:
668 return 0;
669 default:
670 return -1;
671 }
672 }
673
674 static int
675 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
676 uint32_t lpos, uint32_t lneg, uint32_t cstack)
677 {
678 struct nouveau_bo *bo = NULL;
679 int ret;
680 uint64_t size = (lpos + lneg) * 32 + cstack;
681
682 if (size >= (1 << 20)) {
683 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
684 return -1;
685 }
686
687 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
688 size = align(size, 0x8000);
689 size *= screen->mp_count;
690
691 size = align(size, 1 << 17);
692
693 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
694 NULL, &bo);
695 if (ret)
696 return ret;
697 nouveau_bo_ref(NULL, &screen->tls);
698 screen->tls = bo;
699 return 0;
700 }
701
702 int
703 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
704 {
705 struct nouveau_pushbuf *push = screen->base.pushbuf;
706 struct nouveau_bo *bo;
707 int ret;
708
709 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
710 1 << 17, size, NULL, &bo);
711 if (ret)
712 return ret;
713
714 nouveau_bo_ref(NULL, &screen->text);
715 screen->text = bo;
716
717 nouveau_heap_destroy(&screen->lib_code);
718 nouveau_heap_destroy(&screen->text_heap);
719
720 /* XXX: getting a page fault at the end of the code buffer every few
721 * launches, don't use the last 256 bytes to work around them - prefetch ?
722 */
723 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
724
725 /* update the code segment setup */
726 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
727 PUSH_DATAh(push, screen->text->offset);
728 PUSH_DATA (push, screen->text->offset);
729 if (screen->compute) {
730 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
731 PUSH_DATAh(push, screen->text->offset);
732 PUSH_DATA (push, screen->text->offset);
733 }
734
735 return 0;
736 }
737
738 #define FAIL_SCREEN_INIT(str, err) \
739 do { \
740 NOUVEAU_ERR(str, err); \
741 goto fail; \
742 } while(0)
743
744 struct nouveau_screen *
745 nvc0_screen_create(struct nouveau_device *dev)
746 {
747 struct nvc0_screen *screen;
748 struct pipe_screen *pscreen;
749 struct nouveau_object *chan;
750 struct nouveau_pushbuf *push;
751 uint64_t value;
752 uint32_t obj_class;
753 uint32_t flags;
754 int ret;
755 unsigned i;
756
757 switch (dev->chipset & ~0xf) {
758 case 0xc0:
759 case 0xd0:
760 case 0xe0:
761 case 0xf0:
762 case 0x100:
763 case 0x110:
764 case 0x120:
765 case 0x130:
766 break;
767 default:
768 return NULL;
769 }
770
771 screen = CALLOC_STRUCT(nvc0_screen);
772 if (!screen)
773 return NULL;
774 pscreen = &screen->base.base;
775 pscreen->destroy = nvc0_screen_destroy;
776
777 ret = nouveau_screen_init(&screen->base, dev);
778 if (ret)
779 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
780 chan = screen->base.channel;
781 push = screen->base.pushbuf;
782 push->user_priv = screen;
783 push->rsvd_kick = 5;
784
785 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
786 PIPE_BIND_SHADER_BUFFER |
787 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
788 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
789 screen->base.sysmem_bindings |=
790 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
791
792 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
793 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
794 screen->base.vidmem_bindings = 0;
795 }
796
797 pscreen->context_create = nvc0_create;
798 pscreen->is_format_supported = nvc0_screen_is_format_supported;
799 pscreen->get_param = nvc0_screen_get_param;
800 pscreen->get_shader_param = nvc0_screen_get_shader_param;
801 pscreen->get_paramf = nvc0_screen_get_paramf;
802 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
803 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
804
805 nvc0_screen_init_resource_functions(pscreen);
806
807 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
808 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
809
810 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
811 if (screen->base.drm->version >= 0x01000202)
812 flags |= NOUVEAU_BO_COHERENT;
813
814 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
815 if (ret)
816 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
817 nouveau_bo_map(screen->fence.bo, 0, NULL);
818 screen->fence.map = screen->fence.bo->map;
819 screen->base.fence.emit = nvc0_screen_fence_emit;
820 screen->base.fence.update = nvc0_screen_fence_update;
821
822
823 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
824 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
825 if (ret)
826 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
827
828 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
829 PUSH_DATA (push, screen->nvsw->handle);
830
831 switch (dev->chipset & ~0xf) {
832 case 0x130:
833 case 0x120:
834 case 0x110:
835 case 0x100:
836 case 0xf0:
837 obj_class = NVF0_P2MF_CLASS;
838 break;
839 case 0xe0:
840 obj_class = NVE4_P2MF_CLASS;
841 break;
842 default:
843 obj_class = NVC0_M2MF_CLASS;
844 break;
845 }
846 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
847 &screen->m2mf);
848 if (ret)
849 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
850
851 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
852 PUSH_DATA (push, screen->m2mf->oclass);
853 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
854 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
855 PUSH_DATA (push, 0xa0b5);
856 }
857
858 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
859 &screen->eng2d);
860 if (ret)
861 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
862
863 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
864 PUSH_DATA (push, screen->eng2d->oclass);
865 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
866 PUSH_DATA (push, 0);
867 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
868 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
869 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
870 PUSH_DATA (push, 0);
871 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
872 PUSH_DATA (push, 0);
873 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
874 PUSH_DATA (push, 0x3f);
875 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
876 PUSH_DATA (push, 1);
877 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
878 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
879
880 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
881 PUSH_DATAh(push, screen->fence.bo->offset + 16);
882 PUSH_DATA (push, screen->fence.bo->offset + 16);
883
884 switch (dev->chipset & ~0xf) {
885 case 0x130:
886 obj_class = GP100_3D_CLASS;
887 break;
888 case 0x120:
889 obj_class = GM200_3D_CLASS;
890 break;
891 case 0x110:
892 obj_class = GM107_3D_CLASS;
893 break;
894 case 0x100:
895 case 0xf0:
896 obj_class = NVF0_3D_CLASS;
897 break;
898 case 0xe0:
899 switch (dev->chipset) {
900 case 0xea:
901 obj_class = NVEA_3D_CLASS;
902 break;
903 default:
904 obj_class = NVE4_3D_CLASS;
905 break;
906 }
907 break;
908 case 0xd0:
909 obj_class = NVC8_3D_CLASS;
910 break;
911 case 0xc0:
912 default:
913 switch (dev->chipset) {
914 case 0xc8:
915 obj_class = NVC8_3D_CLASS;
916 break;
917 case 0xc1:
918 obj_class = NVC1_3D_CLASS;
919 break;
920 default:
921 obj_class = NVC0_3D_CLASS;
922 break;
923 }
924 break;
925 }
926 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
927 &screen->eng3d);
928 if (ret)
929 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
930 screen->base.class_3d = obj_class;
931
932 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
933 PUSH_DATA (push, screen->eng3d->oclass);
934
935 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
936 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
937
938 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
939 /* kill shaders after about 1 second (at 100 MHz) */
940 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
941 PUSH_DATA (push, 0x17);
942 }
943
944 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
945 screen->base.drm->version >= 0x01000101);
946 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
947 for (i = 0; i < 8; ++i)
948 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
949
950 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
951 PUSH_DATA (push, 1);
952
953 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
954 PUSH_DATA (push, 0);
955 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
956 PUSH_DATA (push, 0);
957 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
958 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
959 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
960 PUSH_DATA (push, 0);
961 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
962 PUSH_DATA (push, 1);
963 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
964 PUSH_DATA (push, 1);
965 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
966 PUSH_DATA (push, 1);
967 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
968 PUSH_DATA (push, 0);
969 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
970 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
971 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
972 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
973 } else {
974 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
975 PUSH_DATA (push, 15);
976 }
977 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
978 PUSH_DATA (push, 8); /* 128 */
979 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
980 PUSH_DATA (push, 1);
981 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
982 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
983 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
984 }
985
986 nvc0_magic_3d_init(push, screen->eng3d->oclass);
987
988 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
989 if (ret)
990 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
991
992 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
993 &screen->uniform_bo);
994 if (ret)
995 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
996
997 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
998
999 for (i = 0; i < 5; ++i) {
1000 /* TIC and TSC entries for each unit (nve4+ only) */
1001 /* auxiliary constants (6 user clip planes, base instance id) */
1002 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1003 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1004 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1005 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1006 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1007 PUSH_DATA (push, (15 << 4) | 1);
1008 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1009 unsigned j;
1010 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1011 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1012 for (j = 0; j < 8; ++j)
1013 PUSH_DATA(push, j);
1014 } else {
1015 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1016 PUSH_DATA (push, 0x54);
1017 }
1018
1019 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1020 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1021 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1022 PUSH_DATA (push, 0); /* 0 */
1023 PUSH_DATA (push, 0);
1024 PUSH_DATA (push, 1); /* 1 */
1025 PUSH_DATA (push, 0);
1026 PUSH_DATA (push, 0); /* 2 */
1027 PUSH_DATA (push, 1);
1028 PUSH_DATA (push, 1); /* 3 */
1029 PUSH_DATA (push, 1);
1030 PUSH_DATA (push, 2); /* 4 */
1031 PUSH_DATA (push, 0);
1032 PUSH_DATA (push, 3); /* 5 */
1033 PUSH_DATA (push, 0);
1034 PUSH_DATA (push, 2); /* 6 */
1035 PUSH_DATA (push, 1);
1036 PUSH_DATA (push, 3); /* 7 */
1037 PUSH_DATA (push, 1);
1038 }
1039 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1040 PUSH_DATA (push, 0);
1041
1042 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1043 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1044 PUSH_DATA (push, 256);
1045 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1046 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1047 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1048 PUSH_DATA (push, 0);
1049 PUSH_DATAf(push, 0.0f);
1050 PUSH_DATAf(push, 0.0f);
1051 PUSH_DATAf(push, 0.0f);
1052 PUSH_DATAf(push, 0.0f);
1053 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1054 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1055 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1056
1057 if (screen->base.drm->version >= 0x01000101) {
1058 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1059 if (ret)
1060 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1061 } else {
1062 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1063 value = (8 << 8) | 4;
1064 else
1065 value = (16 << 8) | 4;
1066 }
1067 screen->gpc_count = value & 0x000000ff;
1068 screen->mp_count = value >> 8;
1069 screen->mp_count_compute = screen->mp_count;
1070
1071 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1072 if (ret)
1073 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1074
1075 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1076 PUSH_DATAh(push, screen->tls->offset);
1077 PUSH_DATA (push, screen->tls->offset);
1078 PUSH_DATA (push, screen->tls->size >> 32);
1079 PUSH_DATA (push, screen->tls->size);
1080 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1081 PUSH_DATA (push, 0);
1082 /* Reduce likelihood of collision with real buffers by placing the hole at
1083 * the top of the 4G area. This will have to be dealt with for real
1084 * eventually by blocking off that area from the VM.
1085 */
1086 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1087 PUSH_DATA (push, 0xff << 24);
1088
1089 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1090 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1091 &screen->poly_cache);
1092 if (ret)
1093 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1094
1095 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1096 PUSH_DATAh(push, screen->poly_cache->offset);
1097 PUSH_DATA (push, screen->poly_cache->offset);
1098 PUSH_DATA (push, 3);
1099 }
1100
1101 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1102 &screen->txc);
1103 if (ret)
1104 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1105
1106 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1107 PUSH_DATAh(push, screen->txc->offset);
1108 PUSH_DATA (push, screen->txc->offset);
1109 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1110 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1111 screen->tic.maxwell = true;
1112 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1113 screen->tic.maxwell =
1114 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1115 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1116 }
1117 }
1118
1119 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1120 PUSH_DATAh(push, screen->txc->offset + 65536);
1121 PUSH_DATA (push, screen->txc->offset + 65536);
1122 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1123
1124 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1125 PUSH_DATA (push, 0);
1126 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1127 PUSH_DATA (push, 0);
1128 PUSH_DATA (push, 0);
1129 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1130 PUSH_DATA (push, 0x3f);
1131
1132 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1133 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1134 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1135 for (i = 0; i < 8 * 2; ++i)
1136 PUSH_DATA(push, 0);
1137 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1138 PUSH_DATA (push, 0);
1139 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1140 PUSH_DATA (push, 0);
1141
1142 /* neither scissors, viewport nor stencil mask should affect clears */
1143 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1144 PUSH_DATA (push, 0);
1145
1146 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1147 PUSH_DATA (push, 1);
1148 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1149 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1150 PUSH_DATAf(push, 0.0f);
1151 PUSH_DATAf(push, 1.0f);
1152 }
1153 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1154 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1155
1156 /* We use scissors instead of exact view volume clipping,
1157 * so they're always enabled.
1158 */
1159 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1160 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1161 PUSH_DATA (push, 1);
1162 PUSH_DATA (push, 8192 << 16);
1163 PUSH_DATA (push, 8192 << 16);
1164 }
1165
1166 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1167
1168 i = 0;
1169 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1170 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1171 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1172 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1173 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1174 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1175 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1176 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1177 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1178 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1179 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1180 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1181 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1182
1183 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1184 PUSH_DATA (push, 1);
1185 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1186 PUSH_DATA (push, 1);
1187 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1188 PUSH_DATA (push, 0x40);
1189 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1190 PUSH_DATA (push, 0);
1191 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1192 PUSH_DATA (push, 0x30);
1193 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1194 PUSH_DATA (push, 3);
1195 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1196 PUSH_DATA (push, 0x20);
1197 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1198 PUSH_DATA (push, 0x00);
1199 screen->save_state.patch_vertices = 3;
1200
1201 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1202 PUSH_DATA (push, 0);
1203 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1204 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1205
1206 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1207
1208 if (nvc0_screen_init_compute(screen))
1209 goto fail;
1210
1211 PUSH_KICK (push);
1212
1213 screen->tic.entries = CALLOC(4096, sizeof(void *));
1214 screen->tsc.entries = screen->tic.entries + 2048;
1215
1216 if (!nvc0_blitter_create(screen))
1217 goto fail;
1218
1219 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1220
1221 return &screen->base;
1222
1223 fail:
1224 screen->base.base.context_create = NULL;
1225 return &screen->base;
1226 }
1227
1228 int
1229 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1230 {
1231 int i = screen->tic.next;
1232
1233 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1234 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1235
1236 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1237
1238 if (screen->tic.entries[i])
1239 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1240
1241 screen->tic.entries[i] = entry;
1242 return i;
1243 }
1244
1245 int
1246 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1247 {
1248 int i = screen->tsc.next;
1249
1250 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1251 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1252
1253 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1254
1255 if (screen->tsc.entries[i])
1256 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1257
1258 screen->tsc.entries[i] = entry;
1259 return i;
1260 }