src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30
  31 #include "nouveau_vp3_video.h"
  32
  33 #include "nvc0/nvc0_context.h"
  34 #include "nvc0/nvc0_screen.h"
  35
  36 #include "nvc0/mme/com9097.mme.h"
  37 #include "nvc0/mme/com90c0.mme.h"
  38
  39 #include "nv50/g80_texture.xml.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned storage_sample_count,
  47                                 unsigned bindings)
  48 {
  49    const struct util_format_description *desc = util_format_description(format);
  50
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55
  56    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  57       return false;
  58
  59    /* Short-circuit the rest of the logic -- this is used by the state tracker
  60     * to determine valid MS levels in a no-attachments scenario.
  61     */
  62    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  63       return true;
  64
  65    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  66       if (util_format_get_blocksizebits(format) == 3 * 32)
  67          return false;
  68
  69    if (bindings & PIPE_BIND_LINEAR)
  70       if (util_format_is_depth_or_stencil(format) ||
  71           (target != PIPE_TEXTURE_1D &&
  72            target != PIPE_TEXTURE_2D &&
  73            target != PIPE_TEXTURE_RECT) ||
  74           sample_count > 1)
  75          return false;
  76
  77    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  78     */
  79    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  80         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  81        /* The claim is that this should work on GM107 but it doesn't. Need to
  82         * test further and figure out if it's a nouveau issue or a HW one.
  83        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  84         */
  85        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  86       return false;
  87
  88    /* shared is always supported */
  89    bindings &= ~(PIPE_BIND_LINEAR |
  90                  PIPE_BIND_SHARED);
  91
  92    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  93       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  94           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
  95          /* This should work on Fermi, but for currently unknown reasons it
  96           * does not and results in breaking reads from pbos. */
  97          return false;
  98       }
  99    }
 100
 101    return (( nvc0_format_table[format].usage |
 102             nvc0_vertex_format[format].usage) & bindings) == bindings;
 103 }
 104
 105 static int
 106 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 107 {
 108    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 109    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 110
 111    switch (param) {
 112    /* non-boolean caps */
 113    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 114    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 115       return 15;
 116    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 117       return 12;
 118    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 119       return 2048;
 120    case PIPE_CAP_MIN_TEXEL_OFFSET:
 121       return -8;
 122    case PIPE_CAP_MAX_TEXEL_OFFSET:
 123       return 7;
 124    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 125       return -32;
 126    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 127       return 31;
 128    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 129       return 128 * 1024 * 1024;
 130    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 131       return 430;
 132    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 133       return 430;
 134    case PIPE_CAP_MAX_RENDER_TARGETS:
 135       return 8;
 136    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 137       return 1;
 138    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 139    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 140       return 8;
 141    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 142       return 4;
 143    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 145       return 128;
 146    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 147    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 148       return 1024;
 149    case PIPE_CAP_MAX_VERTEX_STREAMS:
 150       return 4;
 151    case PIPE_CAP_MAX_GS_INVOCATIONS:
 152       return 32;
 153    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 154       return 1 << 27;
 155    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 156       return 2048;
 157    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 158       return 2047;
 159    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 160       return 256;
 161    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 162       if (class_3d < GM107_3D_CLASS)
 163          return 256; /* IMAGE bindings require alignment to 256 */
 164       return 16;
 165    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 166       return 16;
 167    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 168       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 169    case PIPE_CAP_MAX_VIEWPORTS:
 170       return NVC0_MAX_VIEWPORTS;
 171    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 172       return 4;
 173    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 174       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 175    case PIPE_CAP_ENDIANNESS:
 176       return PIPE_ENDIAN_LITTLE;
 177    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 178       return 30;
 179    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 180       return NVC0_MAX_WINDOW_RECTANGLES;
 181    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 182       return class_3d >= GM200_3D_CLASS ? 8 : 0;
 183    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 184       return 64 * 1024 * 1024;
 185
 186    /* supported caps */
 187    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 188    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 189    case PIPE_CAP_TEXTURE_SWIZZLE:
 190    case PIPE_CAP_NPOT_TEXTURES:
 191    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 192    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 193    case PIPE_CAP_ANISOTROPIC_FILTER:
 194    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 195    case PIPE_CAP_CUBE_MAP_ARRAY:
 196    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 197    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 198    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 199    case PIPE_CAP_POINT_SPRITE:
 200    case PIPE_CAP_TGSI_TEXCOORD:
 201    case PIPE_CAP_SM3:
 202    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 203    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 204    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 205    case PIPE_CAP_QUERY_TIMESTAMP:
 206    case PIPE_CAP_QUERY_TIME_ELAPSED:
 207    case PIPE_CAP_OCCLUSION_QUERY:
 208    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 209    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 210    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 211    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 212    case PIPE_CAP_INDEP_BLEND_ENABLE:
 213    case PIPE_CAP_INDEP_BLEND_FUNC:
 214    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 215    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 216    case PIPE_CAP_PRIMITIVE_RESTART:
 217    case PIPE_CAP_TGSI_INSTANCEID:
 218    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 219    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 220    case PIPE_CAP_CONDITIONAL_RENDER:
 221    case PIPE_CAP_TEXTURE_BARRIER:
 222    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 223    case PIPE_CAP_START_INSTANCE:
 224    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 225    case PIPE_CAP_DRAW_INDIRECT:
 226    case PIPE_CAP_USER_VERTEX_BUFFERS:
 227    case PIPE_CAP_TEXTURE_QUERY_LOD:
 228    case PIPE_CAP_SAMPLE_SHADING:
 229    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 230    case PIPE_CAP_TEXTURE_GATHER_SM5:
 231    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 232    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 233    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 234    case PIPE_CAP_CLIP_HALFZ:
 235    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 236    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 237    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 238    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 239    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 240    case PIPE_CAP_TGSI_TXQS:
 241    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 242    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 243    case PIPE_CAP_SHAREABLE_SHADERS:
 244    case PIPE_CAP_CLEAR_TEXTURE:
 245    case PIPE_CAP_DRAW_PARAMETERS:
 246    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 247    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 248    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 249    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 250    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 251    case PIPE_CAP_INVALIDATE_BUFFER:
 252    case PIPE_CAP_STRING_MARKER:
 253    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 254    case PIPE_CAP_CULL_DISTANCE:
 255    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 256    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 257    case PIPE_CAP_TGSI_VOTE:
 258    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 259    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 260    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 261    case PIPE_CAP_DOUBLES:
 262    case PIPE_CAP_INT64:
 263    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 264    case PIPE_CAP_TGSI_CLOCK:
 265    case PIPE_CAP_COMPUTE:
 266    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 267    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 268    case PIPE_CAP_QUERY_SO_OVERFLOW:
 269    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 270       return 1;
 271    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 272       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 273    case PIPE_CAP_TGSI_FS_FBFETCH:
 274       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 275    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 276    case PIPE_CAP_TGSI_BALLOT:
 277    case PIPE_CAP_BINDLESS_TEXTURE:
 278       return class_3d >= NVE4_3D_CLASS;
 279    case PIPE_CAP_TGSI_ATOMFADD:
 280       return class_3d < GM107_3D_CLASS; /* needs additional lowering */
 281    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 282    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 283    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 284    case PIPE_CAP_POST_DEPTH_COVERAGE:
 285    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 286    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 287    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 288    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 289       return class_3d >= GM200_3D_CLASS;
 290    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 291       return class_3d >= GP100_3D_CLASS;
 292
 293    /* unsupported caps */
 294    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 295    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 296    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 297    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 298    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 299    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 300    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 301    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 302    case PIPE_CAP_FAKE_SW_MSAA:
 303    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 304    case PIPE_CAP_VERTEXID_NOBASE:
 305    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 306    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 307    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 308    case PIPE_CAP_GENERATE_MIPMAP:
 309    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 310    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 311    case PIPE_CAP_QUERY_MEMORY_INFO:
 312    case PIPE_CAP_PCI_GROUP:
 313    case PIPE_CAP_PCI_BUS:
 314    case PIPE_CAP_PCI_DEVICE:
 315    case PIPE_CAP_PCI_FUNCTION:
 316    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 317    case PIPE_CAP_NATIVE_FENCE_FD:
 318    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 319    case PIPE_CAP_INT64_DIVMOD:
 320    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 321    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 322    case PIPE_CAP_MEMOBJ:
 323    case PIPE_CAP_LOAD_CONSTBUF:
 324    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 325    case PIPE_CAP_TILE_RASTER_ORDER:
 326    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 327    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 328    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 329    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 330    case PIPE_CAP_FENCE_SIGNAL:
 331    case PIPE_CAP_CONSTBUF0_FLAGS:
 332    case PIPE_CAP_PACKED_UNIFORMS:
 333    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 334    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 335    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 336    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 337    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 338    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 339    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 340    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 341       return 0;
 342
 343    case PIPE_CAP_VENDOR_ID:
 344       return 0x10de;
 345    case PIPE_CAP_DEVICE_ID: {
 346       uint64_t device_id;
 347       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 348          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 349          return -1;
 350       }
 351       return device_id;
 352    }
 353    case PIPE_CAP_ACCELERATED:
 354       return 1;
 355    case PIPE_CAP_VIDEO_MEMORY:
 356       return dev->vram_size >> 20;
 357    case PIPE_CAP_UMA:
 358       return 0;
 359    default:
 360       debug_printf("%s: unhandled cap %d\n", __func__, param);
 361       return u_pipe_screen_get_param_defaults(pscreen, param);
 362    }
 363 }
 364
 365 static int
 366 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 367                              enum pipe_shader_type shader,
 368                              enum pipe_shader_cap param)
 369 {
 370    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 371
 372    switch (shader) {
 373    case PIPE_SHADER_VERTEX:
 374    case PIPE_SHADER_GEOMETRY:
 375    case PIPE_SHADER_FRAGMENT:
 376    case PIPE_SHADER_COMPUTE:
 377    case PIPE_SHADER_TESS_CTRL:
 378    case PIPE_SHADER_TESS_EVAL:
 379       break;
 380    default:
 381       return 0;
 382    }
 383
 384    switch (param) {
 385    case PIPE_SHADER_CAP_PREFERRED_IR:
 386       return PIPE_SHADER_IR_TGSI;
 387    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 388       return 1 << PIPE_SHADER_IR_TGSI;
 389    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 390    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 391    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 392    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 393       return 16384;
 394    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 395       return 16;
 396    case PIPE_SHADER_CAP_MAX_INPUTS:
 397       if (shader == PIPE_SHADER_VERTEX)
 398          return 32;
 399       /* NOTE: These only count our slots for GENERIC varyings.
 400        * The address space may be larger, but the actual hard limit seems to be
 401        * less than what the address space layout permits, so don't add TEXCOORD,
 402        * COLOR, etc. here.
 403        */
 404       if (shader == PIPE_SHADER_FRAGMENT)
 405          return 0x1f0 / 16;
 406       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 407        * and excludes 0x60 per-patch inputs.
 408        */
 409       return 0x200 / 16;
 410    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 411       return 32;
 412    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 413       return NVC0_MAX_CONSTBUF_SIZE;
 414    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 415       return NVC0_MAX_PIPE_CONSTBUFS;
 416    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 417       return shader != PIPE_SHADER_FRAGMENT;
 418    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 419    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 420    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 421       return 1;
 422    case PIPE_SHADER_CAP_MAX_TEMPS:
 423       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 424    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 425       return 1;
 426    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 427       return 1;
 428    case PIPE_SHADER_CAP_SUBROUTINES:
 429       return 1;
 430    case PIPE_SHADER_CAP_INTEGERS:
 431       return 1;
 432    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 433       return 1;
 434    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 435       return 1;
 436    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 437       return 1;
 438    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 439    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 440    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 441    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 442    case PIPE_SHADER_CAP_INT64_ATOMICS:
 443    case PIPE_SHADER_CAP_FP16:
 444    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 445    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 446       return 0;
 447    case PIPE_SHADER_CAP_SCALAR_ISA:
 448       return 1;
 449    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 450       return NVC0_MAX_BUFFERS;
 451    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 452       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 453    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 454       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 455    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 456       return 32;
 457    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 458       if (class_3d >= NVE4_3D_CLASS)
 459          return NVC0_MAX_IMAGES;
 460       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 461          return NVC0_MAX_IMAGES;
 462       return 0;
 463    default:
 464       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 465       return 0;
 466    }
 467 }
 468
 469 static float
 470 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 471 {
 472    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 473
 474    switch (param) {
 475    case PIPE_CAPF_MAX_LINE_WIDTH:
 476    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 477       return 10.0f;
 478    case PIPE_CAPF_MAX_POINT_WIDTH:
 479       return 63.0f;
 480    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 481       return 63.375f;
 482    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 483       return 16.0f;
 484    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 485       return 15.0f;
 486    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 487       return 0.0f;
 488    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 489       return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
 490    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 491       return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
 492    }
 493
 494    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 495    return 0.0f;
 496 }
 497
 498 static int
 499 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 500                               enum pipe_shader_ir ir_type,
 501                               enum pipe_compute_cap param, void *data)
 502 {
 503    struct nvc0_screen *screen = nvc0_screen(pscreen);
 504    const uint16_t obj_class = screen->compute->oclass;
 505
 506 #define RET(x) do {                  \
 507    if (data)                         \
 508       memcpy(data, x, sizeof(x));    \
 509    return sizeof(x);                 \
 510 } while (0)
 511
 512    switch (param) {
 513    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 514       RET((uint64_t []) { 3 });
 515    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 516       if (obj_class >= NVE4_COMPUTE_CLASS) {
 517          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 518       } else {
 519          RET(((uint64_t []) { 65535, 65535, 65535 }));
 520       }
 521    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 522       RET(((uint64_t []) { 1024, 1024, 64 }));
 523    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 524       RET((uint64_t []) { 1024 });
 525    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 526       if (obj_class >= NVE4_COMPUTE_CLASS) {
 527          RET((uint64_t []) { 1024 });
 528       } else {
 529          RET((uint64_t []) { 512 });
 530       }
 531    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 532       RET((uint64_t []) { 1ULL << 40 });
 533    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 534       switch (obj_class) {
 535       case GM200_COMPUTE_CLASS:
 536          RET((uint64_t []) { 96 << 10 });
 537          break;
 538       case GM107_COMPUTE_CLASS:
 539          RET((uint64_t []) { 64 << 10 });
 540          break;
 541       default:
 542          RET((uint64_t []) { 48 << 10 });
 543          break;
 544       }
 545    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 546       RET((uint64_t []) { 512 << 10 });
 547    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 548       RET((uint64_t []) { 4096 });
 549    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 550       RET((uint32_t []) { 32 });
 551    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 552       RET((uint64_t []) { 1ULL << 40 });
 553    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 554       RET((uint32_t []) { 0 });
 555    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 556       RET((uint32_t []) { screen->mp_count_compute });
 557    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 558       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 559    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 560       RET((uint32_t []) { 64 });
 561    default:
 562       return 0;
 563    }
 564
 565 #undef RET
 566 }
 567
 568 static void
 569 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
 570                                   unsigned sample_count,
 571                                   unsigned *width, unsigned *height)
 572 {
 573    switch (sample_count) {
 574    case 0:
 575    case 1:
 576       /* this could be 4x4, but the GL state tracker makes it difficult to
 577        * create a 1x MSAA texture and smaller grids save CB space */
 578       *width = 2;
 579       *height = 4;
 580       break;
 581    case 2:
 582       *width = 2;
 583       *height = 4;
 584       break;
 585    case 4:
 586       *width = 2;
 587       *height = 2;
 588       break;
 589    case 8:
 590       *width = 1;
 591       *height = 2;
 592       break;
 593    default:
 594       assert(0);
 595    }
 596 }
 597
 598 static void
 599 nvc0_screen_destroy(struct pipe_screen *pscreen)
 600 {
 601    struct nvc0_screen *screen = nvc0_screen(pscreen);
 602
 603    if (!nouveau_drm_screen_unref(&screen->base))
 604       return;
 605
 606    if (screen->base.fence.current) {
 607       struct nouveau_fence *current = NULL;
 608
 609       /* nouveau_fence_wait will create a new current fence, so wait on the
 610        * _current_ one, and remove both.
 611        */
 612       nouveau_fence_ref(screen->base.fence.current, &current);
 613       nouveau_fence_wait(current, NULL);
 614       nouveau_fence_ref(NULL, &current);
 615       nouveau_fence_ref(NULL, &screen->base.fence.current);
 616    }
 617    if (screen->base.pushbuf)
 618       screen->base.pushbuf->user_priv = NULL;
 619
 620    if (screen->blitter)
 621       nvc0_blitter_destroy(screen);
 622    if (screen->pm.prog) {
 623       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 624       nvc0_program_destroy(NULL, screen->pm.prog);
 625       FREE(screen->pm.prog);
 626    }
 627
 628    nouveau_bo_ref(NULL, &screen->text);
 629    nouveau_bo_ref(NULL, &screen->uniform_bo);
 630    nouveau_bo_ref(NULL, &screen->tls);
 631    nouveau_bo_ref(NULL, &screen->txc);
 632    nouveau_bo_ref(NULL, &screen->fence.bo);
 633    nouveau_bo_ref(NULL, &screen->poly_cache);
 634
 635    nouveau_heap_destroy(&screen->lib_code);
 636    nouveau_heap_destroy(&screen->text_heap);
 637
 638    FREE(screen->tic.entries);
 639
 640    nouveau_object_del(&screen->eng3d);
 641    nouveau_object_del(&screen->eng2d);
 642    nouveau_object_del(&screen->m2mf);
 643    nouveau_object_del(&screen->compute);
 644    nouveau_object_del(&screen->nvsw);
 645
 646    nouveau_screen_fini(&screen->base);
 647
 648    FREE(screen);
 649 }
 650
 651 static int
 652 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 653                      unsigned size, const uint32_t *data)
 654 {
 655    struct nouveau_pushbuf *push = screen->base.pushbuf;
 656
 657    size /= 4;
 658
 659    assert((pos + size) <= 0x800);
 660
 661    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 662    PUSH_DATA (push, (m - 0x3800) / 8);
 663    PUSH_DATA (push, pos);
 664    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 665    PUSH_DATA (push, pos);
 666    PUSH_DATAp(push, data, size);
 667
 668    return pos + size;
 669 }
 670
 671 static void
 672 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 673 {
 674    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 675    PUSH_DATA (push, 0xff);
 676    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 677    PUSH_DATA (push, 0xff);
 678    PUSH_DATA (push, 0xff);
 679    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 680    PUSH_DATA (push, 0xff);
 681    PUSH_DATA (push, 0xff);
 682    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 683    PUSH_DATA (push, 0x3f);
 684
 685    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 686    PUSH_DATA (push, (3 << 16) | 3);
 687    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 688    PUSH_DATA (push, (2 << 16) | 2);
 689
 690    if (obj_class < GM107_3D_CLASS) {
 691       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 692       PUSH_DATA (push, 0);
 693    }
 694    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 695    PUSH_DATA (push, 0x10);
 696    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 697    PUSH_DATA (push, 0x10);
 698    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 699    PUSH_DATA (push, 0x10);
 700    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 701    PUSH_DATA (push, 0x10);
 702    PUSH_DATA (push, 0x10);
 703    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 704    PUSH_DATA (push, 0x10);
 705    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 706    PUSH_DATA (push, 0xe);
 707
 708    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 709    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 710    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 711    PUSH_DATA (push, 0);
 712    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 713    PUSH_DATA (push, 3);
 714
 715    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 716    PUSH_DATA (push, 0x3fffff);
 717    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 718    PUSH_DATA (push, 1);
 719    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 720    PUSH_DATA (push, 1);
 721
 722    if (obj_class < GM107_3D_CLASS) {
 723       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 724       PUSH_DATA (push, 3);
 725
 726       if (obj_class >= NVE4_3D_CLASS) {
 727          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 728          PUSH_DATA (push, 1);
 729       }
 730    }
 731
 732    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 733     * are supposed to do */
 734 }
 735
 736 static void
 737 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 738 {
 739    struct nvc0_screen *screen = nvc0_screen(pscreen);
 740    struct nouveau_pushbuf *push = screen->base.pushbuf;
 741
 742    /* we need to do it after possible flush in MARK_RING */
 743    *sequence = ++screen->base.fence.sequence;
 744
 745    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 746    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 747    PUSH_DATAh(push, screen->fence.bo->offset);
 748    PUSH_DATA (push, screen->fence.bo->offset);
 749    PUSH_DATA (push, *sequence);
 750    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 751               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 752 }
 753
 754 static u32
 755 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 756 {
 757    struct nvc0_screen *screen = nvc0_screen(pscreen);
 758    return screen->fence.map[0];
 759 }
 760
 761 static int
 762 nvc0_screen_init_compute(struct nvc0_screen *screen)
 763 {
 764    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 765
 766    switch (screen->base.device->chipset & ~0xf) {
 767    case 0xc0:
 768    case 0xd0:
 769       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 770    case 0xe0:
 771    case 0xf0:
 772    case 0x100:
 773    case 0x110:
 774    case 0x120:
 775    case 0x130:
 776       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 777    default:
 778       return -1;
 779    }
 780 }
 781
 782 static int
 783 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 784                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 785 {
 786    struct nouveau_bo *bo = NULL;
 787    int ret;
 788    uint64_t size = (lpos + lneg) * 32 + cstack;
 789
 790    if (size >= (1 << 20)) {
 791       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 792       return -1;
 793    }
 794
 795    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 796    size  = align(size, 0x8000);
 797    size *= screen->mp_count;
 798
 799    size = align(size, 1 << 17);
 800
 801    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 802                         NULL, &bo);
 803    if (ret)
 804       return ret;
 805
 806    /* Make sure that the pushbuf has acquired a reference to the old tls
 807     * segment, as it may have commands that will reference it.
 808     */
 809    if (screen->tls)
 810       PUSH_REFN(screen->base.pushbuf, screen->tls,
 811                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
 812    nouveau_bo_ref(NULL, &screen->tls);
 813    screen->tls = bo;
 814    return 0;
 815 }
 816
 817 int
 818 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 819 {
 820    struct nouveau_pushbuf *push = screen->base.pushbuf;
 821    struct nouveau_bo *bo;
 822    int ret;
 823
 824    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 825                         1 << 17, size, NULL, &bo);
 826    if (ret)
 827       return ret;
 828
 829    /* Make sure that the pushbuf has acquired a reference to the old text
 830     * segment, as it may have commands that will reference it.
 831     */
 832    if (screen->text)
 833       PUSH_REFN(push, screen->text,
 834                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
 835    nouveau_bo_ref(NULL, &screen->text);
 836    screen->text = bo;
 837
 838    nouveau_heap_destroy(&screen->lib_code);
 839    nouveau_heap_destroy(&screen->text_heap);
 840
 841    /* XXX: getting a page fault at the end of the code buffer every few
 842     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 843     */
 844    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 845
 846    /* update the code segment setup */
 847    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 848    PUSH_DATAh(push, screen->text->offset);
 849    PUSH_DATA (push, screen->text->offset);
 850    if (screen->compute) {
 851       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 852       PUSH_DATAh(push, screen->text->offset);
 853       PUSH_DATA (push, screen->text->offset);
 854    }
 855
 856    return 0;
 857 }
 858
 859 void
 860 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
 861                        int stage, int index, int size, uint64_t addr)
 862 {
 863    assert(stage != 5);
 864
 865    struct nouveau_pushbuf *push = screen->base.pushbuf;
 866
 867    if (screen->base.class_3d >= GM107_3D_CLASS) {
 868       struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
 869
 870       // TODO: Better figure out the conditions in which this is needed
 871       bool serialize = binding->addr == addr && binding->size != size;
 872       if (can_serialize)
 873          serialize = serialize && *can_serialize;
 874       if (serialize) {
 875          IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 876          if (can_serialize)
 877             *can_serialize = false;
 878       }
 879
 880       binding->addr = addr;
 881       binding->size = size;
 882    }
 883
 884    if (size >= 0) {
 885       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 886       PUSH_DATA (push, size);
 887       PUSH_DATAh(push, addr);
 888       PUSH_DATA (push, addr);
 889    }
 890    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
 891 }
 892
 893 #define FAIL_SCREEN_INIT(str, err)                    \
 894    do {                                               \
 895       NOUVEAU_ERR(str, err);                          \
 896       goto fail;                                      \
 897    } while(0)
 898
 899 struct nouveau_screen *
 900 nvc0_screen_create(struct nouveau_device *dev)
 901 {
 902    struct nvc0_screen *screen;
 903    struct pipe_screen *pscreen;
 904    struct nouveau_object *chan;
 905    struct nouveau_pushbuf *push;
 906    uint64_t value;
 907    uint32_t obj_class;
 908    uint32_t flags;
 909    int ret;
 910    unsigned i;
 911
 912    switch (dev->chipset & ~0xf) {
 913    case 0xc0:
 914    case 0xd0:
 915    case 0xe0:
 916    case 0xf0:
 917    case 0x100:
 918    case 0x110:
 919    case 0x120:
 920    case 0x130:
 921       break;
 922    default:
 923       return NULL;
 924    }
 925
 926    screen = CALLOC_STRUCT(nvc0_screen);
 927    if (!screen)
 928       return NULL;
 929    pscreen = &screen->base.base;
 930    pscreen->destroy = nvc0_screen_destroy;
 931
 932    ret = nouveau_screen_init(&screen->base, dev);
 933    if (ret)
 934       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 935    chan = screen->base.channel;
 936    push = screen->base.pushbuf;
 937    push->user_priv = screen;
 938    push->rsvd_kick = 5;
 939
 940    /* TODO: could this be higher on Kepler+? how does reclocking vs no
 941     * reclocking affect performance?
 942     * TODO: could this be higher on Fermi?
 943     */
 944    if (dev->chipset >= 0xe0)
 945       screen->base.transfer_pushbuf_threshold = 1024;
 946
 947    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 948       PIPE_BIND_SHADER_BUFFER |
 949       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 950       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 951    screen->base.sysmem_bindings |=
 952       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 953
 954    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 955       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 956       screen->base.vidmem_bindings = 0;
 957    }
 958
 959    pscreen->context_create = nvc0_create;
 960    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 961    pscreen->get_param = nvc0_screen_get_param;
 962    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 963    pscreen->get_paramf = nvc0_screen_get_paramf;
 964    pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
 965    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 966    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 967
 968    nvc0_screen_init_resource_functions(pscreen);
 969
 970    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 971    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 972
 973    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 974    if (screen->base.drm->version >= 0x01000202)
 975       flags |= NOUVEAU_BO_COHERENT;
 976
 977    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 978    if (ret)
 979       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 980    nouveau_bo_map(screen->fence.bo, 0, NULL);
 981    screen->fence.map = screen->fence.bo->map;
 982    screen->base.fence.emit = nvc0_screen_fence_emit;
 983    screen->base.fence.update = nvc0_screen_fence_update;
 984
 985
 986    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 987                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 988    if (ret)
 989       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 990
 991    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 992    PUSH_DATA (push, screen->nvsw->handle);
 993
 994    switch (dev->chipset & ~0xf) {
 995    case 0x130:
 996    case 0x120:
 997    case 0x110:
 998    case 0x100:
 999    case 0xf0:
1000       obj_class = NVF0_P2MF_CLASS;
1001       break;
1002    case 0xe0:
1003       obj_class = NVE4_P2MF_CLASS;
1004       break;
1005    default:
1006       obj_class = NVC0_M2MF_CLASS;
1007       break;
1008    }
1009    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
1010                             &screen->m2mf);
1011    if (ret)
1012       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
1013
1014    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
1015    PUSH_DATA (push, screen->m2mf->oclass);
1016    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1017       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1018       PUSH_DATA (push, 0xa0b5);
1019    }
1020
1021    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1022                             &screen->eng2d);
1023    if (ret)
1024       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1025
1026    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1027    PUSH_DATA (push, screen->eng2d->oclass);
1028    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1029    PUSH_DATA (push, 0);
1030    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1031    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1032    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1033    PUSH_DATA (push, 0);
1034    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1035    PUSH_DATA (push, 0);
1036    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1037    PUSH_DATA (push, 0x3f);
1038    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1039    PUSH_DATA (push, 1);
1040    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1041    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1042
1043    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1044    PUSH_DATAh(push, screen->fence.bo->offset + 16);
1045    PUSH_DATA (push, screen->fence.bo->offset + 16);
1046
1047    switch (dev->chipset & ~0xf) {
1048    case 0x130:
1049       switch (dev->chipset) {
1050       case 0x130:
1051       case 0x13b:
1052          obj_class = GP100_3D_CLASS;
1053          break;
1054       default:
1055          obj_class = GP102_3D_CLASS;
1056          break;
1057       }
1058       break;
1059    case 0x120:
1060       obj_class = GM200_3D_CLASS;
1061       break;
1062    case 0x110:
1063       obj_class = GM107_3D_CLASS;
1064       break;
1065    case 0x100:
1066    case 0xf0:
1067       obj_class = NVF0_3D_CLASS;
1068       break;
1069    case 0xe0:
1070       switch (dev->chipset) {
1071       case 0xea:
1072          obj_class = NVEA_3D_CLASS;
1073          break;
1074       default:
1075          obj_class = NVE4_3D_CLASS;
1076          break;
1077       }
1078       break;
1079    case 0xd0:
1080       obj_class = NVC8_3D_CLASS;
1081       break;
1082    case 0xc0:
1083    default:
1084       switch (dev->chipset) {
1085       case 0xc8:
1086          obj_class = NVC8_3D_CLASS;
1087          break;
1088       case 0xc1:
1089          obj_class = NVC1_3D_CLASS;
1090          break;
1091       default:
1092          obj_class = NVC0_3D_CLASS;
1093          break;
1094       }
1095       break;
1096    }
1097    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1098                             &screen->eng3d);
1099    if (ret)
1100       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1101    screen->base.class_3d = obj_class;
1102
1103    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1104    PUSH_DATA (push, screen->eng3d->oclass);
1105
1106    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1107    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1108
1109    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1110       /* kill shaders after about 1 second (at 100 MHz) */
1111       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1112       PUSH_DATA (push, 0x17);
1113    }
1114
1115    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1116                     screen->base.drm->version >= 0x01000101);
1117    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1118    for (i = 0; i < 8; ++i)
1119       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1120
1121    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1122    PUSH_DATA (push, 1);
1123
1124    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1125    PUSH_DATA (push, 0);
1126    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1127    PUSH_DATA (push, 0);
1128    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1129    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1130    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1131    PUSH_DATA (push, 0);
1132    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1133    PUSH_DATA (push, 1);
1134    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1135    PUSH_DATA (push, 1);
1136    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1137    PUSH_DATA (push, 1);
1138    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1139    PUSH_DATA (push, 0);
1140    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1141    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1142    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1143       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1144    } else {
1145       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1146       PUSH_DATA (push, 15);
1147    }
1148    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1149    PUSH_DATA (push, 8); /* 128 */
1150    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1151    PUSH_DATA (push, 1);
1152    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1153       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1154       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1155    }
1156
1157    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1158
1159    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1160    if (ret)
1161       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1162
1163    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1164    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1165                         &screen->uniform_bo);
1166    if (ret)
1167       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1168
1169    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1170
1171    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1172    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1173    PUSH_DATA (push, 256);
1174    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1175    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1176    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1177    PUSH_DATA (push, 0);
1178    PUSH_DATAf(push, 0.0f);
1179    PUSH_DATAf(push, 0.0f);
1180    PUSH_DATAf(push, 0.0f);
1181    PUSH_DATAf(push, 0.0f);
1182    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1183    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1184    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1185
1186    if (screen->base.drm->version >= 0x01000101) {
1187       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1188       if (ret)
1189          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1190    } else {
1191       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1192          value = (8 << 8) | 4;
1193       else
1194          value = (16 << 8) | 4;
1195    }
1196    screen->gpc_count = value & 0x000000ff;
1197    screen->mp_count = value >> 8;
1198    screen->mp_count_compute = screen->mp_count;
1199
1200    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1201    if (ret)
1202       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1203
1204    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1205    PUSH_DATAh(push, screen->tls->offset);
1206    PUSH_DATA (push, screen->tls->offset);
1207    PUSH_DATA (push, screen->tls->size >> 32);
1208    PUSH_DATA (push, screen->tls->size);
1209    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1210    PUSH_DATA (push, 0);
1211    /* Reduce likelihood of collision with real buffers by placing the hole at
1212     * the top of the 4G area. This will have to be dealt with for real
1213     * eventually by blocking off that area from the VM.
1214     */
1215    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1216    PUSH_DATA (push, 0xff << 24);
1217
1218    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1219       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1220                            &screen->poly_cache);
1221       if (ret)
1222          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1223
1224       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1225       PUSH_DATAh(push, screen->poly_cache->offset);
1226       PUSH_DATA (push, screen->poly_cache->offset);
1227       PUSH_DATA (push, 3);
1228    }
1229
1230    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1231                         &screen->txc);
1232    if (ret)
1233       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1234
1235    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1236    PUSH_DATAh(push, screen->txc->offset);
1237    PUSH_DATA (push, screen->txc->offset);
1238    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1239    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1240       screen->tic.maxwell = true;
1241       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1242          screen->tic.maxwell =
1243             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1244          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1245       }
1246    }
1247
1248    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1249    PUSH_DATAh(push, screen->txc->offset + 65536);
1250    PUSH_DATA (push, screen->txc->offset + 65536);
1251    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1252
1253    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1254    PUSH_DATA (push, 0);
1255    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1256    PUSH_DATA (push, 0);
1257    PUSH_DATA (push, 0);
1258    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1259    PUSH_DATA (push, 0x3f);
1260
1261    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1262    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1263    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1264    for (i = 0; i < 8 * 2; ++i)
1265       PUSH_DATA(push, 0);
1266    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1267    PUSH_DATA (push, 0);
1268    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1269    PUSH_DATA (push, 0);
1270
1271    /* neither scissors, viewport nor stencil mask should affect clears */
1272    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1273    PUSH_DATA (push, 0);
1274
1275    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1276    PUSH_DATA (push, 1);
1277    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1278       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1279       PUSH_DATAf(push, 0.0f);
1280       PUSH_DATAf(push, 1.0f);
1281    }
1282    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1283    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1284
1285    /* We use scissors instead of exact view volume clipping,
1286     * so they're always enabled.
1287     */
1288    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1289       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1290       PUSH_DATA (push, 1);
1291       PUSH_DATA (push, 8192 << 16);
1292       PUSH_DATA (push, 8192 << 16);
1293    }
1294
1295 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1296
1297    i = 0;
1298    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1299    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1300    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1301    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1302    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1303    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1304    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1305    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1306    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1307    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1308    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1309    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1310    MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1311    MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
1312    MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
1313    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1314
1315    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1316    PUSH_DATA (push, 1);
1317    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1318    PUSH_DATA (push, 1);
1319    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1320    PUSH_DATA (push, 0x40);
1321    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1322    PUSH_DATA (push, 0);
1323    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1324    PUSH_DATA (push, 0x30);
1325    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1326    PUSH_DATA (push, 3);
1327    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1328    PUSH_DATA (push, 0x20);
1329    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1330    PUSH_DATA (push, 0x00);
1331    screen->save_state.patch_vertices = 3;
1332
1333    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1334    PUSH_DATA (push, 0);
1335    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1336    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1337
1338    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1339
1340    if (nvc0_screen_init_compute(screen))
1341       goto fail;
1342
1343    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1344    for (i = 0; i < 5; ++i) {
1345       unsigned j = 0;
1346       for (j = 0; j < 16; j++)
1347          screen->cb_bindings[i][j].size = -1;
1348
1349       /* TIC and TSC entries for each unit (nve4+ only) */
1350       /* auxiliary constants (6 user clip planes, base instance id) */
1351       nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1352                              screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1353       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1354          unsigned j;
1355          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1356          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1357          for (j = 0; j < 8; ++j)
1358             PUSH_DATA(push, j);
1359       } else {
1360          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1361          PUSH_DATA (push, 0x54);
1362       }
1363
1364       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1365       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1366       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1367       PUSH_DATA (push, 0); /* 0 */
1368       PUSH_DATA (push, 0);
1369       PUSH_DATA (push, 1); /* 1 */
1370       PUSH_DATA (push, 0);
1371       PUSH_DATA (push, 0); /* 2 */
1372       PUSH_DATA (push, 1);
1373       PUSH_DATA (push, 1); /* 3 */
1374       PUSH_DATA (push, 1);
1375       PUSH_DATA (push, 2); /* 4 */
1376       PUSH_DATA (push, 0);
1377       PUSH_DATA (push, 3); /* 5 */
1378       PUSH_DATA (push, 0);
1379       PUSH_DATA (push, 2); /* 6 */
1380       PUSH_DATA (push, 1);
1381       PUSH_DATA (push, 3); /* 7 */
1382       PUSH_DATA (push, 1);
1383    }
1384    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1385    PUSH_DATA (push, 0);
1386
1387    PUSH_KICK (push);
1388
1389    screen->tic.entries = CALLOC(
1390          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1391          sizeof(void *));
1392    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1393    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1394
1395    if (!nvc0_blitter_create(screen))
1396       goto fail;
1397
1398    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1399
1400    return &screen->base;
1401
1402 fail:
1403    screen->base.base.context_create = NULL;
1404    return &screen->base;
1405 }
1406
1407 int
1408 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1409 {
1410    int i = screen->tic.next;
1411
1412    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1413       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1414
1415    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1416
1417    if (screen->tic.entries[i])
1418       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1419
1420    screen->tic.entries[i] = entry;
1421    return i;
1422 }
1423
1424 int
1425 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1426 {
1427    int i = screen->tsc.next;
1428
1429    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1430       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1431
1432    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1433
1434    if (screen->tsc.entries[i])
1435       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1436
1437    screen->tsc.entries[i] = entry;
1438    return i;
1439 }