src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/format/u_format.h"
  27 #include "util/format/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30 #include "compiler/nir/nir.h"
  31
  32 #include "nouveau_vp3_video.h"
  33
  34 #include "nvc0/nvc0_context.h"
  35 #include "nvc0/nvc0_screen.h"
  36
  37 #include "nvc0/mme/com9097.mme.h"
  38 #include "nvc0/mme/com90c0.mme.h"
  39
  40 #include "nv50/g80_texture.xml.h"
  41
  42 static bool
  43 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  44                                 enum pipe_format format,
  45                                 enum pipe_texture_target target,
  46                                 unsigned sample_count,
  47                                 unsigned storage_sample_count,
  48                                 unsigned bindings)
  49 {
  50    const struct util_format_description *desc = util_format_description(format);
  51
  52    if (sample_count > 8)
  53       return false;
  54    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  55       return false;
  56
  57    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  58       return false;
  59
  60    /* Short-circuit the rest of the logic -- this is used by the state tracker
  61     * to determine valid MS levels in a no-attachments scenario.
  62     */
  63    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  64       return true;
  65
  66    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  67       if (util_format_get_blocksizebits(format) == 3 * 32)
  68          return false;
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  79     */
  80    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  81         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  82        /* The claim is that this should work on GM107 but it doesn't. Need to
  83         * test further and figure out if it's a nouveau issue or a HW one.
  84        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  85         */
  86        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  87       return false;
  88
  89    /* shared is always supported */
  90    bindings &= ~(PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  94       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  95           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
  96          /* This should work on Fermi, but for currently unknown reasons it
  97           * does not and results in breaking reads from pbos. */
  98          return false;
  99       }
 100    }
 101
 102    return (( nvc0_format_table[format].usage |
 103             nvc0_vertex_format[format].usage) & bindings) == bindings;
 104 }
 105
 106 static int
 107 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 108 {
 109    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 110    const struct nouveau_screen *screen = nouveau_screen(pscreen);
 111    struct nouveau_device *dev = screen->device;
 112
 113    switch (param) {
 114    /* non-boolean caps */
 115    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 116       return 16384;
 117    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 118       return 15;
 119    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 120       return 12;
 121    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 122       return 2048;
 123    case PIPE_CAP_MIN_TEXEL_OFFSET:
 124       return -8;
 125    case PIPE_CAP_MAX_TEXEL_OFFSET:
 126       return 7;
 127    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 128       return -32;
 129    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 130       return 31;
 131    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 132       return 128 * 1024 * 1024;
 133    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 134       return 430;
 135    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 136       return 430;
 137    case PIPE_CAP_MAX_RENDER_TARGETS:
 138       return 8;
 139    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 140       return 1;
 141    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 142    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 143       return 8;
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 145       return 4;
 146    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 147    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 148       return 128;
 149    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 150    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 151       return 1024;
 152    case PIPE_CAP_MAX_VERTEX_STREAMS:
 153       return 4;
 154    case PIPE_CAP_MAX_GS_INVOCATIONS:
 155       return 32;
 156    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 157       return 1 << 27;
 158    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 159       return 2048;
 160    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 161       return 2047;
 162    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 163       return 256;
 164    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 165       if (class_3d < GM107_3D_CLASS)
 166          return 256; /* IMAGE bindings require alignment to 256 */
 167       return 16;
 168    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 169       return 16;
 170    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 171       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 172    case PIPE_CAP_MAX_VIEWPORTS:
 173       return NVC0_MAX_VIEWPORTS;
 174    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 175       return 4;
 176    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 177       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 178    case PIPE_CAP_ENDIANNESS:
 179       return PIPE_ENDIAN_LITTLE;
 180    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 181       return 30;
 182    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 183       return NVC0_MAX_WINDOW_RECTANGLES;
 184    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 185       return class_3d >= GM200_3D_CLASS ? 8 : 0;
 186    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 187       return 64 * 1024 * 1024;
 188    case PIPE_CAP_MAX_VARYINGS:
 189       /* NOTE: These only count our slots for GENERIC varyings.
 190        * The address space may be larger, but the actual hard limit seems to be
 191        * less than what the address space layout permits, so don't add TEXCOORD,
 192        * COLOR, etc. here.
 193        */
 194       return 0x1f0 / 16;
 195    case PIPE_CAP_MAX_VERTEX_BUFFERS:
 196       return 16;
 197
 198    /* supported caps */
 199    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 200    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 201    case PIPE_CAP_TEXTURE_SWIZZLE:
 202    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 203    case PIPE_CAP_NPOT_TEXTURES:
 204    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 205    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 206    case PIPE_CAP_ANISOTROPIC_FILTER:
 207    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 208    case PIPE_CAP_CUBE_MAP_ARRAY:
 209    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 210    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 211    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 212    case PIPE_CAP_POINT_SPRITE:
 213    case PIPE_CAP_TGSI_TEXCOORD:
 214    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 215    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 216    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 217    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 218    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 219    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 220    case PIPE_CAP_QUERY_TIMESTAMP:
 221    case PIPE_CAP_QUERY_TIME_ELAPSED:
 222    case PIPE_CAP_OCCLUSION_QUERY:
 223    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 224    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 225    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 226    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 227    case PIPE_CAP_INDEP_BLEND_ENABLE:
 228    case PIPE_CAP_INDEP_BLEND_FUNC:
 229    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 230    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 231    case PIPE_CAP_PRIMITIVE_RESTART:
 232    case PIPE_CAP_TGSI_INSTANCEID:
 233    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 234    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 235    case PIPE_CAP_CONDITIONAL_RENDER:
 236    case PIPE_CAP_TEXTURE_BARRIER:
 237    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 238    case PIPE_CAP_START_INSTANCE:
 239    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 240    case PIPE_CAP_DRAW_INDIRECT:
 241    case PIPE_CAP_USER_VERTEX_BUFFERS:
 242    case PIPE_CAP_TEXTURE_QUERY_LOD:
 243    case PIPE_CAP_SAMPLE_SHADING:
 244    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 245    case PIPE_CAP_TEXTURE_GATHER_SM5:
 246    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 247    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 248    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 249    case PIPE_CAP_CLIP_HALFZ:
 250    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 251    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 252    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 253    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 254    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 255    case PIPE_CAP_TGSI_TXQS:
 256    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 257    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 258    case PIPE_CAP_SHAREABLE_SHADERS:
 259    case PIPE_CAP_CLEAR_TEXTURE:
 260    case PIPE_CAP_DRAW_PARAMETERS:
 261    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 262    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 263    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 264    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 265    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 266    case PIPE_CAP_INVALIDATE_BUFFER:
 267    case PIPE_CAP_STRING_MARKER:
 268    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 269    case PIPE_CAP_CULL_DISTANCE:
 270    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 271    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 272    case PIPE_CAP_TGSI_VOTE:
 273    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 274    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 275    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 276    case PIPE_CAP_DOUBLES:
 277    case PIPE_CAP_INT64:
 278    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 279    case PIPE_CAP_TGSI_CLOCK:
 280    case PIPE_CAP_COMPUTE:
 281    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 282    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 283    case PIPE_CAP_QUERY_SO_OVERFLOW:
 284    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 285    case PIPE_CAP_TGSI_DIV:
 286    case PIPE_CAP_TGSI_ATOMINC_WRAP:
 287    case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
 288    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 289    case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 290    case PIPE_CAP_FLATSHADE:
 291    case PIPE_CAP_ALPHA_TEST:
 292    case PIPE_CAP_POINT_SIZE_FIXED:
 293    case PIPE_CAP_TWO_SIDED_COLOR:
 294    case PIPE_CAP_CLIP_PLANES:
 295    case PIPE_CAP_TEXTURE_SHADOW_LOD:
 296       return 1;
 297    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 298       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 299    case PIPE_CAP_FBFETCH:
 300       return class_3d >= NVE4_3D_CLASS ? 1 : 0; /* needs testing on fermi */
 301    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 302    case PIPE_CAP_TGSI_BALLOT:
 303       return class_3d >= NVE4_3D_CLASS;
 304    case PIPE_CAP_BINDLESS_TEXTURE:
 305       return class_3d >= NVE4_3D_CLASS;
 306    case PIPE_CAP_TGSI_ATOMFADD:
 307       return class_3d < GM107_3D_CLASS; /* needs additional lowering */
 308    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 309    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 310    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 311    case PIPE_CAP_POST_DEPTH_COVERAGE:
 312    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 313    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 314    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 315    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 316    case PIPE_CAP_VIEWPORT_SWIZZLE:
 317       return class_3d >= GM200_3D_CLASS;
 318    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 319       return class_3d >= GP100_3D_CLASS;
 320
 321    /* caps has to be turned on with nir */
 322    case PIPE_CAP_INT64_DIVMOD:
 323       return screen->prefer_nir ? 1 : 0;
 324
 325    /* unsupported caps */
 326    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 327    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 328    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 329    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 330    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 331    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 332    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 333    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 334    case PIPE_CAP_FAKE_SW_MSAA:
 335    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 336    case PIPE_CAP_VERTEXID_NOBASE:
 337    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 338    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 339    case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 340    case PIPE_CAP_GENERATE_MIPMAP:
 341    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 342    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 343    case PIPE_CAP_QUERY_MEMORY_INFO:
 344    case PIPE_CAP_PCI_GROUP:
 345    case PIPE_CAP_PCI_BUS:
 346    case PIPE_CAP_PCI_DEVICE:
 347    case PIPE_CAP_PCI_FUNCTION:
 348    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 349    case PIPE_CAP_NATIVE_FENCE_FD:
 350    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 351    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 352    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 353    case PIPE_CAP_MEMOBJ:
 354    case PIPE_CAP_LOAD_CONSTBUF:
 355    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 356    case PIPE_CAP_TILE_RASTER_ORDER:
 357    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 358    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 359    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 360    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 361    case PIPE_CAP_FENCE_SIGNAL:
 362    case PIPE_CAP_CONSTBUF0_FLAGS:
 363    case PIPE_CAP_PACKED_UNIFORMS:
 364    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 365    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 366    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 367    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 368    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 369    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 370    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 371    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 372    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 373    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 374    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 375    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 376    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 377    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 378    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 379    case PIPE_CAP_FBFETCH_COHERENT:
 380    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
 381    case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
 382    case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS: /* could be done */
 383    case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
 384    case PIPE_CAP_FRONTEND_NOOP:
 385    case PIPE_CAP_GL_SPIRV:
 386    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 387       return 0;
 388
 389    case PIPE_CAP_VENDOR_ID:
 390       return 0x10de;
 391    case PIPE_CAP_DEVICE_ID: {
 392       uint64_t device_id;
 393       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 394          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 395          return -1;
 396       }
 397       return device_id;
 398    }
 399    case PIPE_CAP_ACCELERATED:
 400       return 1;
 401    case PIPE_CAP_VIDEO_MEMORY:
 402       return dev->vram_size >> 20;
 403    case PIPE_CAP_UMA:
 404       return 0;
 405
 406    default:
 407       debug_printf("%s: unhandled cap %d\n", __func__, param);
 408       /* fallthrough */
 409    /* caps where we want the default value */
 410    case PIPE_CAP_DMABUF:
 411    case PIPE_CAP_ESSL_FEATURE_LEVEL:
 412    case PIPE_CAP_THROTTLE:
 413       return u_pipe_screen_get_param_defaults(pscreen, param);
 414    }
 415 }
 416
 417 static int
 418 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 419                              enum pipe_shader_type shader,
 420                              enum pipe_shader_cap param)
 421 {
 422    const struct nouveau_screen *screen = nouveau_screen(pscreen);
 423    const uint16_t class_3d = screen->class_3d;
 424
 425    switch (shader) {
 426    case PIPE_SHADER_VERTEX:
 427    case PIPE_SHADER_GEOMETRY:
 428    case PIPE_SHADER_FRAGMENT:
 429    case PIPE_SHADER_COMPUTE:
 430    case PIPE_SHADER_TESS_CTRL:
 431    case PIPE_SHADER_TESS_EVAL:
 432       break;
 433    default:
 434       return 0;
 435    }
 436
 437    switch (param) {
 438    case PIPE_SHADER_CAP_PREFERRED_IR:
 439       return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
 440    case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 441       uint32_t irs = 1 << PIPE_SHADER_IR_TGSI |
 442                      1 << PIPE_SHADER_IR_NIR;
 443       if (screen->force_enable_cl)
 444          irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED;
 445       return irs;
 446    }
 447    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 448    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 449    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 450    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 451       return 16384;
 452    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 453       return 16;
 454    case PIPE_SHADER_CAP_MAX_INPUTS:
 455       return 0x200 / 16;
 456    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 457       return 32;
 458    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 459       return NVC0_MAX_CONSTBUF_SIZE;
 460    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 461       return NVC0_MAX_PIPE_CONSTBUFS;
 462    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 463       return shader != PIPE_SHADER_FRAGMENT;
 464    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 465    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 466    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 467       return 1;
 468    case PIPE_SHADER_CAP_MAX_TEMPS:
 469       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 470    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 471       return 1;
 472    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 473       return 1;
 474    case PIPE_SHADER_CAP_SUBROUTINES:
 475       return 1;
 476    case PIPE_SHADER_CAP_INTEGERS:
 477       return 1;
 478    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 479       return 1;
 480    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 481       return 1;
 482    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 483       return 1;
 484    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 485    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 486    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 487    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 488    case PIPE_SHADER_CAP_INT64_ATOMICS:
 489    case PIPE_SHADER_CAP_FP16:
 490    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 491    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 492       return 0;
 493    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 494       return NVC0_MAX_BUFFERS;
 495    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 496       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 497    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 498       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 499    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 500       return 32;
 501    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 502       if (class_3d >= NVE4_3D_CLASS)
 503          return NVC0_MAX_IMAGES;
 504       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 505          return NVC0_MAX_IMAGES;
 506       return 0;
 507    default:
 508       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 509       return 0;
 510    }
 511 }
 512
 513 static float
 514 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 515 {
 516    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 517
 518    switch (param) {
 519    case PIPE_CAPF_MAX_LINE_WIDTH:
 520    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 521       return 10.0f;
 522    case PIPE_CAPF_MAX_POINT_WIDTH:
 523       return 63.0f;
 524    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 525       return 63.375f;
 526    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 527       return 16.0f;
 528    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 529       return 15.0f;
 530    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 531       return 0.0f;
 532    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 533       return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
 534    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 535       return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
 536    }
 537
 538    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 539    return 0.0f;
 540 }
 541
 542 static int
 543 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 544                               enum pipe_shader_ir ir_type,
 545                               enum pipe_compute_cap param, void *data)
 546 {
 547    struct nvc0_screen *screen = nvc0_screen(pscreen);
 548    const uint16_t obj_class = screen->compute->oclass;
 549
 550 #define RET(x) do {                  \
 551    if (data)                         \
 552       memcpy(data, x, sizeof(x));    \
 553    return sizeof(x);                 \
 554 } while (0)
 555
 556    switch (param) {
 557    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 558       RET((uint64_t []) { 3 });
 559    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 560       if (obj_class >= NVE4_COMPUTE_CLASS) {
 561          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 562       } else {
 563          RET(((uint64_t []) { 65535, 65535, 65535 }));
 564       }
 565    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 566       RET(((uint64_t []) { 1024, 1024, 64 }));
 567    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 568       RET((uint64_t []) { 1024 });
 569    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 570       if (obj_class >= NVE4_COMPUTE_CLASS) {
 571          RET((uint64_t []) { 1024 });
 572       } else {
 573          RET((uint64_t []) { 512 });
 574       }
 575    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 576       RET((uint64_t []) { 1ULL << 40 });
 577    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 578       switch (obj_class) {
 579       case GM200_COMPUTE_CLASS:
 580          RET((uint64_t []) { 96 << 10 });
 581          break;
 582       case GM107_COMPUTE_CLASS:
 583          RET((uint64_t []) { 64 << 10 });
 584          break;
 585       default:
 586          RET((uint64_t []) { 48 << 10 });
 587          break;
 588       }
 589    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 590       RET((uint64_t []) { 512 << 10 });
 591    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 592       RET((uint64_t []) { 4096 });
 593    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 594       RET((uint32_t []) { 32 });
 595    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 596       RET((uint64_t []) { 1ULL << 40 });
 597    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 598       RET((uint32_t []) { 0 });
 599    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 600       RET((uint32_t []) { screen->mp_count_compute });
 601    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 602       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 603    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 604       RET((uint32_t []) { 64 });
 605    default:
 606       return 0;
 607    }
 608
 609 #undef RET
 610 }
 611
 612 static void
 613 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
 614                                   unsigned sample_count,
 615                                   unsigned *width, unsigned *height)
 616 {
 617    switch (sample_count) {
 618    case 0:
 619    case 1:
 620       /* this could be 4x4, but the GL state tracker makes it difficult to
 621        * create a 1x MSAA texture and smaller grids save CB space */
 622       *width = 2;
 623       *height = 4;
 624       break;
 625    case 2:
 626       *width = 2;
 627       *height = 4;
 628       break;
 629    case 4:
 630       *width = 2;
 631       *height = 2;
 632       break;
 633    case 8:
 634       *width = 1;
 635       *height = 2;
 636       break;
 637    default:
 638       assert(0);
 639    }
 640 }
 641
 642 static void
 643 nvc0_screen_destroy(struct pipe_screen *pscreen)
 644 {
 645    struct nvc0_screen *screen = nvc0_screen(pscreen);
 646
 647    if (!nouveau_drm_screen_unref(&screen->base))
 648       return;
 649
 650    if (screen->base.fence.current) {
 651       struct nouveau_fence *current = NULL;
 652
 653       /* nouveau_fence_wait will create a new current fence, so wait on the
 654        * _current_ one, and remove both.
 655        */
 656       nouveau_fence_ref(screen->base.fence.current, &current);
 657       nouveau_fence_wait(current, NULL);
 658       nouveau_fence_ref(NULL, &current);
 659       nouveau_fence_ref(NULL, &screen->base.fence.current);
 660    }
 661    if (screen->base.pushbuf)
 662       screen->base.pushbuf->user_priv = NULL;
 663
 664    if (screen->blitter)
 665       nvc0_blitter_destroy(screen);
 666    if (screen->pm.prog) {
 667       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 668       nvc0_program_destroy(NULL, screen->pm.prog);
 669       FREE(screen->pm.prog);
 670    }
 671
 672    nouveau_bo_ref(NULL, &screen->text);
 673    nouveau_bo_ref(NULL, &screen->uniform_bo);
 674    nouveau_bo_ref(NULL, &screen->tls);
 675    nouveau_bo_ref(NULL, &screen->txc);
 676    nouveau_bo_ref(NULL, &screen->fence.bo);
 677    nouveau_bo_ref(NULL, &screen->poly_cache);
 678
 679    nouveau_heap_destroy(&screen->lib_code);
 680    nouveau_heap_destroy(&screen->text_heap);
 681
 682    FREE(screen->tic.entries);
 683
 684    nouveau_object_del(&screen->eng3d);
 685    nouveau_object_del(&screen->eng2d);
 686    nouveau_object_del(&screen->m2mf);
 687    nouveau_object_del(&screen->compute);
 688    nouveau_object_del(&screen->nvsw);
 689
 690    nouveau_screen_fini(&screen->base);
 691
 692    FREE(screen);
 693 }
 694
 695 static int
 696 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 697                      unsigned size, const uint32_t *data)
 698 {
 699    struct nouveau_pushbuf *push = screen->base.pushbuf;
 700
 701    size /= 4;
 702
 703    assert((pos + size) <= 0x800);
 704
 705    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 706    PUSH_DATA (push, (m - 0x3800) / 8);
 707    PUSH_DATA (push, pos);
 708    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 709    PUSH_DATA (push, pos);
 710    PUSH_DATAp(push, data, size);
 711
 712    return pos + size;
 713 }
 714
 715 static void
 716 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 717 {
 718    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 719    PUSH_DATA (push, 0xff);
 720    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 721    PUSH_DATA (push, 0xff);
 722    PUSH_DATA (push, 0xff);
 723    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 724    PUSH_DATA (push, 0xff);
 725    PUSH_DATA (push, 0xff);
 726    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 727    PUSH_DATA (push, 0x3f);
 728
 729    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 730    PUSH_DATA (push, (3 << 16) | 3);
 731    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 732    PUSH_DATA (push, (2 << 16) | 2);
 733
 734    if (obj_class < GM107_3D_CLASS) {
 735       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 736       PUSH_DATA (push, 0);
 737    }
 738    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 739    PUSH_DATA (push, 0x10);
 740    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 741    PUSH_DATA (push, 0x10);
 742    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 743    PUSH_DATA (push, 0x10);
 744    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 745    PUSH_DATA (push, 0x10);
 746    PUSH_DATA (push, 0x10);
 747    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 748    PUSH_DATA (push, 0x10);
 749    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 750    PUSH_DATA (push, 0xe);
 751
 752    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 753    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 754    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 755    PUSH_DATA (push, 0);
 756    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 757    PUSH_DATA (push, 3);
 758
 759    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 760    PUSH_DATA (push, 0x3fffff);
 761    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 762    PUSH_DATA (push, 1);
 763    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 764    PUSH_DATA (push, 1);
 765
 766    if (obj_class < GM107_3D_CLASS) {
 767       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 768       PUSH_DATA (push, 3);
 769
 770       if (obj_class >= NVE4_3D_CLASS) {
 771          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 772          PUSH_DATA (push, 1);
 773       }
 774    }
 775
 776    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 777     * are supposed to do */
 778 }
 779
 780 static void
 781 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 782 {
 783    struct nvc0_screen *screen = nvc0_screen(pscreen);
 784    struct nouveau_pushbuf *push = screen->base.pushbuf;
 785
 786    /* we need to do it after possible flush in MARK_RING */
 787    *sequence = ++screen->base.fence.sequence;
 788
 789    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 790    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 791    PUSH_DATAh(push, screen->fence.bo->offset);
 792    PUSH_DATA (push, screen->fence.bo->offset);
 793    PUSH_DATA (push, *sequence);
 794    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 795               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 796 }
 797
 798 static u32
 799 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 800 {
 801    struct nvc0_screen *screen = nvc0_screen(pscreen);
 802    return screen->fence.map[0];
 803 }
 804
 805 static int
 806 nvc0_screen_init_compute(struct nvc0_screen *screen)
 807 {
 808    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 809
 810    switch (screen->base.device->chipset & ~0xf) {
 811    case 0xc0:
 812    case 0xd0:
 813       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 814    case 0xe0:
 815    case 0xf0:
 816    case 0x100:
 817    case 0x110:
 818    case 0x120:
 819    case 0x130:
 820       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 821    default:
 822       return -1;
 823    }
 824 }
 825
 826 static int
 827 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 828                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 829 {
 830    struct nouveau_bo *bo = NULL;
 831    int ret;
 832    uint64_t size = (lpos + lneg) * 32 + cstack;
 833
 834    if (size >= (1 << 20)) {
 835       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 836       return -1;
 837    }
 838
 839    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 840    size  = align(size, 0x8000);
 841    size *= screen->mp_count;
 842
 843    size = align(size, 1 << 17);
 844
 845    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 846                         NULL, &bo);
 847    if (ret)
 848       return ret;
 849
 850    /* Make sure that the pushbuf has acquired a reference to the old tls
 851     * segment, as it may have commands that will reference it.
 852     */
 853    if (screen->tls)
 854       PUSH_REFN(screen->base.pushbuf, screen->tls,
 855                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
 856    nouveau_bo_ref(NULL, &screen->tls);
 857    screen->tls = bo;
 858    return 0;
 859 }
 860
 861 int
 862 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 863 {
 864    struct nouveau_pushbuf *push = screen->base.pushbuf;
 865    struct nouveau_bo *bo;
 866    int ret;
 867
 868    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 869                         1 << 17, size, NULL, &bo);
 870    if (ret)
 871       return ret;
 872
 873    /* Make sure that the pushbuf has acquired a reference to the old text
 874     * segment, as it may have commands that will reference it.
 875     */
 876    if (screen->text)
 877       PUSH_REFN(push, screen->text,
 878                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
 879    nouveau_bo_ref(NULL, &screen->text);
 880    screen->text = bo;
 881
 882    nouveau_heap_destroy(&screen->lib_code);
 883    nouveau_heap_destroy(&screen->text_heap);
 884
 885    /* XXX: getting a page fault at the end of the code buffer every few
 886     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 887     */
 888    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 889
 890    /* update the code segment setup */
 891    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 892    PUSH_DATAh(push, screen->text->offset);
 893    PUSH_DATA (push, screen->text->offset);
 894    if (screen->compute) {
 895       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 896       PUSH_DATAh(push, screen->text->offset);
 897       PUSH_DATA (push, screen->text->offset);
 898    }
 899
 900    return 0;
 901 }
 902
 903 void
 904 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
 905                        int stage, int index, int size, uint64_t addr)
 906 {
 907    assert(stage != 5);
 908
 909    struct nouveau_pushbuf *push = screen->base.pushbuf;
 910
 911    if (screen->base.class_3d >= GM107_3D_CLASS) {
 912       struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
 913
 914       // TODO: Better figure out the conditions in which this is needed
 915       bool serialize = binding->addr == addr && binding->size != size;
 916       if (can_serialize)
 917          serialize = serialize && *can_serialize;
 918       if (serialize) {
 919          IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 920          if (can_serialize)
 921             *can_serialize = false;
 922       }
 923
 924       binding->addr = addr;
 925       binding->size = size;
 926    }
 927
 928    if (size >= 0) {
 929       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 930       PUSH_DATA (push, size);
 931       PUSH_DATAh(push, addr);
 932       PUSH_DATA (push, addr);
 933    }
 934    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
 935 }
 936
 937 static const nir_shader_compiler_options nir_options = {
 938    .lower_fdiv = false,
 939    .lower_ffma = false,
 940    .fuse_ffma = false, /* nir doesn't track mad vs fma */
 941    .lower_flrp32 = true,
 942    .lower_flrp64 = true,
 943    .lower_fpow = false,
 944    .lower_fsat = false,
 945    .lower_fsqrt = false, // TODO: only before gm200
 946    .lower_fmod = true,
 947    .lower_bitfield_extract = false,
 948    .lower_bitfield_extract_to_shifts = false,
 949    .lower_bitfield_insert = false,
 950    .lower_bitfield_insert_to_shifts = false,
 951    .lower_bitfield_reverse = false,
 952    .lower_bit_count = false,
 953    .lower_ifind_msb = false,
 954    .lower_find_lsb = false,
 955    .lower_uadd_carry = true, // TODO
 956    .lower_usub_borrow = true, // TODO
 957    .lower_mul_high = false,
 958    .lower_negate = false,
 959    .lower_sub = true,
 960    .lower_scmp = true, // TODO: not implemented yet
 961    .lower_idiv = true,
 962    .lower_isign = false, // TODO
 963    .fdot_replicates = false, // TODO
 964    .lower_ffloor = false, // TODO
 965    .lower_ffract = true,
 966    .lower_fceil = false, // TODO
 967    .lower_ldexp = true,
 968    .lower_pack_half_2x16 = true,
 969    .lower_pack_unorm_2x16 = true,
 970    .lower_pack_snorm_2x16 = true,
 971    .lower_pack_unorm_4x8 = true,
 972    .lower_pack_snorm_4x8 = true,
 973    .lower_unpack_half_2x16 = true,
 974    .lower_unpack_unorm_2x16 = true,
 975    .lower_unpack_snorm_2x16 = true,
 976    .lower_unpack_unorm_4x8 = true,
 977    .lower_unpack_snorm_4x8 = true,
 978    .lower_extract_byte = true,
 979    .lower_extract_word = true,
 980    .lower_all_io_to_temps = false,
 981    .vertex_id_zero_based = false,
 982    .lower_base_vertex = false,
 983    .lower_helper_invocation = false,
 984    .lower_cs_local_index_from_id = true,
 985    .lower_cs_local_id_from_index = false,
 986    .lower_device_index_to_zero = false, // TODO
 987    .lower_wpos_pntc = false, // TODO
 988    .lower_hadd = true, // TODO
 989    .lower_add_sat = true, // TODO
 990    .use_interpolated_input_intrinsics = true,
 991    .lower_mul_2x32_64 = true, // TODO
 992    .max_unroll_iterations = 32,
 993    .lower_int64_options = nir_lower_ufind_msb64|nir_lower_divmod64, // TODO
 994    .lower_doubles_options = nir_lower_dmod, // TODO
 995    .lower_to_scalar = true,
 996 };
 997
 998 static const void *
 999 nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
1000                                  enum pipe_shader_ir ir,
1001                                  enum pipe_shader_type shader)
1002 {
1003    if (ir == PIPE_SHADER_IR_NIR)
1004       return &nir_options;
1005    return NULL;
1006 }
1007
1008 #define FAIL_SCREEN_INIT(str, err)                    \
1009    do {                                               \
1010       NOUVEAU_ERR(str, err);                          \
1011       goto fail;                                      \
1012    } while(0)
1013
1014 struct nouveau_screen *
1015 nvc0_screen_create(struct nouveau_device *dev)
1016 {
1017    struct nvc0_screen *screen;
1018    struct pipe_screen *pscreen;
1019    struct nouveau_object *chan;
1020    struct nouveau_pushbuf *push;
1021    uint64_t value;
1022    uint32_t obj_class;
1023    uint32_t flags;
1024    int ret;
1025    unsigned i;
1026
1027    switch (dev->chipset & ~0xf) {
1028    case 0xc0:
1029    case 0xd0:
1030    case 0xe0:
1031    case 0xf0:
1032    case 0x100:
1033    case 0x110:
1034    case 0x120:
1035    case 0x130:
1036       break;
1037    default:
1038       return NULL;
1039    }
1040
1041    screen = CALLOC_STRUCT(nvc0_screen);
1042    if (!screen)
1043       return NULL;
1044    pscreen = &screen->base.base;
1045    pscreen->destroy = nvc0_screen_destroy;
1046
1047    ret = nouveau_screen_init(&screen->base, dev);
1048    if (ret)
1049       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
1050    chan = screen->base.channel;
1051    push = screen->base.pushbuf;
1052    push->user_priv = screen;
1053    push->rsvd_kick = 5;
1054
1055    /* TODO: could this be higher on Kepler+? how does reclocking vs no
1056     * reclocking affect performance?
1057     * TODO: could this be higher on Fermi?
1058     */
1059    if (dev->chipset >= 0xe0)
1060       screen->base.transfer_pushbuf_threshold = 1024;
1061
1062    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
1063       PIPE_BIND_SHADER_BUFFER |
1064       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
1065       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
1066    screen->base.sysmem_bindings |=
1067       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
1068
1069    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
1070       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
1071       screen->base.vidmem_bindings = 0;
1072    }
1073
1074    pscreen->context_create = nvc0_create;
1075    pscreen->is_format_supported = nvc0_screen_is_format_supported;
1076    pscreen->get_param = nvc0_screen_get_param;
1077    pscreen->get_shader_param = nvc0_screen_get_shader_param;
1078    pscreen->get_paramf = nvc0_screen_get_paramf;
1079    pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
1080    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
1081    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
1082    /* nir stuff */
1083    pscreen->get_compiler_options = nvc0_screen_get_compiler_options;
1084
1085    nvc0_screen_init_resource_functions(pscreen);
1086
1087    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1088    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1089
1090    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
1091    if (screen->base.drm->version >= 0x01000202)
1092       flags |= NOUVEAU_BO_COHERENT;
1093
1094    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
1095    if (ret)
1096       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
1097    nouveau_bo_map(screen->fence.bo, 0, NULL);
1098    screen->fence.map = screen->fence.bo->map;
1099    screen->base.fence.emit = nvc0_screen_fence_emit;
1100    screen->base.fence.update = nvc0_screen_fence_update;
1101
1102
1103    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
1104                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
1105    if (ret)
1106       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
1107
1108    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
1109    PUSH_DATA (push, screen->nvsw->handle);
1110
1111    switch (dev->chipset & ~0xf) {
1112    case 0x130:
1113    case 0x120:
1114    case 0x110:
1115    case 0x100:
1116    case 0xf0:
1117       obj_class = NVF0_P2MF_CLASS;
1118       break;
1119    case 0xe0:
1120       obj_class = NVE4_P2MF_CLASS;
1121       break;
1122    default:
1123       obj_class = NVC0_M2MF_CLASS;
1124       break;
1125    }
1126    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
1127                             &screen->m2mf);
1128    if (ret)
1129       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
1130
1131    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
1132    PUSH_DATA (push, screen->m2mf->oclass);
1133    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1134       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1135       PUSH_DATA (push, 0xa0b5);
1136    }
1137
1138    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1139                             &screen->eng2d);
1140    if (ret)
1141       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1142
1143    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1144    PUSH_DATA (push, screen->eng2d->oclass);
1145    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1146    PUSH_DATA (push, 0);
1147    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1148    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1149    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1150    PUSH_DATA (push, 0);
1151    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1152    PUSH_DATA (push, 0);
1153    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1154    PUSH_DATA (push, 0x3f);
1155    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1156    PUSH_DATA (push, 1);
1157    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1158    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1159
1160    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1161    PUSH_DATAh(push, screen->fence.bo->offset + 16);
1162    PUSH_DATA (push, screen->fence.bo->offset + 16);
1163
1164    switch (dev->chipset & ~0xf) {
1165    case 0x130:
1166       switch (dev->chipset) {
1167       case 0x130:
1168       case 0x13b:
1169          obj_class = GP100_3D_CLASS;
1170          break;
1171       default:
1172          obj_class = GP102_3D_CLASS;
1173          break;
1174       }
1175       break;
1176    case 0x120:
1177       obj_class = GM200_3D_CLASS;
1178       break;
1179    case 0x110:
1180       obj_class = GM107_3D_CLASS;
1181       break;
1182    case 0x100:
1183    case 0xf0:
1184       obj_class = NVF0_3D_CLASS;
1185       break;
1186    case 0xe0:
1187       switch (dev->chipset) {
1188       case 0xea:
1189          obj_class = NVEA_3D_CLASS;
1190          break;
1191       default:
1192          obj_class = NVE4_3D_CLASS;
1193          break;
1194       }
1195       break;
1196    case 0xd0:
1197       obj_class = NVC8_3D_CLASS;
1198       break;
1199    case 0xc0:
1200    default:
1201       switch (dev->chipset) {
1202       case 0xc8:
1203          obj_class = NVC8_3D_CLASS;
1204          break;
1205       case 0xc1:
1206          obj_class = NVC1_3D_CLASS;
1207          break;
1208       default:
1209          obj_class = NVC0_3D_CLASS;
1210          break;
1211       }
1212       break;
1213    }
1214    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1215                             &screen->eng3d);
1216    if (ret)
1217       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1218    screen->base.class_3d = obj_class;
1219
1220    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1221    PUSH_DATA (push, screen->eng3d->oclass);
1222
1223    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1224    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1225
1226    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1227       /* kill shaders after about 1 second (at 100 MHz) */
1228       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1229       PUSH_DATA (push, 0x17);
1230    }
1231
1232    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1233                     screen->base.drm->version >= 0x01000101);
1234    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1235    for (i = 0; i < 8; ++i)
1236       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1237
1238    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1239    PUSH_DATA (push, 1);
1240
1241    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1242    PUSH_DATA (push, 0);
1243    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1244    PUSH_DATA (push, 0);
1245    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1246    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1247    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1248    PUSH_DATA (push, 0);
1249    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1250    PUSH_DATA (push, 1);
1251    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1252    PUSH_DATA (push, 1);
1253    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1254    PUSH_DATA (push, 1);
1255    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1256    PUSH_DATA (push, 0);
1257    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1258    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1259    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1260       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1261    } else {
1262       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1263       PUSH_DATA (push, 15);
1264    }
1265    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1266    PUSH_DATA (push, 8); /* 128 */
1267    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1268    PUSH_DATA (push, 1);
1269    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1270       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1271       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1272    }
1273
1274    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1275
1276    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1277    if (ret)
1278       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1279
1280    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1281    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1282                         &screen->uniform_bo);
1283    if (ret)
1284       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1285
1286    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1287
1288    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1289    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1290    PUSH_DATA (push, 256);
1291    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1292    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1293    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1294    PUSH_DATA (push, 0);
1295    PUSH_DATAf(push, 0.0f);
1296    PUSH_DATAf(push, 0.0f);
1297    PUSH_DATAf(push, 0.0f);
1298    PUSH_DATAf(push, 0.0f);
1299    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1300    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1301    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1302
1303    if (screen->base.drm->version >= 0x01000101) {
1304       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1305       if (ret)
1306          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1307    } else {
1308       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1309          value = (8 << 8) | 4;
1310       else
1311          value = (16 << 8) | 4;
1312    }
1313    screen->gpc_count = value & 0x000000ff;
1314    screen->mp_count = value >> 8;
1315    screen->mp_count_compute = screen->mp_count;
1316
1317    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1318    if (ret)
1319       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1320
1321    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1322    PUSH_DATAh(push, screen->tls->offset);
1323    PUSH_DATA (push, screen->tls->offset);
1324    PUSH_DATA (push, screen->tls->size >> 32);
1325    PUSH_DATA (push, screen->tls->size);
1326    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1327    PUSH_DATA (push, 0);
1328    /* Reduce likelihood of collision with real buffers by placing the hole at
1329     * the top of the 4G area. This will have to be dealt with for real
1330     * eventually by blocking off that area from the VM.
1331     */
1332    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1333    PUSH_DATA (push, 0xff << 24);
1334
1335    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1336       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1337                            &screen->poly_cache);
1338       if (ret)
1339          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1340
1341       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1342       PUSH_DATAh(push, screen->poly_cache->offset);
1343       PUSH_DATA (push, screen->poly_cache->offset);
1344       PUSH_DATA (push, 3);
1345    }
1346
1347    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1348                         &screen->txc);
1349    if (ret)
1350       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1351
1352    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1353    PUSH_DATAh(push, screen->txc->offset);
1354    PUSH_DATA (push, screen->txc->offset);
1355    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1356    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1357       screen->tic.maxwell = true;
1358       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1359          screen->tic.maxwell =
1360             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1361          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1362       }
1363    }
1364
1365    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1366    PUSH_DATAh(push, screen->txc->offset + 65536);
1367    PUSH_DATA (push, screen->txc->offset + 65536);
1368    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1369
1370    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1371    PUSH_DATA (push, 0);
1372    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1373    PUSH_DATA (push, 0);
1374    PUSH_DATA (push, 0);
1375    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1376    PUSH_DATA (push, 0x3f);
1377
1378    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1379    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1380    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1381    for (i = 0; i < 8 * 2; ++i)
1382       PUSH_DATA(push, 0);
1383    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1384    PUSH_DATA (push, 0);
1385    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1386    PUSH_DATA (push, 0);
1387
1388    /* neither scissors, viewport nor stencil mask should affect clears */
1389    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1390    PUSH_DATA (push, 0);
1391
1392    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1393    PUSH_DATA (push, 1);
1394    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1395       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1396       PUSH_DATAf(push, 0.0f);
1397       PUSH_DATAf(push, 1.0f);
1398    }
1399    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1400    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1401
1402    /* We use scissors instead of exact view volume clipping,
1403     * so they're always enabled.
1404     */
1405    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1406       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1407       PUSH_DATA (push, 1);
1408       PUSH_DATA (push, 16384 << 16);
1409       PUSH_DATA (push, 16384 << 16);
1410    }
1411
1412 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1413
1414    i = 0;
1415    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1416    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1417    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1418    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1419    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1420    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1421    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1422    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1423    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1424    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1425    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1426    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1427    MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1428    MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
1429    MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
1430    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1431
1432    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1433    PUSH_DATA (push, 1);
1434    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1435    PUSH_DATA (push, 1);
1436    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1437    PUSH_DATA (push, 0x40);
1438    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1439    PUSH_DATA (push, 0);
1440    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1441    PUSH_DATA (push, 0x30);
1442    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1443    PUSH_DATA (push, 3);
1444    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1445    PUSH_DATA (push, 0x20);
1446    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1447    PUSH_DATA (push, 0x00);
1448    screen->save_state.patch_vertices = 3;
1449
1450    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1451    PUSH_DATA (push, 0);
1452    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1453    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1454
1455    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1456
1457    if (nvc0_screen_init_compute(screen))
1458       goto fail;
1459
1460    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1461    for (i = 0; i < 5; ++i) {
1462       unsigned j = 0;
1463       for (j = 0; j < 16; j++)
1464          screen->cb_bindings[i][j].size = -1;
1465
1466       /* TIC and TSC entries for each unit (nve4+ only) */
1467       /* auxiliary constants (6 user clip planes, base instance id) */
1468       nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1469                              screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1470       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1471          unsigned j;
1472          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1473          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1474          for (j = 0; j < 8; ++j)
1475             PUSH_DATA(push, j);
1476       } else {
1477          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1478          PUSH_DATA (push, 0x54);
1479       }
1480
1481       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1482       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1483       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1484       PUSH_DATA (push, 0); /* 0 */
1485       PUSH_DATA (push, 0);
1486       PUSH_DATA (push, 1); /* 1 */
1487       PUSH_DATA (push, 0);
1488       PUSH_DATA (push, 0); /* 2 */
1489       PUSH_DATA (push, 1);
1490       PUSH_DATA (push, 1); /* 3 */
1491       PUSH_DATA (push, 1);
1492       PUSH_DATA (push, 2); /* 4 */
1493       PUSH_DATA (push, 0);
1494       PUSH_DATA (push, 3); /* 5 */
1495       PUSH_DATA (push, 0);
1496       PUSH_DATA (push, 2); /* 6 */
1497       PUSH_DATA (push, 1);
1498       PUSH_DATA (push, 3); /* 7 */
1499       PUSH_DATA (push, 1);
1500    }
1501    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1502    PUSH_DATA (push, 0);
1503
1504    PUSH_KICK (push);
1505
1506    screen->tic.entries = CALLOC(
1507          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1508          sizeof(void *));
1509    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1510    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1511
1512    if (!nvc0_blitter_create(screen))
1513       goto fail;
1514
1515    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1516
1517    return &screen->base;
1518
1519 fail:
1520    screen->base.base.context_create = NULL;
1521    return &screen->base;
1522 }
1523
1524 int
1525 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1526 {
1527    int i = screen->tic.next;
1528
1529    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1530       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1531
1532    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1533
1534    if (screen->tic.entries[i])
1535       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1536
1537    screen->tic.entries[i] = entry;
1538    return i;
1539 }
1540
1541 int
1542 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1543 {
1544    int i = screen->tsc.next;
1545
1546    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1547       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1548
1549    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1550
1551    if (screen->tsc.entries[i])
1552       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1553
1554    screen->tsc.entries[i] = entry;
1555    return i;
1556 }