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gallium: add PIPE_SHADER_CAP_MAX_OUTPUTS and use it in st/mesa
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include "util/u_format.h"
26 #include "util/u_format_s3tc.h"
27 #include "pipe/p_screen.h"
28
29 #include "vl/vl_decoder.h"
30 #include "vl/vl_video_buffer.h"
31
32 #include "nouveau_vp3_video.h"
33
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_screen.h"
36
37 #include "nvc0/mme/com9097.mme.h"
38
39 static boolean
40 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
41 enum pipe_format format,
42 enum pipe_texture_target target,
43 unsigned sample_count,
44 unsigned bindings)
45 {
46 if (sample_count > 8)
47 return FALSE;
48 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
49 return FALSE;
50
51 if (!util_format_is_supported(format, bindings))
52 return FALSE;
53
54 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
55 if (util_format_get_blocksizebits(format) == 3 * 32)
56 return FALSE;
57
58 /* transfers & shared are always supported */
59 bindings &= ~(PIPE_BIND_TRANSFER_READ |
60 PIPE_BIND_TRANSFER_WRITE |
61 PIPE_BIND_SHARED);
62
63 return (nvc0_format_table[format].usage & bindings) == bindings;
64 }
65
66 static int
67 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
68 {
69 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
70 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
71
72 switch (param) {
73 /* non-boolean caps */
74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
76 return 15;
77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
78 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
80 return 2048;
81 case PIPE_CAP_MIN_TEXEL_OFFSET:
82 return -8;
83 case PIPE_CAP_MAX_TEXEL_OFFSET:
84 return 7;
85 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
86 return -32;
87 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
88 return 31;
89 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
90 return 65536;
91 case PIPE_CAP_GLSL_FEATURE_LEVEL:
92 return 400;
93 case PIPE_CAP_MAX_RENDER_TARGETS:
94 return 8;
95 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
96 return 1;
97 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
98 return 4;
99 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
100 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
101 return 128;
102 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
103 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
104 return 1024;
105 case PIPE_CAP_MAX_VERTEX_STREAMS:
106 return 4;
107 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
108 return 2048;
109 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
110 return 256;
111 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
112 return 1; /* 256 for binding as RT, but that's not possible in GL */
113 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
114 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
115 case PIPE_CAP_MAX_VIEWPORTS:
116 return NVC0_MAX_VIEWPORTS;
117 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
118 return 4;
119 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
120 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
121 case PIPE_CAP_ENDIANNESS:
122 return PIPE_ENDIAN_LITTLE;
123
124 /* supported caps */
125 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
126 case PIPE_CAP_TEXTURE_SWIZZLE:
127 case PIPE_CAP_TEXTURE_SHADOW_MAP:
128 case PIPE_CAP_NPOT_TEXTURES:
129 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
130 case PIPE_CAP_ANISOTROPIC_FILTER:
131 case PIPE_CAP_SEAMLESS_CUBE_MAP:
132 case PIPE_CAP_CUBE_MAP_ARRAY:
133 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
134 case PIPE_CAP_TEXTURE_MULTISAMPLE:
135 case PIPE_CAP_TWO_SIDED_STENCIL:
136 case PIPE_CAP_DEPTH_CLIP_DISABLE:
137 case PIPE_CAP_POINT_SPRITE:
138 case PIPE_CAP_TGSI_TEXCOORD:
139 case PIPE_CAP_SM3:
140 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
141 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
142 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
143 case PIPE_CAP_QUERY_TIMESTAMP:
144 case PIPE_CAP_QUERY_TIME_ELAPSED:
145 case PIPE_CAP_OCCLUSION_QUERY:
146 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
147 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
148 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
149 case PIPE_CAP_INDEP_BLEND_ENABLE:
150 case PIPE_CAP_INDEP_BLEND_FUNC:
151 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
152 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
153 case PIPE_CAP_PRIMITIVE_RESTART:
154 case PIPE_CAP_TGSI_INSTANCEID:
155 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
156 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
157 case PIPE_CAP_CONDITIONAL_RENDER:
158 case PIPE_CAP_TEXTURE_BARRIER:
159 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
160 case PIPE_CAP_START_INSTANCE:
161 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
162 case PIPE_CAP_DRAW_INDIRECT:
163 case PIPE_CAP_USER_CONSTANT_BUFFERS:
164 case PIPE_CAP_USER_INDEX_BUFFERS:
165 case PIPE_CAP_USER_VERTEX_BUFFERS:
166 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
167 case PIPE_CAP_TEXTURE_QUERY_LOD:
168 case PIPE_CAP_SAMPLE_SHADING:
169 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
170 case PIPE_CAP_TEXTURE_GATHER_SM5:
171 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
172 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
173 case PIPE_CAP_SAMPLER_VIEW_TARGET:
174 return 1;
175 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
176 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
177 case PIPE_CAP_COMPUTE:
178 return (class_3d == NVE4_3D_CLASS) ? 1 : 0;
179
180 /* unsupported caps */
181 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
182 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
183 case PIPE_CAP_SHADER_STENCIL_EXPORT:
184 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
185 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
186 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
187 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
188 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
189 case PIPE_CAP_FAKE_SW_MSAA:
190 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
191 return 0;
192
193 case PIPE_CAP_VENDOR_ID:
194 return 0x10de;
195 case PIPE_CAP_DEVICE_ID: {
196 uint64_t device_id;
197 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
198 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
199 return -1;
200 }
201 return device_id;
202 }
203 case PIPE_CAP_ACCELERATED:
204 return 1;
205 case PIPE_CAP_VIDEO_MEMORY:
206 return dev->vram_size >> 20;
207 case PIPE_CAP_UMA:
208 return 0;
209 }
210
211 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
212 return 0;
213 }
214
215 static int
216 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
217 enum pipe_shader_cap param)
218 {
219 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
220
221 switch (shader) {
222 case PIPE_SHADER_VERTEX:
223 /*
224 case PIPE_SHADER_TESSELLATION_CONTROL:
225 case PIPE_SHADER_TESSELLATION_EVALUATION:
226 */
227 case PIPE_SHADER_GEOMETRY:
228 case PIPE_SHADER_FRAGMENT:
229 break;
230 case PIPE_SHADER_COMPUTE:
231 if (class_3d != NVE4_3D_CLASS)
232 return 0;
233 break;
234 default:
235 return 0;
236 }
237
238 switch (param) {
239 case PIPE_SHADER_CAP_PREFERRED_IR:
240 return PIPE_SHADER_IR_TGSI;
241 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
242 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
243 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
244 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
245 return 16384;
246 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
247 return 16;
248 case PIPE_SHADER_CAP_MAX_INPUTS:
249 if (shader == PIPE_SHADER_VERTEX)
250 return 32;
251 /* NOTE: These only count our slots for GENERIC varyings.
252 * The address space may be larger, but the actual hard limit seems to be
253 * less than what the address space layout permits, so don't add TEXCOORD,
254 * COLOR, etc. here.
255 */
256 if (shader == PIPE_SHADER_FRAGMENT)
257 return 0x1f0 / 16;
258 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
259 * and excludes 0x60 per-patch inputs.
260 */
261 return 0x200 / 16;
262 case PIPE_SHADER_CAP_MAX_OUTPUTS:
263 return 32;
264 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
265 return 65536;
266 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
267 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
268 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
269 return NVC0_MAX_PIPE_CONSTBUFS;
270 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
271 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
272 return shader != PIPE_SHADER_FRAGMENT;
273 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
274 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
275 return 1;
276 case PIPE_SHADER_CAP_MAX_PREDS:
277 return 0;
278 case PIPE_SHADER_CAP_MAX_TEMPS:
279 return NVC0_CAP_MAX_PROGRAM_TEMPS;
280 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
281 return 1;
282 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
283 return 0;
284 case PIPE_SHADER_CAP_SUBROUTINES:
285 return 1;
286 case PIPE_SHADER_CAP_INTEGERS:
287 return 1;
288 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
289 return 16; /* would be 32 in linked (OpenGL-style) mode */
290 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
291 return 16; /* XXX not sure if more are really safe */
292 default:
293 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
294 return 0;
295 }
296 }
297
298 static float
299 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
300 {
301 switch (param) {
302 case PIPE_CAPF_MAX_LINE_WIDTH:
303 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
304 return 10.0f;
305 case PIPE_CAPF_MAX_POINT_WIDTH:
306 return 63.0f;
307 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
308 return 63.375f;
309 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
310 return 16.0f;
311 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
312 return 15.0f;
313 case PIPE_CAPF_GUARD_BAND_LEFT:
314 case PIPE_CAPF_GUARD_BAND_TOP:
315 return 0.0f;
316 case PIPE_CAPF_GUARD_BAND_RIGHT:
317 case PIPE_CAPF_GUARD_BAND_BOTTOM:
318 return 0.0f; /* that or infinity */
319 }
320
321 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
322 return 0.0f;
323 }
324
325 static int
326 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
327 enum pipe_compute_cap param, void *data)
328 {
329 uint64_t *data64 = (uint64_t *)data;
330 const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
331
332 switch (param) {
333 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
334 data64[0] = 3;
335 return 8;
336 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
337 data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
338 data64[1] = 65535;
339 data64[2] = 65535;
340 return 24;
341 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
342 data64[0] = 1024;
343 data64[1] = 1024;
344 data64[2] = 64;
345 return 24;
346 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
347 data64[0] = 1024;
348 return 8;
349 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
350 data64[0] = (uint64_t)1 << 40;
351 return 8;
352 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
353 data64[0] = 48 << 10;
354 return 8;
355 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
356 data64[0] = 512 << 10;
357 return 8;
358 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
359 data64[0] = 4096;
360 return 8;
361 default:
362 return 0;
363 }
364 }
365
366 static void
367 nvc0_screen_destroy(struct pipe_screen *pscreen)
368 {
369 struct nvc0_screen *screen = nvc0_screen(pscreen);
370
371 if (!nouveau_drm_screen_unref(&screen->base))
372 return;
373
374 if (screen->base.fence.current) {
375 struct nouveau_fence *current = NULL;
376
377 /* nouveau_fence_wait will create a new current fence, so wait on the
378 * _current_ one, and remove both.
379 */
380 nouveau_fence_ref(screen->base.fence.current, &current);
381 nouveau_fence_wait(current);
382 nouveau_fence_ref(NULL, &current);
383 nouveau_fence_ref(NULL, &screen->base.fence.current);
384 }
385 if (screen->base.pushbuf)
386 screen->base.pushbuf->user_priv = NULL;
387
388 if (screen->blitter)
389 nvc0_blitter_destroy(screen);
390 if (screen->pm.prog) {
391 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
392 nvc0_program_destroy(NULL, screen->pm.prog);
393 }
394
395 nouveau_bo_ref(NULL, &screen->text);
396 nouveau_bo_ref(NULL, &screen->uniform_bo);
397 nouveau_bo_ref(NULL, &screen->tls);
398 nouveau_bo_ref(NULL, &screen->txc);
399 nouveau_bo_ref(NULL, &screen->fence.bo);
400 nouveau_bo_ref(NULL, &screen->poly_cache);
401 nouveau_bo_ref(NULL, &screen->parm);
402
403 nouveau_heap_destroy(&screen->lib_code);
404 nouveau_heap_destroy(&screen->text_heap);
405
406 FREE(screen->tic.entries);
407
408 nouveau_mm_destroy(screen->mm_VRAM_fe0);
409
410 nouveau_object_del(&screen->eng3d);
411 nouveau_object_del(&screen->eng2d);
412 nouveau_object_del(&screen->m2mf);
413 nouveau_object_del(&screen->compute);
414 nouveau_object_del(&screen->nvsw);
415
416 nouveau_screen_fini(&screen->base);
417
418 FREE(screen);
419 }
420
421 static int
422 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
423 unsigned size, const uint32_t *data)
424 {
425 struct nouveau_pushbuf *push = screen->base.pushbuf;
426
427 size /= 4;
428
429 assert((pos + size) <= 0x800);
430
431 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
432 PUSH_DATA (push, (m - 0x3800) / 8);
433 PUSH_DATA (push, pos);
434 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
435 PUSH_DATA (push, pos);
436 PUSH_DATAp(push, data, size);
437
438 return pos + size;
439 }
440
441 static void
442 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
443 {
444 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
445 PUSH_DATA (push, 0xff);
446 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
447 PUSH_DATA (push, 0xff);
448 PUSH_DATA (push, 0xff);
449 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
450 PUSH_DATA (push, 0xff);
451 PUSH_DATA (push, 0xff);
452 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
453 PUSH_DATA (push, 0x3f);
454
455 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
456 PUSH_DATA (push, (3 << 16) | 3);
457 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
458 PUSH_DATA (push, (2 << 16) | 2);
459
460 if (obj_class < GM107_3D_CLASS) {
461 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
462 PUSH_DATA (push, 0);
463 }
464 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
465 PUSH_DATA (push, 0x10);
466 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
467 PUSH_DATA (push, 0x10);
468 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
469 PUSH_DATA (push, 0x10);
470 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
471 PUSH_DATA (push, 0x10);
472 PUSH_DATA (push, 0x10);
473 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
474 PUSH_DATA (push, 0x10);
475 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
476 PUSH_DATA (push, 0xe);
477
478 BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
479 PUSH_DATA (push, 1 << 12);
480 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
481 PUSH_DATA (push, 0);
482 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
483 PUSH_DATA (push, 3);
484
485 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
486 PUSH_DATA (push, 0x3fffff);
487 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
488 PUSH_DATA (push, 1);
489 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
490 PUSH_DATA (push, 1);
491
492 if (obj_class < GM107_3D_CLASS) {
493 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
494 PUSH_DATA (push, 3);
495
496 if (obj_class >= NVE4_3D_CLASS) {
497 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
498 PUSH_DATA (push, 1);
499 }
500 }
501
502 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
503 * are supposed to do */
504 }
505
506 static void
507 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
508 {
509 struct nvc0_screen *screen = nvc0_screen(pscreen);
510 struct nouveau_pushbuf *push = screen->base.pushbuf;
511
512 /* we need to do it after possible flush in MARK_RING */
513 *sequence = ++screen->base.fence.sequence;
514
515 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
516 PUSH_DATAh(push, screen->fence.bo->offset);
517 PUSH_DATA (push, screen->fence.bo->offset);
518 PUSH_DATA (push, *sequence);
519 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
520 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
521 }
522
523 static u32
524 nvc0_screen_fence_update(struct pipe_screen *pscreen)
525 {
526 struct nvc0_screen *screen = nvc0_screen(pscreen);
527 return screen->fence.map[0];
528 }
529
530 static int
531 nvc0_screen_init_compute(struct nvc0_screen *screen)
532 {
533 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
534
535 switch (screen->base.device->chipset & ~0xf) {
536 case 0xc0:
537 case 0xd0:
538 /* Using COMPUTE has weird effects on 3D state, we need to
539 * investigate this further before enabling it by default.
540 */
541 if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
542 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
543 return 0;
544 case 0xe0:
545 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
546 case 0xf0:
547 case 0x100:
548 case 0x110:
549 return 0;
550 default:
551 return -1;
552 }
553 }
554
555 boolean
556 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
557 uint32_t lpos, uint32_t lneg, uint32_t cstack)
558 {
559 struct nouveau_bo *bo = NULL;
560 int ret;
561 uint64_t size = (lpos + lneg) * 32 + cstack;
562
563 if (size >= (1 << 20)) {
564 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
565 return FALSE;
566 }
567
568 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
569 size = align(size, 0x8000);
570 size *= screen->mp_count;
571
572 size = align(size, 1 << 17);
573
574 ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
575 NULL, &bo);
576 if (ret) {
577 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
578 return FALSE;
579 }
580 nouveau_bo_ref(NULL, &screen->tls);
581 screen->tls = bo;
582 return TRUE;
583 }
584
585 #define FAIL_SCREEN_INIT(str, err) \
586 do { \
587 NOUVEAU_ERR(str, err); \
588 nvc0_screen_destroy(pscreen); \
589 return NULL; \
590 } while(0)
591
592 struct pipe_screen *
593 nvc0_screen_create(struct nouveau_device *dev)
594 {
595 struct nvc0_screen *screen;
596 struct pipe_screen *pscreen;
597 struct nouveau_object *chan;
598 struct nouveau_pushbuf *push;
599 uint64_t value;
600 uint32_t obj_class;
601 int ret;
602 unsigned i;
603 union nouveau_bo_config mm_config;
604
605 switch (dev->chipset & ~0xf) {
606 case 0xc0:
607 case 0xd0:
608 case 0xe0:
609 case 0xf0:
610 case 0x100:
611 case 0x110:
612 break;
613 default:
614 return NULL;
615 }
616
617 screen = CALLOC_STRUCT(nvc0_screen);
618 if (!screen)
619 return NULL;
620 pscreen = &screen->base.base;
621
622 ret = nouveau_screen_init(&screen->base, dev);
623 if (ret) {
624 nvc0_screen_destroy(pscreen);
625 return NULL;
626 }
627 chan = screen->base.channel;
628 push = screen->base.pushbuf;
629 push->user_priv = screen;
630 push->rsvd_kick = 5;
631
632 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
633 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
634 PIPE_BIND_COMMAND_ARGS_BUFFER;
635 screen->base.sysmem_bindings |=
636 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
637
638 pscreen->destroy = nvc0_screen_destroy;
639 pscreen->context_create = nvc0_create;
640 pscreen->is_format_supported = nvc0_screen_is_format_supported;
641 pscreen->get_param = nvc0_screen_get_param;
642 pscreen->get_shader_param = nvc0_screen_get_shader_param;
643 pscreen->get_paramf = nvc0_screen_get_paramf;
644 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
645
646 nvc0_screen_init_resource_functions(pscreen);
647
648 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
649 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
650
651 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
652 &screen->fence.bo);
653 if (ret)
654 goto fail;
655 nouveau_bo_map(screen->fence.bo, 0, NULL);
656 screen->fence.map = screen->fence.bo->map;
657 screen->base.fence.emit = nvc0_screen_fence_emit;
658 screen->base.fence.update = nvc0_screen_fence_update;
659
660
661 ret = nouveau_object_new(chan,
662 (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
663 NULL, 0, &screen->nvsw);
664 if (ret)
665 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
666
667
668 switch (dev->chipset & ~0xf) {
669 case 0x110:
670 case 0x100:
671 case 0xf0:
672 obj_class = NVF0_P2MF_CLASS;
673 break;
674 case 0xe0:
675 obj_class = NVE4_P2MF_CLASS;
676 break;
677 default:
678 obj_class = NVC0_M2MF_CLASS;
679 break;
680 }
681 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
682 &screen->m2mf);
683 if (ret)
684 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
685
686 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
687 PUSH_DATA (push, screen->m2mf->oclass);
688 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
689 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
690 PUSH_DATA (push, 0xa0b5);
691 }
692
693 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
694 &screen->eng2d);
695 if (ret)
696 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
697
698 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
699 PUSH_DATA (push, screen->eng2d->oclass);
700 BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
701 PUSH_DATA (push, 0);
702 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
703 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
704 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
705 PUSH_DATA (push, 0);
706 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
707 PUSH_DATA (push, 0);
708 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
709 PUSH_DATA (push, 0x3f);
710 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
711 PUSH_DATA (push, 1);
712 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
713 PUSH_DATA (push, NVC0_2D_COND_MODE_ALWAYS);
714
715 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
716 PUSH_DATAh(push, screen->fence.bo->offset + 16);
717 PUSH_DATA (push, screen->fence.bo->offset + 16);
718
719 switch (dev->chipset & ~0xf) {
720 case 0x110:
721 obj_class = GM107_3D_CLASS;
722 break;
723 case 0x100:
724 case 0xf0:
725 obj_class = NVF0_3D_CLASS;
726 break;
727 case 0xe0:
728 switch (dev->chipset) {
729 case 0xea:
730 obj_class = NVEA_3D_CLASS;
731 break;
732 default:
733 obj_class = NVE4_3D_CLASS;
734 break;
735 }
736 break;
737 case 0xd0:
738 obj_class = NVC8_3D_CLASS;
739 break;
740 case 0xc0:
741 default:
742 switch (dev->chipset) {
743 case 0xc8:
744 obj_class = NVC8_3D_CLASS;
745 break;
746 case 0xc1:
747 obj_class = NVC1_3D_CLASS;
748 break;
749 default:
750 obj_class = NVC0_3D_CLASS;
751 break;
752 }
753 break;
754 }
755 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
756 &screen->eng3d);
757 if (ret)
758 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
759 screen->base.class_3d = obj_class;
760
761 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
762 PUSH_DATA (push, screen->eng3d->oclass);
763
764 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
765 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
766
767 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
768 /* kill shaders after about 1 second (at 100 MHz) */
769 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
770 PUSH_DATA (push, 0x17);
771 }
772
773 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
774 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
775 for (i = 0; i < 8; ++i)
776 PUSH_DATA(push, dev->drm_version >= 0x01000101);
777
778 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
779 PUSH_DATA (push, 1);
780
781 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
782 PUSH_DATA (push, 0);
783 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
784 PUSH_DATA (push, 0);
785 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
786 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
787 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
788 PUSH_DATA (push, 0);
789 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
790 PUSH_DATA (push, 1);
791 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
792 PUSH_DATA (push, 0);
793 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
794 PUSH_DATA (push, 1);
795 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
796 PUSH_DATA (push, 1);
797 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
798 PUSH_DATA (push, 0);
799 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
800 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
801 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
802 } else {
803 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
804 PUSH_DATA (push, 15);
805 }
806 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
807 PUSH_DATA (push, 8); /* 128 */
808 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
809 PUSH_DATA (push, 1);
810 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
811 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
812 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
813 }
814
815 nvc0_magic_3d_init(push, screen->eng3d->oclass);
816
817 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
818 &screen->text);
819 if (ret)
820 goto fail;
821
822 /* XXX: getting a page fault at the end of the code buffer every few
823 * launches, don't use the last 256 bytes to work around them - prefetch ?
824 */
825 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
826
827 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
828 &screen->uniform_bo);
829 if (ret)
830 goto fail;
831
832 PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
833
834 for (i = 0; i < 5; ++i) {
835 /* TIC and TSC entries for each unit (nve4+ only) */
836 /* auxiliary constants (6 user clip planes, base instance id) */
837 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
838 PUSH_DATA (push, 512);
839 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
840 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
841 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
842 PUSH_DATA (push, (15 << 4) | 1);
843 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
844 unsigned j;
845 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
846 PUSH_DATA (push, 0);
847 for (j = 0; j < 8; ++j)
848 PUSH_DATA(push, j);
849 } else {
850 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
851 PUSH_DATA (push, 0x54);
852 }
853 }
854 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
855 PUSH_DATA (push, 0);
856
857 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
858 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
859 PUSH_DATA (push, 256);
860 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
861 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
862 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
863 PUSH_DATA (push, 0);
864 PUSH_DATAf(push, 0.0f);
865 PUSH_DATAf(push, 0.0f);
866 PUSH_DATAf(push, 0.0f);
867 PUSH_DATAf(push, 0.0f);
868 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
869 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
870 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
871
872 if (dev->drm_version >= 0x01000101) {
873 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
874 if (ret) {
875 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
876 goto fail;
877 }
878 } else {
879 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
880 value = (8 << 8) | 4;
881 else
882 value = (16 << 8) | 4;
883 }
884 screen->mp_count = value >> 8;
885 screen->mp_count_compute = screen->mp_count;
886
887 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
888
889 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
890 PUSH_DATAh(push, screen->text->offset);
891 PUSH_DATA (push, screen->text->offset);
892 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
893 PUSH_DATAh(push, screen->tls->offset);
894 PUSH_DATA (push, screen->tls->offset);
895 PUSH_DATA (push, screen->tls->size >> 32);
896 PUSH_DATA (push, screen->tls->size);
897 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
898 PUSH_DATA (push, 0);
899 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
900 PUSH_DATA (push, 0);
901
902 if (screen->eng3d->oclass < GM107_3D_CLASS) {
903 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
904 &screen->poly_cache);
905 if (ret)
906 goto fail;
907
908 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
909 PUSH_DATAh(push, screen->poly_cache->offset);
910 PUSH_DATA (push, screen->poly_cache->offset);
911 PUSH_DATA (push, 3);
912 }
913
914 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
915 &screen->txc);
916 if (ret)
917 goto fail;
918
919 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
920 PUSH_DATAh(push, screen->txc->offset);
921 PUSH_DATA (push, screen->txc->offset);
922 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
923
924 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
925 PUSH_DATAh(push, screen->txc->offset + 65536);
926 PUSH_DATA (push, screen->txc->offset + 65536);
927 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
928
929 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
930 PUSH_DATA (push, 0);
931 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
932 PUSH_DATA (push, 0);
933 PUSH_DATA (push, 0);
934 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
935 PUSH_DATA (push, 0x3f);
936
937 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
938 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
939 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
940 for (i = 0; i < 8 * 2; ++i)
941 PUSH_DATA(push, 0);
942 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
943 PUSH_DATA (push, 0);
944 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
945 PUSH_DATA (push, 0);
946
947 /* neither scissors, viewport nor stencil mask should affect clears */
948 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
949 PUSH_DATA (push, 0);
950
951 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
952 PUSH_DATA (push, 1);
953 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
954 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
955 PUSH_DATAf(push, 0.0f);
956 PUSH_DATAf(push, 1.0f);
957 }
958 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
959 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
960
961 /* We use scissors instead of exact view volume clipping,
962 * so they're always enabled.
963 */
964 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
965 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
966 PUSH_DATA (push, 1);
967 PUSH_DATA (push, 8192 << 16);
968 PUSH_DATA (push, 8192 << 16);
969 }
970
971 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
972
973 i = 0;
974 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
975 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
976 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
977 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
978 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
979 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
980 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
981 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
982 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
983
984 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
985 PUSH_DATA (push, 1);
986 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
987 PUSH_DATA (push, 1);
988 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
989 PUSH_DATA (push, 0x40);
990 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
991 PUSH_DATA (push, 0);
992 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
993 PUSH_DATA (push, 0x30);
994 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
995 PUSH_DATA (push, 3);
996 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
997 PUSH_DATA (push, 0x20);
998 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
999 PUSH_DATA (push, 0x00);
1000
1001 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1002 PUSH_DATA (push, 0);
1003 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1004 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1005
1006 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1007
1008 if (nvc0_screen_init_compute(screen))
1009 goto fail;
1010
1011 PUSH_KICK (push);
1012
1013 screen->tic.entries = CALLOC(4096, sizeof(void *));
1014 screen->tsc.entries = screen->tic.entries + 2048;
1015
1016 mm_config.nvc0.tile_mode = 0;
1017 mm_config.nvc0.memtype = 0xfe0;
1018 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
1019
1020 if (!nvc0_blitter_create(screen))
1021 goto fail;
1022
1023 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
1024
1025 return pscreen;
1026
1027 fail:
1028 nvc0_screen_destroy(pscreen);
1029 return NULL;
1030 }
1031
1032 int
1033 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1034 {
1035 int i = screen->tic.next;
1036
1037 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1038 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1039
1040 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1041
1042 if (screen->tic.entries[i])
1043 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1044
1045 screen->tic.entries[i] = entry;
1046 return i;
1047 }
1048
1049 int
1050 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1051 {
1052 int i = screen->tsc.next;
1053
1054 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1055 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1056
1057 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1058
1059 if (screen->tsc.entries[i])
1060 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1061
1062 screen->tsc.entries[i] = entry;
1063 return i;
1064 }