src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30
  31 #include "nouveau_vp3_video.h"
  32
  33 #include "nvc0/nvc0_context.h"
  34 #include "nvc0/nvc0_screen.h"
  35
  36 #include "nvc0/mme/com9097.mme.h"
  37 #include "nvc0/mme/com90c0.mme.h"
  38
  39 #include "nv50/g80_texture.xml.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned storage_sample_count,
  47                                 unsigned bindings)
  48 {
  49    const struct util_format_description *desc = util_format_description(format);
  50
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55
  56    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  57       return false;
  58
  59    /* Short-circuit the rest of the logic -- this is used by the state tracker
  60     * to determine valid MS levels in a no-attachments scenario.
  61     */
  62    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  63       return true;
  64
  65    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  66       if (util_format_get_blocksizebits(format) == 3 * 32)
  67          return false;
  68
  69    if (bindings & PIPE_BIND_LINEAR)
  70       if (util_format_is_depth_or_stencil(format) ||
  71           (target != PIPE_TEXTURE_1D &&
  72            target != PIPE_TEXTURE_2D &&
  73            target != PIPE_TEXTURE_RECT) ||
  74           sample_count > 1)
  75          return false;
  76
  77    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  78     */
  79    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  80         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  81        /* The claim is that this should work on GM107 but it doesn't. Need to
  82         * test further and figure out if it's a nouveau issue or a HW one.
  83        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  84         */
  85        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  86       return false;
  87
  88    /* shared is always supported */
  89    bindings &= ~(PIPE_BIND_LINEAR |
  90                  PIPE_BIND_SHARED);
  91
  92    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  93       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  94           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
  95          /* This should work on Fermi, but for currently unknown reasons it
  96           * does not and results in breaking reads from pbos. */
  97          return false;
  98       }
  99    }
 100
 101    return (( nvc0_format_table[format].usage |
 102             nvc0_vertex_format[format].usage) & bindings) == bindings;
 103 }
 104
 105 static int
 106 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 107 {
 108    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 109    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 110
 111    switch (param) {
 112    /* non-boolean caps */
 113    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 114    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 115       return 15;
 116    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 117       return 12;
 118    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 119       return 2048;
 120    case PIPE_CAP_MIN_TEXEL_OFFSET:
 121       return -8;
 122    case PIPE_CAP_MAX_TEXEL_OFFSET:
 123       return 7;
 124    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 125       return -32;
 126    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 127       return 31;
 128    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 129       return 128 * 1024 * 1024;
 130    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 131       return 430;
 132    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 133       return 430;
 134    case PIPE_CAP_MAX_RENDER_TARGETS:
 135       return 8;
 136    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 137       return 1;
 138    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 139    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 140       return 8;
 141    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 142       return 4;
 143    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 145       return 128;
 146    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 147    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 148       return 1024;
 149    case PIPE_CAP_MAX_VERTEX_STREAMS:
 150       return 4;
 151    case PIPE_CAP_MAX_GS_INVOCATIONS:
 152       return 32;
 153    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 154       return 1 << 27;
 155    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 156       return 2048;
 157    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 158       return 2047;
 159    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 160       return 256;
 161    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 162       if (class_3d < GM107_3D_CLASS)
 163          return 256; /* IMAGE bindings require alignment to 256 */
 164       return 16;
 165    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 166       return 16;
 167    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 168       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 169    case PIPE_CAP_MAX_VIEWPORTS:
 170       return NVC0_MAX_VIEWPORTS;
 171    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 172       return 4;
 173    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 174       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 175    case PIPE_CAP_ENDIANNESS:
 176       return PIPE_ENDIAN_LITTLE;
 177    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 178       return 30;
 179    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 180       return NVC0_MAX_WINDOW_RECTANGLES;
 181    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 182       return class_3d >= GM200_3D_CLASS ? 8 : 0;
 183    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 184       return 64 * 1024 * 1024;
 185    case PIPE_CAP_MAX_VARYINGS:
 186       /* NOTE: These only count our slots for GENERIC varyings.
 187        * The address space may be larger, but the actual hard limit seems to be
 188        * less than what the address space layout permits, so don't add TEXCOORD,
 189        * COLOR, etc. here.
 190        */
 191       return 0x1f0 / 16;
 192
 193    /* supported caps */
 194    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 195    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 196    case PIPE_CAP_TEXTURE_SWIZZLE:
 197    case PIPE_CAP_NPOT_TEXTURES:
 198    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 199    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 200    case PIPE_CAP_ANISOTROPIC_FILTER:
 201    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 202    case PIPE_CAP_CUBE_MAP_ARRAY:
 203    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 204    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 205    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 206    case PIPE_CAP_POINT_SPRITE:
 207    case PIPE_CAP_TGSI_TEXCOORD:
 208    case PIPE_CAP_SM3:
 209    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 210    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 211    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 212    case PIPE_CAP_QUERY_TIMESTAMP:
 213    case PIPE_CAP_QUERY_TIME_ELAPSED:
 214    case PIPE_CAP_OCCLUSION_QUERY:
 215    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 216    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 217    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 218    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 219    case PIPE_CAP_INDEP_BLEND_ENABLE:
 220    case PIPE_CAP_INDEP_BLEND_FUNC:
 221    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 222    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 223    case PIPE_CAP_PRIMITIVE_RESTART:
 224    case PIPE_CAP_TGSI_INSTANCEID:
 225    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 226    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 227    case PIPE_CAP_CONDITIONAL_RENDER:
 228    case PIPE_CAP_TEXTURE_BARRIER:
 229    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 230    case PIPE_CAP_START_INSTANCE:
 231    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 232    case PIPE_CAP_DRAW_INDIRECT:
 233    case PIPE_CAP_USER_VERTEX_BUFFERS:
 234    case PIPE_CAP_TEXTURE_QUERY_LOD:
 235    case PIPE_CAP_SAMPLE_SHADING:
 236    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 237    case PIPE_CAP_TEXTURE_GATHER_SM5:
 238    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 239    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 240    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 241    case PIPE_CAP_CLIP_HALFZ:
 242    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 243    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 244    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 245    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 246    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 247    case PIPE_CAP_TGSI_TXQS:
 248    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 249    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 250    case PIPE_CAP_SHAREABLE_SHADERS:
 251    case PIPE_CAP_CLEAR_TEXTURE:
 252    case PIPE_CAP_DRAW_PARAMETERS:
 253    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 254    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 255    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 256    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 257    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 258    case PIPE_CAP_INVALIDATE_BUFFER:
 259    case PIPE_CAP_STRING_MARKER:
 260    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 261    case PIPE_CAP_CULL_DISTANCE:
 262    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 263    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 264    case PIPE_CAP_TGSI_VOTE:
 265    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 266    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 267    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 268    case PIPE_CAP_DOUBLES:
 269    case PIPE_CAP_INT64:
 270    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 271    case PIPE_CAP_TGSI_CLOCK:
 272    case PIPE_CAP_COMPUTE:
 273    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 274    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 275    case PIPE_CAP_QUERY_SO_OVERFLOW:
 276    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 277       return 1;
 278    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 279       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 280    case PIPE_CAP_TGSI_FS_FBFETCH:
 281       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 282    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 283    case PIPE_CAP_TGSI_BALLOT:
 284    case PIPE_CAP_BINDLESS_TEXTURE:
 285       return class_3d >= NVE4_3D_CLASS;
 286    case PIPE_CAP_TGSI_ATOMFADD:
 287       return class_3d < GM107_3D_CLASS; /* needs additional lowering */
 288    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 289    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 290    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 291    case PIPE_CAP_POST_DEPTH_COVERAGE:
 292    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 293    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 294    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 295    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 296       return class_3d >= GM200_3D_CLASS;
 297    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 298       return class_3d >= GP100_3D_CLASS;
 299
 300    /* unsupported caps */
 301    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 302    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 303    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 304    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 305    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 306    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 307    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 308    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 309    case PIPE_CAP_FAKE_SW_MSAA:
 310    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 311    case PIPE_CAP_VERTEXID_NOBASE:
 312    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 313    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 314    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 315    case PIPE_CAP_GENERATE_MIPMAP:
 316    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 317    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 318    case PIPE_CAP_QUERY_MEMORY_INFO:
 319    case PIPE_CAP_PCI_GROUP:
 320    case PIPE_CAP_PCI_BUS:
 321    case PIPE_CAP_PCI_DEVICE:
 322    case PIPE_CAP_PCI_FUNCTION:
 323    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 324    case PIPE_CAP_NATIVE_FENCE_FD:
 325    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 326    case PIPE_CAP_INT64_DIVMOD:
 327    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 328    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 329    case PIPE_CAP_MEMOBJ:
 330    case PIPE_CAP_LOAD_CONSTBUF:
 331    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 332    case PIPE_CAP_TILE_RASTER_ORDER:
 333    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 334    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 335    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 336    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 337    case PIPE_CAP_FENCE_SIGNAL:
 338    case PIPE_CAP_CONSTBUF0_FLAGS:
 339    case PIPE_CAP_PACKED_UNIFORMS:
 340    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 341    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 342    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 343    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 344    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 345    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 346    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 347    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 348       return 0;
 349
 350    case PIPE_CAP_VENDOR_ID:
 351       return 0x10de;
 352    case PIPE_CAP_DEVICE_ID: {
 353       uint64_t device_id;
 354       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 355          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 356          return -1;
 357       }
 358       return device_id;
 359    }
 360    case PIPE_CAP_ACCELERATED:
 361       return 1;
 362    case PIPE_CAP_VIDEO_MEMORY:
 363       return dev->vram_size >> 20;
 364    case PIPE_CAP_UMA:
 365       return 0;
 366    default:
 367       debug_printf("%s: unhandled cap %d\n", __func__, param);
 368       return u_pipe_screen_get_param_defaults(pscreen, param);
 369    }
 370 }
 371
 372 static int
 373 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 374                              enum pipe_shader_type shader,
 375                              enum pipe_shader_cap param)
 376 {
 377    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 378
 379    switch (shader) {
 380    case PIPE_SHADER_VERTEX:
 381    case PIPE_SHADER_GEOMETRY:
 382    case PIPE_SHADER_FRAGMENT:
 383    case PIPE_SHADER_COMPUTE:
 384    case PIPE_SHADER_TESS_CTRL:
 385    case PIPE_SHADER_TESS_EVAL:
 386       break;
 387    default:
 388       return 0;
 389    }
 390
 391    switch (param) {
 392    case PIPE_SHADER_CAP_PREFERRED_IR:
 393       return PIPE_SHADER_IR_TGSI;
 394    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 395       return 1 << PIPE_SHADER_IR_TGSI;
 396    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 397    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 398    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 399    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 400       return 16384;
 401    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 402       return 16;
 403    case PIPE_SHADER_CAP_MAX_INPUTS:
 404       return 0x200 / 16;
 405    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 406       return 32;
 407    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 408       return NVC0_MAX_CONSTBUF_SIZE;
 409    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 410       return NVC0_MAX_PIPE_CONSTBUFS;
 411    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 412       return shader != PIPE_SHADER_FRAGMENT;
 413    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 414    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 415    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 416       return 1;
 417    case PIPE_SHADER_CAP_MAX_TEMPS:
 418       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 419    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 420       return 1;
 421    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 422       return 1;
 423    case PIPE_SHADER_CAP_SUBROUTINES:
 424       return 1;
 425    case PIPE_SHADER_CAP_INTEGERS:
 426       return 1;
 427    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 428       return 1;
 429    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 430       return 1;
 431    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 432       return 1;
 433    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 434    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 435    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 436    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 437    case PIPE_SHADER_CAP_INT64_ATOMICS:
 438    case PIPE_SHADER_CAP_FP16:
 439    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 440    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 441       return 0;
 442    case PIPE_SHADER_CAP_SCALAR_ISA:
 443       return 1;
 444    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 445       return NVC0_MAX_BUFFERS;
 446    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 447       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 448    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 449       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 450    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 451       return 32;
 452    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 453       if (class_3d >= NVE4_3D_CLASS)
 454          return NVC0_MAX_IMAGES;
 455       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 456          return NVC0_MAX_IMAGES;
 457       return 0;
 458    default:
 459       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 460       return 0;
 461    }
 462 }
 463
 464 static float
 465 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 466 {
 467    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 468
 469    switch (param) {
 470    case PIPE_CAPF_MAX_LINE_WIDTH:
 471    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 472       return 10.0f;
 473    case PIPE_CAPF_MAX_POINT_WIDTH:
 474       return 63.0f;
 475    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 476       return 63.375f;
 477    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 478       return 16.0f;
 479    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 480       return 15.0f;
 481    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 482       return 0.0f;
 483    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 484       return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
 485    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 486       return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
 487    }
 488
 489    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 490    return 0.0f;
 491 }
 492
 493 static int
 494 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 495                               enum pipe_shader_ir ir_type,
 496                               enum pipe_compute_cap param, void *data)
 497 {
 498    struct nvc0_screen *screen = nvc0_screen(pscreen);
 499    const uint16_t obj_class = screen->compute->oclass;
 500
 501 #define RET(x) do {                  \
 502    if (data)                         \
 503       memcpy(data, x, sizeof(x));    \
 504    return sizeof(x);                 \
 505 } while (0)
 506
 507    switch (param) {
 508    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 509       RET((uint64_t []) { 3 });
 510    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 511       if (obj_class >= NVE4_COMPUTE_CLASS) {
 512          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 513       } else {
 514          RET(((uint64_t []) { 65535, 65535, 65535 }));
 515       }
 516    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 517       RET(((uint64_t []) { 1024, 1024, 64 }));
 518    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 519       RET((uint64_t []) { 1024 });
 520    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 521       if (obj_class >= NVE4_COMPUTE_CLASS) {
 522          RET((uint64_t []) { 1024 });
 523       } else {
 524          RET((uint64_t []) { 512 });
 525       }
 526    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 527       RET((uint64_t []) { 1ULL << 40 });
 528    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 529       switch (obj_class) {
 530       case GM200_COMPUTE_CLASS:
 531          RET((uint64_t []) { 96 << 10 });
 532          break;
 533       case GM107_COMPUTE_CLASS:
 534          RET((uint64_t []) { 64 << 10 });
 535          break;
 536       default:
 537          RET((uint64_t []) { 48 << 10 });
 538          break;
 539       }
 540    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 541       RET((uint64_t []) { 512 << 10 });
 542    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 543       RET((uint64_t []) { 4096 });
 544    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 545       RET((uint32_t []) { 32 });
 546    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 547       RET((uint64_t []) { 1ULL << 40 });
 548    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 549       RET((uint32_t []) { 0 });
 550    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 551       RET((uint32_t []) { screen->mp_count_compute });
 552    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 553       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 554    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 555       RET((uint32_t []) { 64 });
 556    default:
 557       return 0;
 558    }
 559
 560 #undef RET
 561 }
 562
 563 static void
 564 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
 565                                   unsigned sample_count,
 566                                   unsigned *width, unsigned *height)
 567 {
 568    switch (sample_count) {
 569    case 0:
 570    case 1:
 571       /* this could be 4x4, but the GL state tracker makes it difficult to
 572        * create a 1x MSAA texture and smaller grids save CB space */
 573       *width = 2;
 574       *height = 4;
 575       break;
 576    case 2:
 577       *width = 2;
 578       *height = 4;
 579       break;
 580    case 4:
 581       *width = 2;
 582       *height = 2;
 583       break;
 584    case 8:
 585       *width = 1;
 586       *height = 2;
 587       break;
 588    default:
 589       assert(0);
 590    }
 591 }
 592
 593 static void
 594 nvc0_screen_destroy(struct pipe_screen *pscreen)
 595 {
 596    struct nvc0_screen *screen = nvc0_screen(pscreen);
 597
 598    if (!nouveau_drm_screen_unref(&screen->base))
 599       return;
 600
 601    if (screen->base.fence.current) {
 602       struct nouveau_fence *current = NULL;
 603
 604       /* nouveau_fence_wait will create a new current fence, so wait on the
 605        * _current_ one, and remove both.
 606        */
 607       nouveau_fence_ref(screen->base.fence.current, &current);
 608       nouveau_fence_wait(current, NULL);
 609       nouveau_fence_ref(NULL, &current);
 610       nouveau_fence_ref(NULL, &screen->base.fence.current);
 611    }
 612    if (screen->base.pushbuf)
 613       screen->base.pushbuf->user_priv = NULL;
 614
 615    if (screen->blitter)
 616       nvc0_blitter_destroy(screen);
 617    if (screen->pm.prog) {
 618       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 619       nvc0_program_destroy(NULL, screen->pm.prog);
 620       FREE(screen->pm.prog);
 621    }
 622
 623    nouveau_bo_ref(NULL, &screen->text);
 624    nouveau_bo_ref(NULL, &screen->uniform_bo);
 625    nouveau_bo_ref(NULL, &screen->tls);
 626    nouveau_bo_ref(NULL, &screen->txc);
 627    nouveau_bo_ref(NULL, &screen->fence.bo);
 628    nouveau_bo_ref(NULL, &screen->poly_cache);
 629
 630    nouveau_heap_destroy(&screen->lib_code);
 631    nouveau_heap_destroy(&screen->text_heap);
 632
 633    FREE(screen->tic.entries);
 634
 635    nouveau_object_del(&screen->eng3d);
 636    nouveau_object_del(&screen->eng2d);
 637    nouveau_object_del(&screen->m2mf);
 638    nouveau_object_del(&screen->compute);
 639    nouveau_object_del(&screen->nvsw);
 640
 641    nouveau_screen_fini(&screen->base);
 642
 643    FREE(screen);
 644 }
 645
 646 static int
 647 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 648                      unsigned size, const uint32_t *data)
 649 {
 650    struct nouveau_pushbuf *push = screen->base.pushbuf;
 651
 652    size /= 4;
 653
 654    assert((pos + size) <= 0x800);
 655
 656    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 657    PUSH_DATA (push, (m - 0x3800) / 8);
 658    PUSH_DATA (push, pos);
 659    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 660    PUSH_DATA (push, pos);
 661    PUSH_DATAp(push, data, size);
 662
 663    return pos + size;
 664 }
 665
 666 static void
 667 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 668 {
 669    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 670    PUSH_DATA (push, 0xff);
 671    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 672    PUSH_DATA (push, 0xff);
 673    PUSH_DATA (push, 0xff);
 674    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 675    PUSH_DATA (push, 0xff);
 676    PUSH_DATA (push, 0xff);
 677    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 678    PUSH_DATA (push, 0x3f);
 679
 680    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 681    PUSH_DATA (push, (3 << 16) | 3);
 682    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 683    PUSH_DATA (push, (2 << 16) | 2);
 684
 685    if (obj_class < GM107_3D_CLASS) {
 686       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 687       PUSH_DATA (push, 0);
 688    }
 689    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 690    PUSH_DATA (push, 0x10);
 691    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 692    PUSH_DATA (push, 0x10);
 693    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 694    PUSH_DATA (push, 0x10);
 695    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 696    PUSH_DATA (push, 0x10);
 697    PUSH_DATA (push, 0x10);
 698    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 699    PUSH_DATA (push, 0x10);
 700    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 701    PUSH_DATA (push, 0xe);
 702
 703    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 704    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 705    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 706    PUSH_DATA (push, 0);
 707    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 708    PUSH_DATA (push, 3);
 709
 710    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 711    PUSH_DATA (push, 0x3fffff);
 712    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 713    PUSH_DATA (push, 1);
 714    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 715    PUSH_DATA (push, 1);
 716
 717    if (obj_class < GM107_3D_CLASS) {
 718       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 719       PUSH_DATA (push, 3);
 720
 721       if (obj_class >= NVE4_3D_CLASS) {
 722          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 723          PUSH_DATA (push, 1);
 724       }
 725    }
 726
 727    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 728     * are supposed to do */
 729 }
 730
 731 static void
 732 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 733 {
 734    struct nvc0_screen *screen = nvc0_screen(pscreen);
 735    struct nouveau_pushbuf *push = screen->base.pushbuf;
 736
 737    /* we need to do it after possible flush in MARK_RING */
 738    *sequence = ++screen->base.fence.sequence;
 739
 740    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 741    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 742    PUSH_DATAh(push, screen->fence.bo->offset);
 743    PUSH_DATA (push, screen->fence.bo->offset);
 744    PUSH_DATA (push, *sequence);
 745    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 746               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 747 }
 748
 749 static u32
 750 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 751 {
 752    struct nvc0_screen *screen = nvc0_screen(pscreen);
 753    return screen->fence.map[0];
 754 }
 755
 756 static int
 757 nvc0_screen_init_compute(struct nvc0_screen *screen)
 758 {
 759    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 760
 761    switch (screen->base.device->chipset & ~0xf) {
 762    case 0xc0:
 763    case 0xd0:
 764       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 765    case 0xe0:
 766    case 0xf0:
 767    case 0x100:
 768    case 0x110:
 769    case 0x120:
 770    case 0x130:
 771       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 772    default:
 773       return -1;
 774    }
 775 }
 776
 777 static int
 778 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 779                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 780 {
 781    struct nouveau_bo *bo = NULL;
 782    int ret;
 783    uint64_t size = (lpos + lneg) * 32 + cstack;
 784
 785    if (size >= (1 << 20)) {
 786       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 787       return -1;
 788    }
 789
 790    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 791    size  = align(size, 0x8000);
 792    size *= screen->mp_count;
 793
 794    size = align(size, 1 << 17);
 795
 796    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 797                         NULL, &bo);
 798    if (ret)
 799       return ret;
 800
 801    /* Make sure that the pushbuf has acquired a reference to the old tls
 802     * segment, as it may have commands that will reference it.
 803     */
 804    if (screen->tls)
 805       PUSH_REFN(screen->base.pushbuf, screen->tls,
 806                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
 807    nouveau_bo_ref(NULL, &screen->tls);
 808    screen->tls = bo;
 809    return 0;
 810 }
 811
 812 int
 813 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 814 {
 815    struct nouveau_pushbuf *push = screen->base.pushbuf;
 816    struct nouveau_bo *bo;
 817    int ret;
 818
 819    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 820                         1 << 17, size, NULL, &bo);
 821    if (ret)
 822       return ret;
 823
 824    /* Make sure that the pushbuf has acquired a reference to the old text
 825     * segment, as it may have commands that will reference it.
 826     */
 827    if (screen->text)
 828       PUSH_REFN(push, screen->text,
 829                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
 830    nouveau_bo_ref(NULL, &screen->text);
 831    screen->text = bo;
 832
 833    nouveau_heap_destroy(&screen->lib_code);
 834    nouveau_heap_destroy(&screen->text_heap);
 835
 836    /* XXX: getting a page fault at the end of the code buffer every few
 837     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 838     */
 839    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 840
 841    /* update the code segment setup */
 842    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 843    PUSH_DATAh(push, screen->text->offset);
 844    PUSH_DATA (push, screen->text->offset);
 845    if (screen->compute) {
 846       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 847       PUSH_DATAh(push, screen->text->offset);
 848       PUSH_DATA (push, screen->text->offset);
 849    }
 850
 851    return 0;
 852 }
 853
 854 void
 855 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
 856                        int stage, int index, int size, uint64_t addr)
 857 {
 858    assert(stage != 5);
 859
 860    struct nouveau_pushbuf *push = screen->base.pushbuf;
 861
 862    if (screen->base.class_3d >= GM107_3D_CLASS) {
 863       struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
 864
 865       // TODO: Better figure out the conditions in which this is needed
 866       bool serialize = binding->addr == addr && binding->size != size;
 867       if (can_serialize)
 868          serialize = serialize && *can_serialize;
 869       if (serialize) {
 870          IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 871          if (can_serialize)
 872             *can_serialize = false;
 873       }
 874
 875       binding->addr = addr;
 876       binding->size = size;
 877    }
 878
 879    if (size >= 0) {
 880       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 881       PUSH_DATA (push, size);
 882       PUSH_DATAh(push, addr);
 883       PUSH_DATA (push, addr);
 884    }
 885    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
 886 }
 887
 888 #define FAIL_SCREEN_INIT(str, err)                    \
 889    do {                                               \
 890       NOUVEAU_ERR(str, err);                          \
 891       goto fail;                                      \
 892    } while(0)
 893
 894 struct nouveau_screen *
 895 nvc0_screen_create(struct nouveau_device *dev)
 896 {
 897    struct nvc0_screen *screen;
 898    struct pipe_screen *pscreen;
 899    struct nouveau_object *chan;
 900    struct nouveau_pushbuf *push;
 901    uint64_t value;
 902    uint32_t obj_class;
 903    uint32_t flags;
 904    int ret;
 905    unsigned i;
 906
 907    switch (dev->chipset & ~0xf) {
 908    case 0xc0:
 909    case 0xd0:
 910    case 0xe0:
 911    case 0xf0:
 912    case 0x100:
 913    case 0x110:
 914    case 0x120:
 915    case 0x130:
 916       break;
 917    default:
 918       return NULL;
 919    }
 920
 921    screen = CALLOC_STRUCT(nvc0_screen);
 922    if (!screen)
 923       return NULL;
 924    pscreen = &screen->base.base;
 925    pscreen->destroy = nvc0_screen_destroy;
 926
 927    ret = nouveau_screen_init(&screen->base, dev);
 928    if (ret)
 929       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 930    chan = screen->base.channel;
 931    push = screen->base.pushbuf;
 932    push->user_priv = screen;
 933    push->rsvd_kick = 5;
 934
 935    /* TODO: could this be higher on Kepler+? how does reclocking vs no
 936     * reclocking affect performance?
 937     * TODO: could this be higher on Fermi?
 938     */
 939    if (dev->chipset >= 0xe0)
 940       screen->base.transfer_pushbuf_threshold = 1024;
 941
 942    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 943       PIPE_BIND_SHADER_BUFFER |
 944       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 945       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 946    screen->base.sysmem_bindings |=
 947       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 948
 949    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 950       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 951       screen->base.vidmem_bindings = 0;
 952    }
 953
 954    pscreen->context_create = nvc0_create;
 955    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 956    pscreen->get_param = nvc0_screen_get_param;
 957    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 958    pscreen->get_paramf = nvc0_screen_get_paramf;
 959    pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
 960    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 961    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 962
 963    nvc0_screen_init_resource_functions(pscreen);
 964
 965    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 966    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 967
 968    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 969    if (screen->base.drm->version >= 0x01000202)
 970       flags |= NOUVEAU_BO_COHERENT;
 971
 972    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 973    if (ret)
 974       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 975    nouveau_bo_map(screen->fence.bo, 0, NULL);
 976    screen->fence.map = screen->fence.bo->map;
 977    screen->base.fence.emit = nvc0_screen_fence_emit;
 978    screen->base.fence.update = nvc0_screen_fence_update;
 979
 980
 981    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 982                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 983    if (ret)
 984       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 985
 986    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 987    PUSH_DATA (push, screen->nvsw->handle);
 988
 989    switch (dev->chipset & ~0xf) {
 990    case 0x130:
 991    case 0x120:
 992    case 0x110:
 993    case 0x100:
 994    case 0xf0:
 995       obj_class = NVF0_P2MF_CLASS;
 996       break;
 997    case 0xe0:
 998       obj_class = NVE4_P2MF_CLASS;
 999       break;
1000    default:
1001       obj_class = NVC0_M2MF_CLASS;
1002       break;
1003    }
1004    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
1005                             &screen->m2mf);
1006    if (ret)
1007       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
1008
1009    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
1010    PUSH_DATA (push, screen->m2mf->oclass);
1011    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1012       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1013       PUSH_DATA (push, 0xa0b5);
1014    }
1015
1016    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1017                             &screen->eng2d);
1018    if (ret)
1019       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1020
1021    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1022    PUSH_DATA (push, screen->eng2d->oclass);
1023    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1024    PUSH_DATA (push, 0);
1025    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1026    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1027    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1028    PUSH_DATA (push, 0);
1029    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1030    PUSH_DATA (push, 0);
1031    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1032    PUSH_DATA (push, 0x3f);
1033    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1034    PUSH_DATA (push, 1);
1035    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1036    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1037
1038    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1039    PUSH_DATAh(push, screen->fence.bo->offset + 16);
1040    PUSH_DATA (push, screen->fence.bo->offset + 16);
1041
1042    switch (dev->chipset & ~0xf) {
1043    case 0x130:
1044       switch (dev->chipset) {
1045       case 0x130:
1046       case 0x13b:
1047          obj_class = GP100_3D_CLASS;
1048          break;
1049       default:
1050          obj_class = GP102_3D_CLASS;
1051          break;
1052       }
1053       break;
1054    case 0x120:
1055       obj_class = GM200_3D_CLASS;
1056       break;
1057    case 0x110:
1058       obj_class = GM107_3D_CLASS;
1059       break;
1060    case 0x100:
1061    case 0xf0:
1062       obj_class = NVF0_3D_CLASS;
1063       break;
1064    case 0xe0:
1065       switch (dev->chipset) {
1066       case 0xea:
1067          obj_class = NVEA_3D_CLASS;
1068          break;
1069       default:
1070          obj_class = NVE4_3D_CLASS;
1071          break;
1072       }
1073       break;
1074    case 0xd0:
1075       obj_class = NVC8_3D_CLASS;
1076       break;
1077    case 0xc0:
1078    default:
1079       switch (dev->chipset) {
1080       case 0xc8:
1081          obj_class = NVC8_3D_CLASS;
1082          break;
1083       case 0xc1:
1084          obj_class = NVC1_3D_CLASS;
1085          break;
1086       default:
1087          obj_class = NVC0_3D_CLASS;
1088          break;
1089       }
1090       break;
1091    }
1092    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1093                             &screen->eng3d);
1094    if (ret)
1095       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1096    screen->base.class_3d = obj_class;
1097
1098    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1099    PUSH_DATA (push, screen->eng3d->oclass);
1100
1101    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1102    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1103
1104    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1105       /* kill shaders after about 1 second (at 100 MHz) */
1106       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1107       PUSH_DATA (push, 0x17);
1108    }
1109
1110    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1111                     screen->base.drm->version >= 0x01000101);
1112    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1113    for (i = 0; i < 8; ++i)
1114       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1115
1116    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1117    PUSH_DATA (push, 1);
1118
1119    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1120    PUSH_DATA (push, 0);
1121    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1122    PUSH_DATA (push, 0);
1123    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1124    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1125    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1126    PUSH_DATA (push, 0);
1127    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1128    PUSH_DATA (push, 1);
1129    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1130    PUSH_DATA (push, 1);
1131    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1132    PUSH_DATA (push, 1);
1133    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1134    PUSH_DATA (push, 0);
1135    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1136    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1137    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1138       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1139    } else {
1140       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1141       PUSH_DATA (push, 15);
1142    }
1143    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1144    PUSH_DATA (push, 8); /* 128 */
1145    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1146    PUSH_DATA (push, 1);
1147    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1148       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1149       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1150    }
1151
1152    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1153
1154    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1155    if (ret)
1156       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1157
1158    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1159    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1160                         &screen->uniform_bo);
1161    if (ret)
1162       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1163
1164    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1165
1166    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1167    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1168    PUSH_DATA (push, 256);
1169    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1170    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1171    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1172    PUSH_DATA (push, 0);
1173    PUSH_DATAf(push, 0.0f);
1174    PUSH_DATAf(push, 0.0f);
1175    PUSH_DATAf(push, 0.0f);
1176    PUSH_DATAf(push, 0.0f);
1177    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1178    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1179    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1180
1181    if (screen->base.drm->version >= 0x01000101) {
1182       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1183       if (ret)
1184          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1185    } else {
1186       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1187          value = (8 << 8) | 4;
1188       else
1189          value = (16 << 8) | 4;
1190    }
1191    screen->gpc_count = value & 0x000000ff;
1192    screen->mp_count = value >> 8;
1193    screen->mp_count_compute = screen->mp_count;
1194
1195    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1196    if (ret)
1197       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1198
1199    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1200    PUSH_DATAh(push, screen->tls->offset);
1201    PUSH_DATA (push, screen->tls->offset);
1202    PUSH_DATA (push, screen->tls->size >> 32);
1203    PUSH_DATA (push, screen->tls->size);
1204    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1205    PUSH_DATA (push, 0);
1206    /* Reduce likelihood of collision with real buffers by placing the hole at
1207     * the top of the 4G area. This will have to be dealt with for real
1208     * eventually by blocking off that area from the VM.
1209     */
1210    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1211    PUSH_DATA (push, 0xff << 24);
1212
1213    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1214       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1215                            &screen->poly_cache);
1216       if (ret)
1217          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1218
1219       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1220       PUSH_DATAh(push, screen->poly_cache->offset);
1221       PUSH_DATA (push, screen->poly_cache->offset);
1222       PUSH_DATA (push, 3);
1223    }
1224
1225    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1226                         &screen->txc);
1227    if (ret)
1228       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1229
1230    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1231    PUSH_DATAh(push, screen->txc->offset);
1232    PUSH_DATA (push, screen->txc->offset);
1233    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1234    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1235       screen->tic.maxwell = true;
1236       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1237          screen->tic.maxwell =
1238             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1239          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1240       }
1241    }
1242
1243    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1244    PUSH_DATAh(push, screen->txc->offset + 65536);
1245    PUSH_DATA (push, screen->txc->offset + 65536);
1246    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1247
1248    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1249    PUSH_DATA (push, 0);
1250    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1251    PUSH_DATA (push, 0);
1252    PUSH_DATA (push, 0);
1253    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1254    PUSH_DATA (push, 0x3f);
1255
1256    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1257    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1258    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1259    for (i = 0; i < 8 * 2; ++i)
1260       PUSH_DATA(push, 0);
1261    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1262    PUSH_DATA (push, 0);
1263    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1264    PUSH_DATA (push, 0);
1265
1266    /* neither scissors, viewport nor stencil mask should affect clears */
1267    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1268    PUSH_DATA (push, 0);
1269
1270    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1271    PUSH_DATA (push, 1);
1272    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1273       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1274       PUSH_DATAf(push, 0.0f);
1275       PUSH_DATAf(push, 1.0f);
1276    }
1277    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1278    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1279
1280    /* We use scissors instead of exact view volume clipping,
1281     * so they're always enabled.
1282     */
1283    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1284       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1285       PUSH_DATA (push, 1);
1286       PUSH_DATA (push, 8192 << 16);
1287       PUSH_DATA (push, 8192 << 16);
1288    }
1289
1290 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1291
1292    i = 0;
1293    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1294    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1295    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1296    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1297    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1298    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1299    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1300    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1301    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1302    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1303    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1304    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1305    MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1306    MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
1307    MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
1308    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1309
1310    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1311    PUSH_DATA (push, 1);
1312    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1313    PUSH_DATA (push, 1);
1314    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1315    PUSH_DATA (push, 0x40);
1316    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1317    PUSH_DATA (push, 0);
1318    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1319    PUSH_DATA (push, 0x30);
1320    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1321    PUSH_DATA (push, 3);
1322    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1323    PUSH_DATA (push, 0x20);
1324    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1325    PUSH_DATA (push, 0x00);
1326    screen->save_state.patch_vertices = 3;
1327
1328    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1329    PUSH_DATA (push, 0);
1330    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1331    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1332
1333    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1334
1335    if (nvc0_screen_init_compute(screen))
1336       goto fail;
1337
1338    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1339    for (i = 0; i < 5; ++i) {
1340       unsigned j = 0;
1341       for (j = 0; j < 16; j++)
1342          screen->cb_bindings[i][j].size = -1;
1343
1344       /* TIC and TSC entries for each unit (nve4+ only) */
1345       /* auxiliary constants (6 user clip planes, base instance id) */
1346       nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1347                              screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1348       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1349          unsigned j;
1350          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1351          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1352          for (j = 0; j < 8; ++j)
1353             PUSH_DATA(push, j);
1354       } else {
1355          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1356          PUSH_DATA (push, 0x54);
1357       }
1358
1359       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1360       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1361       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1362       PUSH_DATA (push, 0); /* 0 */
1363       PUSH_DATA (push, 0);
1364       PUSH_DATA (push, 1); /* 1 */
1365       PUSH_DATA (push, 0);
1366       PUSH_DATA (push, 0); /* 2 */
1367       PUSH_DATA (push, 1);
1368       PUSH_DATA (push, 1); /* 3 */
1369       PUSH_DATA (push, 1);
1370       PUSH_DATA (push, 2); /* 4 */
1371       PUSH_DATA (push, 0);
1372       PUSH_DATA (push, 3); /* 5 */
1373       PUSH_DATA (push, 0);
1374       PUSH_DATA (push, 2); /* 6 */
1375       PUSH_DATA (push, 1);
1376       PUSH_DATA (push, 3); /* 7 */
1377       PUSH_DATA (push, 1);
1378    }
1379    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1380    PUSH_DATA (push, 0);
1381
1382    PUSH_KICK (push);
1383
1384    screen->tic.entries = CALLOC(
1385          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1386          sizeof(void *));
1387    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1388    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1389
1390    if (!nvc0_blitter_create(screen))
1391       goto fail;
1392
1393    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1394
1395    return &screen->base;
1396
1397 fail:
1398    screen->base.base.context_create = NULL;
1399    return &screen->base;
1400 }
1401
1402 int
1403 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1404 {
1405    int i = screen->tic.next;
1406
1407    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1408       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1409
1410    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1411
1412    if (screen->tic.entries[i])
1413       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1414
1415    screen->tic.entries[i] = entry;
1416    return i;
1417 }
1418
1419 int
1420 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1421 {
1422    int i = screen->tsc.next;
1423
1424    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1425       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1426
1427    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1428
1429    if (screen->tsc.entries[i])
1430       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1431
1432    screen->tsc.entries[i] = entry;
1433    return i;
1434 }