src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    const struct util_format_description *desc = util_format_description(format);
  49
  50    if (sample_count > 8)
  51       return false;
  52    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  53       return false;
  54
  55    if (!util_format_is_supported(format, bindings))
  56       return false;
  57
  58    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  59       if (util_format_get_blocksizebits(format) == 3 * 32)
  60          return false;
  61
  62    if (bindings & PIPE_BIND_LINEAR)
  63       if (util_format_is_depth_or_stencil(format) ||
  64           (target != PIPE_TEXTURE_1D &&
  65            target != PIPE_TEXTURE_2D &&
  66            target != PIPE_TEXTURE_RECT) ||
  67           sample_count > 1)
  68          return false;
  69
  70    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  71     */
  72    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  73         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  74        /* The claim is that this should work on GM107 but it doesn't. Need to
  75         * test further and figure out if it's a nouveau issue or a HW one.
  76        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  77         */
  78        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  79       return false;
  80
  81    /* transfers & shared are always supported */
  82    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  83                  PIPE_BIND_TRANSFER_WRITE |
  84                  PIPE_BIND_LINEAR |
  85                  PIPE_BIND_SHARED);
  86
  87    return (( nvc0_format_table[format].usage |
  88             nvc0_vertex_format[format].usage) & bindings) == bindings;
  89 }
  90
  91 static int
  92 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  93 {
  94    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  95    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  96
  97    switch (param) {
  98    /* non-boolean caps */
  99    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 100    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 101       return 15;
 102    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 103       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
 104    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 105       return 2048;
 106    case PIPE_CAP_MIN_TEXEL_OFFSET:
 107       return -8;
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109       return 7;
 110    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 111       return -32;
 112    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 113       return 31;
 114    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 115       return 128 * 1024 * 1024;
 116    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 117       return 410;
 118    case PIPE_CAP_MAX_RENDER_TARGETS:
 119       return 8;
 120    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 121       return 1;
 122    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 123       return 4;
 124    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 126       return 128;
 127    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 128    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 129       return 1024;
 130    case PIPE_CAP_MAX_VERTEX_STREAMS:
 131       return 4;
 132    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 133       return 2048;
 134    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 135       return 256;
 136    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 137       return 16; /* 256 for binding as RT, but that's not possible in GL */
 138    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 139       return 16;
 140    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 141       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 142    case PIPE_CAP_MAX_VIEWPORTS:
 143       return NVC0_MAX_VIEWPORTS;
 144    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 145       return 4;
 146    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 147       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 148    case PIPE_CAP_ENDIANNESS:
 149       return PIPE_ENDIAN_LITTLE;
 150    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 151       return 30;
 152
 153    /* supported caps */
 154    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 155    case PIPE_CAP_TEXTURE_SWIZZLE:
 156    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 157    case PIPE_CAP_NPOT_TEXTURES:
 158    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 159    case PIPE_CAP_ANISOTROPIC_FILTER:
 160    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 161    case PIPE_CAP_CUBE_MAP_ARRAY:
 162    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 163    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 164    case PIPE_CAP_TWO_SIDED_STENCIL:
 165    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 166    case PIPE_CAP_POINT_SPRITE:
 167    case PIPE_CAP_TGSI_TEXCOORD:
 168    case PIPE_CAP_SM3:
 169    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 170    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 171    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 172    case PIPE_CAP_QUERY_TIMESTAMP:
 173    case PIPE_CAP_QUERY_TIME_ELAPSED:
 174    case PIPE_CAP_OCCLUSION_QUERY:
 175    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 176    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 177    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 178    case PIPE_CAP_INDEP_BLEND_ENABLE:
 179    case PIPE_CAP_INDEP_BLEND_FUNC:
 180    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 181    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 182    case PIPE_CAP_PRIMITIVE_RESTART:
 183    case PIPE_CAP_TGSI_INSTANCEID:
 184    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 185    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 186    case PIPE_CAP_CONDITIONAL_RENDER:
 187    case PIPE_CAP_TEXTURE_BARRIER:
 188    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 189    case PIPE_CAP_START_INSTANCE:
 190    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 191    case PIPE_CAP_DRAW_INDIRECT:
 192    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 193    case PIPE_CAP_USER_INDEX_BUFFERS:
 194    case PIPE_CAP_USER_VERTEX_BUFFERS:
 195    case PIPE_CAP_TEXTURE_QUERY_LOD:
 196    case PIPE_CAP_SAMPLE_SHADING:
 197    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 198    case PIPE_CAP_TEXTURE_GATHER_SM5:
 199    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 200    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 201    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 202    case PIPE_CAP_CLIP_HALFZ:
 203    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 204    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 205    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 206    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 207    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 208    case PIPE_CAP_TGSI_TXQS:
 209    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 210    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 211    case PIPE_CAP_SHAREABLE_SHADERS:
 212    case PIPE_CAP_CLEAR_TEXTURE:
 213    case PIPE_CAP_DRAW_PARAMETERS:
 214    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 215    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 216    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 217    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 218    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 219       return 1;
 220    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 221       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 222    case PIPE_CAP_COMPUTE:
 223       if (debug_get_bool_option("NVF0_COMPUTE", false))
 224          return 1;
 225       return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
 226    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 227       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 228
 229    /* unsupported caps */
 230    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 231    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 232    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 233    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 234    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 235    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 236    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 237    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 238    case PIPE_CAP_FAKE_SW_MSAA:
 239    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 240    case PIPE_CAP_VERTEXID_NOBASE:
 241    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 242    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 243    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 244    case PIPE_CAP_INVALIDATE_BUFFER:
 245    case PIPE_CAP_GENERATE_MIPMAP:
 246    case PIPE_CAP_STRING_MARKER:
 247    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 248    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 249    case PIPE_CAP_QUERY_MEMORY_INFO:
 250    case PIPE_CAP_PCI_GROUP:
 251    case PIPE_CAP_PCI_BUS:
 252    case PIPE_CAP_PCI_DEVICE:
 253    case PIPE_CAP_PCI_FUNCTION:
 254       return 0;
 255
 256    case PIPE_CAP_VENDOR_ID:
 257       return 0x10de;
 258    case PIPE_CAP_DEVICE_ID: {
 259       uint64_t device_id;
 260       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 261          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 262          return -1;
 263       }
 264       return device_id;
 265    }
 266    case PIPE_CAP_ACCELERATED:
 267       return 1;
 268    case PIPE_CAP_VIDEO_MEMORY:
 269       return dev->vram_size >> 20;
 270    case PIPE_CAP_UMA:
 271       return 0;
 272    }
 273
 274    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 275    return 0;
 276 }
 277
 278 static int
 279 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 280                              enum pipe_shader_cap param)
 281 {
 282    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 283
 284    switch (shader) {
 285    case PIPE_SHADER_VERTEX:
 286    case PIPE_SHADER_GEOMETRY:
 287    case PIPE_SHADER_FRAGMENT:
 288       break;
 289    case PIPE_SHADER_TESS_CTRL:
 290    case PIPE_SHADER_TESS_EVAL:
 291       if (class_3d >= GM107_3D_CLASS)
 292          return 0;
 293       break;
 294    case PIPE_SHADER_COMPUTE:
 295       if (!debug_get_bool_option("NVF0_COMPUTE", false))
 296          if (class_3d > NVE4_3D_CLASS)
 297             return 0;
 298       break;
 299    default:
 300       return 0;
 301    }
 302
 303    switch (param) {
 304    case PIPE_SHADER_CAP_PREFERRED_IR:
 305       return PIPE_SHADER_IR_TGSI;
 306    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 307       if (class_3d == NVF0_3D_CLASS &&
 308           !debug_get_bool_option("NVF0_COMPUTE", false))
 309          return 0;
 310       return 1 << PIPE_SHADER_IR_TGSI;
 311    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 312    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 313    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 314    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 315       return 16384;
 316    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 317       return 16;
 318    case PIPE_SHADER_CAP_MAX_INPUTS:
 319       if (shader == PIPE_SHADER_VERTEX)
 320          return 32;
 321       /* NOTE: These only count our slots for GENERIC varyings.
 322        * The address space may be larger, but the actual hard limit seems to be
 323        * less than what the address space layout permits, so don't add TEXCOORD,
 324        * COLOR, etc. here.
 325        */
 326       if (shader == PIPE_SHADER_FRAGMENT)
 327          return 0x1f0 / 16;
 328       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 329        * and excludes 0x60 per-patch inputs.
 330        */
 331       return 0x200 / 16;
 332    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 333       return 32;
 334    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 335       return 65536;
 336    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 337       return NVC0_MAX_PIPE_CONSTBUFS;
 338    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 339       return shader != PIPE_SHADER_FRAGMENT;
 340    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 341       return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
 342    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 343    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 344       return 1;
 345    case PIPE_SHADER_CAP_MAX_PREDS:
 346       return 0;
 347    case PIPE_SHADER_CAP_MAX_TEMPS:
 348       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 349    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 350       return 1;
 351    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 352       return 1;
 353    case PIPE_SHADER_CAP_SUBROUTINES:
 354       return 1;
 355    case PIPE_SHADER_CAP_INTEGERS:
 356       return 1;
 357    case PIPE_SHADER_CAP_DOUBLES:
 358       return 1;
 359    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 360       return 1;
 361    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 362       return 1;
 363    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 364    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 365       return 0;
 366    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 367       return NVC0_MAX_BUFFERS;
 368    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 369       return 16; /* would be 32 in linked (OpenGL-style) mode */
 370    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 371       return 16; /* XXX not sure if more are really safe */
 372    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 373       return 32;
 374    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 375       return 0;
 376    default:
 377       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 378       return 0;
 379    }
 380 }
 381
 382 static float
 383 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 384 {
 385    switch (param) {
 386    case PIPE_CAPF_MAX_LINE_WIDTH:
 387    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 388       return 10.0f;
 389    case PIPE_CAPF_MAX_POINT_WIDTH:
 390       return 63.0f;
 391    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 392       return 63.375f;
 393    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 394       return 16.0f;
 395    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 396       return 15.0f;
 397    case PIPE_CAPF_GUARD_BAND_LEFT:
 398    case PIPE_CAPF_GUARD_BAND_TOP:
 399       return 0.0f;
 400    case PIPE_CAPF_GUARD_BAND_RIGHT:
 401    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 402       return 0.0f; /* that or infinity */
 403    }
 404
 405    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 406    return 0.0f;
 407 }
 408
 409 static int
 410 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 411                               enum pipe_shader_ir ir_type,
 412                               enum pipe_compute_cap param, void *data)
 413 {
 414    struct nvc0_screen *screen = nvc0_screen(pscreen);
 415    const uint16_t obj_class = screen->compute->oclass;
 416
 417 #define RET(x) do {                  \
 418    if (data)                         \
 419       memcpy(data, x, sizeof(x));    \
 420    return sizeof(x);                 \
 421 } while (0)
 422
 423    switch (param) {
 424    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 425       RET((uint64_t []) { 3 });
 426    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 427       if (obj_class >= NVE4_COMPUTE_CLASS) {
 428          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 429       } else {
 430          RET(((uint64_t []) { 65535, 65535, 65535 }));
 431       }
 432    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 433       RET(((uint64_t []) { 1024, 1024, 64 }));
 434    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 435       RET((uint64_t []) { 1024 });
 436    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 437       RET((uint64_t []) { 1ULL << 40 });
 438    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 439       RET((uint64_t []) { 48 << 10 });
 440    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 441       RET((uint64_t []) { 512 << 10 });
 442    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 443       RET((uint64_t []) { 4096 });
 444    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 445       RET((uint32_t []) { 32 });
 446    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 447       RET((uint64_t []) { 1ULL << 40 });
 448    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 449       RET((uint32_t []) { 0 });
 450    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 451       RET((uint32_t []) { screen->mp_count_compute });
 452    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 453       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 454    default:
 455       return 0;
 456    }
 457
 458 #undef RET
 459 }
 460
 461 static void
 462 nvc0_screen_destroy(struct pipe_screen *pscreen)
 463 {
 464    struct nvc0_screen *screen = nvc0_screen(pscreen);
 465
 466    if (!nouveau_drm_screen_unref(&screen->base))
 467       return;
 468
 469    if (screen->base.fence.current) {
 470       struct nouveau_fence *current = NULL;
 471
 472       /* nouveau_fence_wait will create a new current fence, so wait on the
 473        * _current_ one, and remove both.
 474        */
 475       nouveau_fence_ref(screen->base.fence.current, &current);
 476       nouveau_fence_wait(current, NULL);
 477       nouveau_fence_ref(NULL, &current);
 478       nouveau_fence_ref(NULL, &screen->base.fence.current);
 479    }
 480    if (screen->base.pushbuf)
 481       screen->base.pushbuf->user_priv = NULL;
 482
 483    if (screen->blitter)
 484       nvc0_blitter_destroy(screen);
 485    if (screen->pm.prog) {
 486       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 487       nvc0_program_destroy(NULL, screen->pm.prog);
 488       FREE(screen->pm.prog);
 489    }
 490
 491    nouveau_bo_ref(NULL, &screen->text);
 492    nouveau_bo_ref(NULL, &screen->uniform_bo);
 493    nouveau_bo_ref(NULL, &screen->tls);
 494    nouveau_bo_ref(NULL, &screen->txc);
 495    nouveau_bo_ref(NULL, &screen->fence.bo);
 496    nouveau_bo_ref(NULL, &screen->poly_cache);
 497    nouveau_bo_ref(NULL, &screen->parm);
 498
 499    nouveau_heap_destroy(&screen->lib_code);
 500    nouveau_heap_destroy(&screen->text_heap);
 501
 502    FREE(screen->tic.entries);
 503
 504    nouveau_object_del(&screen->eng3d);
 505    nouveau_object_del(&screen->eng2d);
 506    nouveau_object_del(&screen->m2mf);
 507    nouveau_object_del(&screen->compute);
 508    nouveau_object_del(&screen->nvsw);
 509
 510    nouveau_screen_fini(&screen->base);
 511
 512    FREE(screen);
 513 }
 514
 515 static int
 516 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 517                      unsigned size, const uint32_t *data)
 518 {
 519    struct nouveau_pushbuf *push = screen->base.pushbuf;
 520
 521    size /= 4;
 522
 523    assert((pos + size) <= 0x800);
 524
 525    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 526    PUSH_DATA (push, (m - 0x3800) / 8);
 527    PUSH_DATA (push, pos);
 528    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 529    PUSH_DATA (push, pos);
 530    PUSH_DATAp(push, data, size);
 531
 532    return pos + size;
 533 }
 534
 535 static void
 536 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 537 {
 538    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 539    PUSH_DATA (push, 0xff);
 540    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 541    PUSH_DATA (push, 0xff);
 542    PUSH_DATA (push, 0xff);
 543    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 544    PUSH_DATA (push, 0xff);
 545    PUSH_DATA (push, 0xff);
 546    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 547    PUSH_DATA (push, 0x3f);
 548
 549    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 550    PUSH_DATA (push, (3 << 16) | 3);
 551    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 552    PUSH_DATA (push, (2 << 16) | 2);
 553
 554    if (obj_class < GM107_3D_CLASS) {
 555       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 556       PUSH_DATA (push, 0);
 557    }
 558    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 559    PUSH_DATA (push, 0x10);
 560    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 561    PUSH_DATA (push, 0x10);
 562    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 563    PUSH_DATA (push, 0x10);
 564    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 565    PUSH_DATA (push, 0x10);
 566    PUSH_DATA (push, 0x10);
 567    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 568    PUSH_DATA (push, 0x10);
 569    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 570    PUSH_DATA (push, 0xe);
 571
 572    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 573    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 574    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 575    PUSH_DATA (push, 0);
 576    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 577    PUSH_DATA (push, 3);
 578
 579    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 580    PUSH_DATA (push, 0x3fffff);
 581    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 582    PUSH_DATA (push, 1);
 583    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 584    PUSH_DATA (push, 1);
 585
 586    if (obj_class < GM107_3D_CLASS) {
 587       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 588       PUSH_DATA (push, 3);
 589
 590       if (obj_class >= NVE4_3D_CLASS) {
 591          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 592          PUSH_DATA (push, 1);
 593       }
 594    }
 595
 596    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 597     * are supposed to do */
 598 }
 599
 600 static void
 601 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 602 {
 603    struct nvc0_screen *screen = nvc0_screen(pscreen);
 604    struct nouveau_pushbuf *push = screen->base.pushbuf;
 605
 606    /* we need to do it after possible flush in MARK_RING */
 607    *sequence = ++screen->base.fence.sequence;
 608
 609    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 610    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 611    PUSH_DATAh(push, screen->fence.bo->offset);
 612    PUSH_DATA (push, screen->fence.bo->offset);
 613    PUSH_DATA (push, *sequence);
 614    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 615               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 616 }
 617
 618 static u32
 619 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 620 {
 621    struct nvc0_screen *screen = nvc0_screen(pscreen);
 622    return screen->fence.map[0];
 623 }
 624
 625 static int
 626 nvc0_screen_init_compute(struct nvc0_screen *screen)
 627 {
 628    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 629
 630    switch (screen->base.device->chipset & ~0xf) {
 631    case 0xc0:
 632    case 0xd0:
 633       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 634    case 0xe0:
 635       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 636    case 0xf0:
 637    case 0x100:
 638    case 0x110:
 639       if (debug_get_bool_option("NVF0_COMPUTE", false))
 640          return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 641    case 0x120:
 642       return 0;
 643    default:
 644       return -1;
 645    }
 646 }
 647
 648 bool
 649 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 650                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 651 {
 652    struct nouveau_bo *bo = NULL;
 653    int ret;
 654    uint64_t size = (lpos + lneg) * 32 + cstack;
 655
 656    if (size >= (1 << 20)) {
 657       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 658       return false;
 659    }
 660
 661    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 662    size  = align(size, 0x8000);
 663    size *= screen->mp_count;
 664
 665    size = align(size, 1 << 17);
 666
 667    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 668                         NULL, &bo);
 669    if (ret) {
 670       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 671       return false;
 672    }
 673    nouveau_bo_ref(NULL, &screen->tls);
 674    screen->tls = bo;
 675    return true;
 676 }
 677
 678 #define FAIL_SCREEN_INIT(str, err)                    \
 679    do {                                               \
 680       NOUVEAU_ERR(str, err);                          \
 681       goto fail;                                      \
 682    } while(0)
 683
 684 struct nouveau_screen *
 685 nvc0_screen_create(struct nouveau_device *dev)
 686 {
 687    struct nvc0_screen *screen;
 688    struct pipe_screen *pscreen;
 689    struct nouveau_object *chan;
 690    struct nouveau_pushbuf *push;
 691    uint64_t value;
 692    uint32_t obj_class;
 693    uint32_t flags;
 694    int ret;
 695    unsigned i;
 696
 697    switch (dev->chipset & ~0xf) {
 698    case 0xc0:
 699    case 0xd0:
 700    case 0xe0:
 701    case 0xf0:
 702    case 0x100:
 703    case 0x110:
 704    case 0x120:
 705       break;
 706    default:
 707       return NULL;
 708    }
 709
 710    screen = CALLOC_STRUCT(nvc0_screen);
 711    if (!screen)
 712       return NULL;
 713    pscreen = &screen->base.base;
 714    pscreen->destroy = nvc0_screen_destroy;
 715
 716    ret = nouveau_screen_init(&screen->base, dev);
 717    if (ret) {
 718       nvc0_screen_destroy(pscreen);
 719       return NULL;
 720    }
 721    chan = screen->base.channel;
 722    push = screen->base.pushbuf;
 723    push->user_priv = screen;
 724    push->rsvd_kick = 5;
 725
 726    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 727       PIPE_BIND_SHADER_BUFFER |
 728       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 729       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 730    screen->base.sysmem_bindings |=
 731       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 732
 733    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 734       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 735       screen->base.vidmem_bindings = 0;
 736    }
 737
 738    pscreen->context_create = nvc0_create;
 739    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 740    pscreen->get_param = nvc0_screen_get_param;
 741    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 742    pscreen->get_paramf = nvc0_screen_get_paramf;
 743    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 744    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 745
 746    nvc0_screen_init_resource_functions(pscreen);
 747
 748    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 749    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 750
 751    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 752    if (screen->base.drm->version >= 0x01000202)
 753       flags |= NOUVEAU_BO_COHERENT;
 754
 755    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 756    if (ret)
 757       goto fail;
 758    nouveau_bo_map(screen->fence.bo, 0, NULL);
 759    screen->fence.map = screen->fence.bo->map;
 760    screen->base.fence.emit = nvc0_screen_fence_emit;
 761    screen->base.fence.update = nvc0_screen_fence_update;
 762
 763
 764    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 765                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 766    if (ret)
 767       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 768
 769    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 770    PUSH_DATA (push, screen->nvsw->handle);
 771
 772    switch (dev->chipset & ~0xf) {
 773    case 0x120:
 774    case 0x110:
 775    case 0x100:
 776    case 0xf0:
 777       obj_class = NVF0_P2MF_CLASS;
 778       break;
 779    case 0xe0:
 780       obj_class = NVE4_P2MF_CLASS;
 781       break;
 782    default:
 783       obj_class = NVC0_M2MF_CLASS;
 784       break;
 785    }
 786    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 787                             &screen->m2mf);
 788    if (ret)
 789       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 790
 791    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 792    PUSH_DATA (push, screen->m2mf->oclass);
 793    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 794       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 795       PUSH_DATA (push, 0xa0b5);
 796    }
 797
 798    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 799                             &screen->eng2d);
 800    if (ret)
 801       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 802
 803    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 804    PUSH_DATA (push, screen->eng2d->oclass);
 805    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 806    PUSH_DATA (push, 0);
 807    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 808    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 809    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 810    PUSH_DATA (push, 0);
 811    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 812    PUSH_DATA (push, 0);
 813    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 814    PUSH_DATA (push, 0x3f);
 815    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 816    PUSH_DATA (push, 1);
 817    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 818    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 819
 820    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 821    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 822    PUSH_DATA (push, screen->fence.bo->offset + 16);
 823
 824    switch (dev->chipset & ~0xf) {
 825    case 0x120:
 826       obj_class = GM200_3D_CLASS;
 827       break;
 828    case 0x110:
 829       obj_class = GM107_3D_CLASS;
 830       break;
 831    case 0x100:
 832    case 0xf0:
 833       obj_class = NVF0_3D_CLASS;
 834       break;
 835    case 0xe0:
 836       switch (dev->chipset) {
 837       case 0xea:
 838          obj_class = NVEA_3D_CLASS;
 839          break;
 840       default:
 841          obj_class = NVE4_3D_CLASS;
 842          break;
 843       }
 844       break;
 845    case 0xd0:
 846       obj_class = NVC8_3D_CLASS;
 847       break;
 848    case 0xc0:
 849    default:
 850       switch (dev->chipset) {
 851       case 0xc8:
 852          obj_class = NVC8_3D_CLASS;
 853          break;
 854       case 0xc1:
 855          obj_class = NVC1_3D_CLASS;
 856          break;
 857       default:
 858          obj_class = NVC0_3D_CLASS;
 859          break;
 860       }
 861       break;
 862    }
 863    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 864                             &screen->eng3d);
 865    if (ret)
 866       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 867    screen->base.class_3d = obj_class;
 868
 869    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 870    PUSH_DATA (push, screen->eng3d->oclass);
 871
 872    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 873    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 874
 875    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 876       /* kill shaders after about 1 second (at 100 MHz) */
 877       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 878       PUSH_DATA (push, 0x17);
 879    }
 880
 881    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 882                     screen->base.drm->version >= 0x01000101);
 883    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 884    for (i = 0; i < 8; ++i)
 885            PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 886
 887    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 888    PUSH_DATA (push, 1);
 889
 890    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 891    PUSH_DATA (push, 0);
 892    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 893    PUSH_DATA (push, 0);
 894    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 895    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 896    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 897    PUSH_DATA (push, 0);
 898    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 899    PUSH_DATA (push, 1);
 900    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 901    PUSH_DATA (push, 1);
 902    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 903    PUSH_DATA (push, 1);
 904    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 905    PUSH_DATA (push, 0);
 906    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 907    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 908    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 909       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 910    } else {
 911       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 912       PUSH_DATA (push, 15);
 913    }
 914    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 915    PUSH_DATA (push, 8); /* 128 */
 916    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 917    PUSH_DATA (push, 1);
 918    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 919       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 920       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 921    }
 922
 923    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 924
 925    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
 926                         &screen->text);
 927    if (ret)
 928       goto fail;
 929
 930    /* XXX: getting a page fault at the end of the code buffer every few
 931     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 932     */
 933    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 934
 935    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
 936                         &screen->uniform_bo);
 937    if (ret)
 938       goto fail;
 939
 940    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
 941
 942    for (i = 0; i < 5; ++i) {
 943       /* TIC and TSC entries for each unit (nve4+ only) */
 944       /* auxiliary constants (6 user clip planes, base instance id) */
 945       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 946       PUSH_DATA (push, 1024);
 947       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 948       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 949       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 950       PUSH_DATA (push, (15 << 4) | 1);
 951       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 952          unsigned j;
 953          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 954          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
 955          for (j = 0; j < 8; ++j)
 956             PUSH_DATA(push, j);
 957       } else {
 958          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 959          PUSH_DATA (push, 0x54);
 960       }
 961    }
 962    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 963    PUSH_DATA (push, 0);
 964
 965    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 966    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 967    PUSH_DATA (push, 256);
 968    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 969    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 970    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 971    PUSH_DATA (push, 0);
 972    PUSH_DATAf(push, 0.0f);
 973    PUSH_DATAf(push, 0.0f);
 974    PUSH_DATAf(push, 0.0f);
 975    PUSH_DATAf(push, 0.0f);
 976    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 977    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 978    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 979
 980    if (screen->base.drm->version >= 0x01000101) {
 981       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 982       if (ret) {
 983          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 984          goto fail;
 985       }
 986    } else {
 987       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 988          value = (8 << 8) | 4;
 989       else
 990          value = (16 << 8) | 4;
 991    }
 992    screen->gpc_count = value & 0x000000ff;
 993    screen->mp_count = value >> 8;
 994    screen->mp_count_compute = screen->mp_count;
 995
 996    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 997
 998    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 999    PUSH_DATAh(push, screen->text->offset);
1000    PUSH_DATA (push, screen->text->offset);
1001    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1002    PUSH_DATAh(push, screen->tls->offset);
1003    PUSH_DATA (push, screen->tls->offset);
1004    PUSH_DATA (push, screen->tls->size >> 32);
1005    PUSH_DATA (push, screen->tls->size);
1006    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1007    PUSH_DATA (push, 0);
1008    /* Reduce likelihood of collision with real buffers by placing the hole at
1009     * the top of the 4G area. This will have to be dealt with for real
1010     * eventually by blocking off that area from the VM.
1011     */
1012    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1013    PUSH_DATA (push, 0xff << 24);
1014
1015    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1016       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1017                            &screen->poly_cache);
1018       if (ret)
1019          goto fail;
1020
1021       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1022       PUSH_DATAh(push, screen->poly_cache->offset);
1023       PUSH_DATA (push, screen->poly_cache->offset);
1024       PUSH_DATA (push, 3);
1025    }
1026
1027    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1028                         &screen->txc);
1029    if (ret)
1030       goto fail;
1031
1032    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1033    PUSH_DATAh(push, screen->txc->offset);
1034    PUSH_DATA (push, screen->txc->offset);
1035    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1036    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1037       screen->tic.maxwell = true;
1038       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1039          screen->tic.maxwell =
1040             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1041          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1042       }
1043    }
1044
1045    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1046    PUSH_DATAh(push, screen->txc->offset + 65536);
1047    PUSH_DATA (push, screen->txc->offset + 65536);
1048    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1049
1050    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1051    PUSH_DATA (push, 0);
1052    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1053    PUSH_DATA (push, 0);
1054    PUSH_DATA (push, 0);
1055    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1056    PUSH_DATA (push, 0x3f);
1057
1058    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1059    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1060    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1061    for (i = 0; i < 8 * 2; ++i)
1062       PUSH_DATA(push, 0);
1063    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1064    PUSH_DATA (push, 0);
1065    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1066    PUSH_DATA (push, 0);
1067
1068    /* neither scissors, viewport nor stencil mask should affect clears */
1069    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1070    PUSH_DATA (push, 0);
1071
1072    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1073    PUSH_DATA (push, 1);
1074    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1075       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1076       PUSH_DATAf(push, 0.0f);
1077       PUSH_DATAf(push, 1.0f);
1078    }
1079    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1080    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1081
1082    /* We use scissors instead of exact view volume clipping,
1083     * so they're always enabled.
1084     */
1085    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1086       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1087       PUSH_DATA (push, 1);
1088       PUSH_DATA (push, 8192 << 16);
1089       PUSH_DATA (push, 8192 << 16);
1090    }
1091
1092 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1093
1094    i = 0;
1095    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1096    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1097    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1098    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1099    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1100    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1101    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1102    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1103    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1104    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1105    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1106    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1107    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1108
1109    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1110    PUSH_DATA (push, 1);
1111    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1112    PUSH_DATA (push, 1);
1113    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1114    PUSH_DATA (push, 0x40);
1115    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1116    PUSH_DATA (push, 0);
1117    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1118    PUSH_DATA (push, 0x30);
1119    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1120    PUSH_DATA (push, 3);
1121    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1122    PUSH_DATA (push, 0x20);
1123    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1124    PUSH_DATA (push, 0x00);
1125    screen->save_state.patch_vertices = 3;
1126
1127    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1128    PUSH_DATA (push, 0);
1129    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1130    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1131
1132    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1133
1134    if (nvc0_screen_init_compute(screen))
1135       goto fail;
1136
1137    PUSH_KICK (push);
1138
1139    screen->tic.entries = CALLOC(4096, sizeof(void *));
1140    screen->tsc.entries = screen->tic.entries + 2048;
1141
1142    if (!nvc0_blitter_create(screen))
1143       goto fail;
1144
1145    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1146
1147    return &screen->base;
1148
1149 fail:
1150    screen->base.base.context_create = NULL;
1151    return &screen->base;
1152 }
1153
1154 int
1155 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1156 {
1157    int i = screen->tic.next;
1158
1159    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1160       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1161
1162    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1163
1164    if (screen->tic.entries[i])
1165       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1166
1167    screen->tic.entries[i] = entry;
1168    return i;
1169 }
1170
1171 int
1172 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1173 {
1174    int i = screen->tsc.next;
1175
1176    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1177       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1178
1179    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1180
1181    if (screen->tsc.entries[i])
1182       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1183
1184    screen->tsc.entries[i] = entry;
1185    return i;
1186 }