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gallium: add PIPE_CAP_TGSI_ARRAY_COMPONENTS
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 const struct util_format_description *desc = util_format_description(format);
49
50 if (sample_count > 8)
51 return false;
52 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
53 return false;
54
55 /* Short-circuit the rest of the logic -- this is used by the state tracker
56 * to determine valid MS levels in a no-attachments scenario.
57 */
58 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
59 return true;
60
61 if (!util_format_is_supported(format, bindings))
62 return false;
63
64 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
65 if (util_format_get_blocksizebits(format) == 3 * 32)
66 return false;
67
68 if (bindings & PIPE_BIND_LINEAR)
69 if (util_format_is_depth_or_stencil(format) ||
70 (target != PIPE_TEXTURE_1D &&
71 target != PIPE_TEXTURE_2D &&
72 target != PIPE_TEXTURE_RECT) ||
73 sample_count > 1)
74 return false;
75
76 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
77 */
78 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
79 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
80 /* The claim is that this should work on GM107 but it doesn't. Need to
81 * test further and figure out if it's a nouveau issue or a HW one.
82 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
83 */
84 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
85 return false;
86
87 /* shared is always supported */
88 bindings &= ~(PIPE_BIND_LINEAR |
89 PIPE_BIND_SHARED);
90
91 if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
92 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
93 /* MS images are currently unsupported on Maxwell because they have to
94 * be handled explicitly. */
95 return false;
96 }
97
98 return (( nvc0_format_table[format].usage |
99 nvc0_vertex_format[format].usage) & bindings) == bindings;
100 }
101
102 static int
103 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
104 {
105 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
106 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
107
108 switch (param) {
109 /* non-boolean caps */
110 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
111 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
112 return 15;
113 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
114 return 12;
115 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
116 return 2048;
117 case PIPE_CAP_MIN_TEXEL_OFFSET:
118 return -8;
119 case PIPE_CAP_MAX_TEXEL_OFFSET:
120 return 7;
121 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
122 return -32;
123 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
124 return 31;
125 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
126 return 128 * 1024 * 1024;
127 case PIPE_CAP_GLSL_FEATURE_LEVEL:
128 if (class_3d <= NVF0_3D_CLASS)
129 return 430;
130 return 410;
131 case PIPE_CAP_MAX_RENDER_TARGETS:
132 return 8;
133 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
134 return 1;
135 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
136 return 4;
137 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
138 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
139 return 128;
140 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
141 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
142 return 1024;
143 case PIPE_CAP_MAX_VERTEX_STREAMS:
144 return 4;
145 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
146 return 2048;
147 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
148 return 256;
149 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
150 return 16; /* 256 for binding as RT, but that's not possible in GL */
151 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
152 return 16;
153 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
154 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
155 case PIPE_CAP_MAX_VIEWPORTS:
156 return NVC0_MAX_VIEWPORTS;
157 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
158 return 4;
159 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
160 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
161 case PIPE_CAP_ENDIANNESS:
162 return PIPE_ENDIAN_LITTLE;
163 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
164 return 30;
165 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
166 return NVC0_MAX_WINDOW_RECTANGLES;
167
168 /* supported caps */
169 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
170 case PIPE_CAP_TEXTURE_SWIZZLE:
171 case PIPE_CAP_TEXTURE_SHADOW_MAP:
172 case PIPE_CAP_NPOT_TEXTURES:
173 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
174 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
175 case PIPE_CAP_ANISOTROPIC_FILTER:
176 case PIPE_CAP_SEAMLESS_CUBE_MAP:
177 case PIPE_CAP_CUBE_MAP_ARRAY:
178 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
179 case PIPE_CAP_TEXTURE_MULTISAMPLE:
180 case PIPE_CAP_TWO_SIDED_STENCIL:
181 case PIPE_CAP_DEPTH_CLIP_DISABLE:
182 case PIPE_CAP_POINT_SPRITE:
183 case PIPE_CAP_TGSI_TEXCOORD:
184 case PIPE_CAP_SM3:
185 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
186 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
187 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
188 case PIPE_CAP_QUERY_TIMESTAMP:
189 case PIPE_CAP_QUERY_TIME_ELAPSED:
190 case PIPE_CAP_OCCLUSION_QUERY:
191 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
192 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
193 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
194 case PIPE_CAP_INDEP_BLEND_ENABLE:
195 case PIPE_CAP_INDEP_BLEND_FUNC:
196 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
197 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
198 case PIPE_CAP_PRIMITIVE_RESTART:
199 case PIPE_CAP_TGSI_INSTANCEID:
200 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
201 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
202 case PIPE_CAP_CONDITIONAL_RENDER:
203 case PIPE_CAP_TEXTURE_BARRIER:
204 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
205 case PIPE_CAP_START_INSTANCE:
206 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
207 case PIPE_CAP_DRAW_INDIRECT:
208 case PIPE_CAP_USER_CONSTANT_BUFFERS:
209 case PIPE_CAP_USER_INDEX_BUFFERS:
210 case PIPE_CAP_USER_VERTEX_BUFFERS:
211 case PIPE_CAP_TEXTURE_QUERY_LOD:
212 case PIPE_CAP_SAMPLE_SHADING:
213 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
214 case PIPE_CAP_TEXTURE_GATHER_SM5:
215 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
216 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
217 case PIPE_CAP_SAMPLER_VIEW_TARGET:
218 case PIPE_CAP_CLIP_HALFZ:
219 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
220 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
221 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
222 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
223 case PIPE_CAP_DEPTH_BOUNDS_TEST:
224 case PIPE_CAP_TGSI_TXQS:
225 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
226 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
227 case PIPE_CAP_SHAREABLE_SHADERS:
228 case PIPE_CAP_CLEAR_TEXTURE:
229 case PIPE_CAP_DRAW_PARAMETERS:
230 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
231 case PIPE_CAP_MULTI_DRAW_INDIRECT:
232 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
233 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
234 case PIPE_CAP_QUERY_BUFFER_OBJECT:
235 case PIPE_CAP_INVALIDATE_BUFFER:
236 case PIPE_CAP_STRING_MARKER:
237 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
238 case PIPE_CAP_CULL_DISTANCE:
239 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
240 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
241 case PIPE_CAP_TGSI_VOTE:
242 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
243 return 1;
244 case PIPE_CAP_COMPUTE:
245 return (class_3d < GP100_3D_CLASS);
246 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
247 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
248 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
249 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
250
251 /* unsupported caps */
252 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
253 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
254 case PIPE_CAP_SHADER_STENCIL_EXPORT:
255 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
256 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
257 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
258 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
259 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
260 case PIPE_CAP_FAKE_SW_MSAA:
261 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
262 case PIPE_CAP_VERTEXID_NOBASE:
263 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
264 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
265 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
266 case PIPE_CAP_GENERATE_MIPMAP:
267 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
268 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
269 case PIPE_CAP_QUERY_MEMORY_INFO:
270 case PIPE_CAP_PCI_GROUP:
271 case PIPE_CAP_PCI_BUS:
272 case PIPE_CAP_PCI_DEVICE:
273 case PIPE_CAP_PCI_FUNCTION:
274 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
275 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
276 return 0;
277
278 case PIPE_CAP_VENDOR_ID:
279 return 0x10de;
280 case PIPE_CAP_DEVICE_ID: {
281 uint64_t device_id;
282 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
283 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
284 return -1;
285 }
286 return device_id;
287 }
288 case PIPE_CAP_ACCELERATED:
289 return 1;
290 case PIPE_CAP_VIDEO_MEMORY:
291 return dev->vram_size >> 20;
292 case PIPE_CAP_UMA:
293 return 0;
294 }
295
296 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
297 return 0;
298 }
299
300 static int
301 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
302 enum pipe_shader_cap param)
303 {
304 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
305
306 switch (shader) {
307 case PIPE_SHADER_VERTEX:
308 case PIPE_SHADER_GEOMETRY:
309 case PIPE_SHADER_FRAGMENT:
310 case PIPE_SHADER_COMPUTE:
311 case PIPE_SHADER_TESS_CTRL:
312 case PIPE_SHADER_TESS_EVAL:
313 break;
314 default:
315 return 0;
316 }
317
318 switch (param) {
319 case PIPE_SHADER_CAP_PREFERRED_IR:
320 return PIPE_SHADER_IR_TGSI;
321 case PIPE_SHADER_CAP_SUPPORTED_IRS:
322 return 1 << PIPE_SHADER_IR_TGSI;
323 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
324 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
325 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
326 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
327 return 16384;
328 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
329 return 16;
330 case PIPE_SHADER_CAP_MAX_INPUTS:
331 if (shader == PIPE_SHADER_VERTEX)
332 return 32;
333 /* NOTE: These only count our slots for GENERIC varyings.
334 * The address space may be larger, but the actual hard limit seems to be
335 * less than what the address space layout permits, so don't add TEXCOORD,
336 * COLOR, etc. here.
337 */
338 if (shader == PIPE_SHADER_FRAGMENT)
339 return 0x1f0 / 16;
340 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
341 * and excludes 0x60 per-patch inputs.
342 */
343 return 0x200 / 16;
344 case PIPE_SHADER_CAP_MAX_OUTPUTS:
345 return 32;
346 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
347 return 65536;
348 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
349 return NVC0_MAX_PIPE_CONSTBUFS;
350 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
351 return shader != PIPE_SHADER_FRAGMENT;
352 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
353 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
354 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
355 return 1;
356 case PIPE_SHADER_CAP_MAX_PREDS:
357 return 0;
358 case PIPE_SHADER_CAP_MAX_TEMPS:
359 return NVC0_CAP_MAX_PROGRAM_TEMPS;
360 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
361 return 1;
362 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
363 return 1;
364 case PIPE_SHADER_CAP_SUBROUTINES:
365 return 1;
366 case PIPE_SHADER_CAP_INTEGERS:
367 return 1;
368 case PIPE_SHADER_CAP_DOUBLES:
369 return 1;
370 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
371 return 1;
372 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
373 return 1;
374 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
375 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
376 return 0;
377 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
378 return NVC0_MAX_BUFFERS;
379 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
380 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
381 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
382 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
383 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
384 return 32;
385 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
386 if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
387 return NVC0_MAX_IMAGES;
388 if (class_3d < NVE4_3D_CLASS)
389 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
390 return NVC0_MAX_IMAGES;
391 return 0;
392 default:
393 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
394 return 0;
395 }
396 }
397
398 static float
399 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
400 {
401 switch (param) {
402 case PIPE_CAPF_MAX_LINE_WIDTH:
403 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
404 return 10.0f;
405 case PIPE_CAPF_MAX_POINT_WIDTH:
406 return 63.0f;
407 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
408 return 63.375f;
409 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
410 return 16.0f;
411 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
412 return 15.0f;
413 case PIPE_CAPF_GUARD_BAND_LEFT:
414 case PIPE_CAPF_GUARD_BAND_TOP:
415 return 0.0f;
416 case PIPE_CAPF_GUARD_BAND_RIGHT:
417 case PIPE_CAPF_GUARD_BAND_BOTTOM:
418 return 0.0f; /* that or infinity */
419 }
420
421 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
422 return 0.0f;
423 }
424
425 static int
426 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
427 enum pipe_shader_ir ir_type,
428 enum pipe_compute_cap param, void *data)
429 {
430 struct nvc0_screen *screen = nvc0_screen(pscreen);
431 const uint16_t obj_class = screen->compute->oclass;
432
433 #define RET(x) do { \
434 if (data) \
435 memcpy(data, x, sizeof(x)); \
436 return sizeof(x); \
437 } while (0)
438
439 switch (param) {
440 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
441 RET((uint64_t []) { 3 });
442 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
443 if (obj_class >= NVE4_COMPUTE_CLASS) {
444 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
445 } else {
446 RET(((uint64_t []) { 65535, 65535, 65535 }));
447 }
448 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
449 RET(((uint64_t []) { 1024, 1024, 64 }));
450 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
451 RET((uint64_t []) { 1024 });
452 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
453 if (obj_class >= NVE4_COMPUTE_CLASS) {
454 RET((uint64_t []) { 1024 });
455 } else {
456 RET((uint64_t []) { 512 });
457 }
458 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
459 RET((uint64_t []) { 1ULL << 40 });
460 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
461 switch (obj_class) {
462 case GM200_COMPUTE_CLASS:
463 RET((uint64_t []) { 96 << 10 });
464 break;
465 case GM107_COMPUTE_CLASS:
466 RET((uint64_t []) { 64 << 10 });
467 break;
468 default:
469 RET((uint64_t []) { 48 << 10 });
470 break;
471 }
472 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
473 RET((uint64_t []) { 512 << 10 });
474 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
475 RET((uint64_t []) { 4096 });
476 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
477 RET((uint32_t []) { 32 });
478 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
479 RET((uint64_t []) { 1ULL << 40 });
480 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
481 RET((uint32_t []) { 0 });
482 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
483 RET((uint32_t []) { screen->mp_count_compute });
484 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
485 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
486 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
487 RET((uint32_t []) { 64 });
488 default:
489 return 0;
490 }
491
492 #undef RET
493 }
494
495 static void
496 nvc0_screen_destroy(struct pipe_screen *pscreen)
497 {
498 struct nvc0_screen *screen = nvc0_screen(pscreen);
499
500 if (!nouveau_drm_screen_unref(&screen->base))
501 return;
502
503 if (screen->base.fence.current) {
504 struct nouveau_fence *current = NULL;
505
506 /* nouveau_fence_wait will create a new current fence, so wait on the
507 * _current_ one, and remove both.
508 */
509 nouveau_fence_ref(screen->base.fence.current, &current);
510 nouveau_fence_wait(current, NULL);
511 nouveau_fence_ref(NULL, &current);
512 nouveau_fence_ref(NULL, &screen->base.fence.current);
513 }
514 if (screen->base.pushbuf)
515 screen->base.pushbuf->user_priv = NULL;
516
517 if (screen->blitter)
518 nvc0_blitter_destroy(screen);
519 if (screen->pm.prog) {
520 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
521 nvc0_program_destroy(NULL, screen->pm.prog);
522 FREE(screen->pm.prog);
523 }
524
525 nouveau_bo_ref(NULL, &screen->text);
526 nouveau_bo_ref(NULL, &screen->uniform_bo);
527 nouveau_bo_ref(NULL, &screen->tls);
528 nouveau_bo_ref(NULL, &screen->txc);
529 nouveau_bo_ref(NULL, &screen->fence.bo);
530 nouveau_bo_ref(NULL, &screen->poly_cache);
531
532 nouveau_heap_destroy(&screen->lib_code);
533 nouveau_heap_destroy(&screen->text_heap);
534
535 FREE(screen->tic.entries);
536
537 nouveau_object_del(&screen->eng3d);
538 nouveau_object_del(&screen->eng2d);
539 nouveau_object_del(&screen->m2mf);
540 nouveau_object_del(&screen->compute);
541 nouveau_object_del(&screen->nvsw);
542
543 nouveau_screen_fini(&screen->base);
544
545 FREE(screen);
546 }
547
548 static int
549 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
550 unsigned size, const uint32_t *data)
551 {
552 struct nouveau_pushbuf *push = screen->base.pushbuf;
553
554 size /= 4;
555
556 assert((pos + size) <= 0x800);
557
558 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
559 PUSH_DATA (push, (m - 0x3800) / 8);
560 PUSH_DATA (push, pos);
561 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
562 PUSH_DATA (push, pos);
563 PUSH_DATAp(push, data, size);
564
565 return pos + size;
566 }
567
568 static void
569 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
570 {
571 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
572 PUSH_DATA (push, 0xff);
573 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
574 PUSH_DATA (push, 0xff);
575 PUSH_DATA (push, 0xff);
576 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
577 PUSH_DATA (push, 0xff);
578 PUSH_DATA (push, 0xff);
579 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
580 PUSH_DATA (push, 0x3f);
581
582 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
583 PUSH_DATA (push, (3 << 16) | 3);
584 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
585 PUSH_DATA (push, (2 << 16) | 2);
586
587 if (obj_class < GM107_3D_CLASS) {
588 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
589 PUSH_DATA (push, 0);
590 }
591 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
592 PUSH_DATA (push, 0x10);
593 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
594 PUSH_DATA (push, 0x10);
595 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
596 PUSH_DATA (push, 0x10);
597 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
598 PUSH_DATA (push, 0x10);
599 PUSH_DATA (push, 0x10);
600 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
601 PUSH_DATA (push, 0x10);
602 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
603 PUSH_DATA (push, 0xe);
604
605 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
606 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
607 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
608 PUSH_DATA (push, 0);
609 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
610 PUSH_DATA (push, 3);
611
612 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
613 PUSH_DATA (push, 0x3fffff);
614 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
615 PUSH_DATA (push, 1);
616 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
617 PUSH_DATA (push, 1);
618
619 if (obj_class < GM107_3D_CLASS) {
620 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
621 PUSH_DATA (push, 3);
622
623 if (obj_class >= NVE4_3D_CLASS) {
624 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
625 PUSH_DATA (push, 1);
626 }
627 }
628
629 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
630 * are supposed to do */
631 }
632
633 static void
634 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
635 {
636 struct nvc0_screen *screen = nvc0_screen(pscreen);
637 struct nouveau_pushbuf *push = screen->base.pushbuf;
638
639 /* we need to do it after possible flush in MARK_RING */
640 *sequence = ++screen->base.fence.sequence;
641
642 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
643 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
644 PUSH_DATAh(push, screen->fence.bo->offset);
645 PUSH_DATA (push, screen->fence.bo->offset);
646 PUSH_DATA (push, *sequence);
647 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
648 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
649 }
650
651 static u32
652 nvc0_screen_fence_update(struct pipe_screen *pscreen)
653 {
654 struct nvc0_screen *screen = nvc0_screen(pscreen);
655 return screen->fence.map[0];
656 }
657
658 static int
659 nvc0_screen_init_compute(struct nvc0_screen *screen)
660 {
661 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
662
663 switch (screen->base.device->chipset & ~0xf) {
664 case 0xc0:
665 case 0xd0:
666 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
667 case 0xe0:
668 case 0xf0:
669 case 0x100:
670 case 0x110:
671 case 0x120:
672 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
673 case 0x130:
674 return 0;
675 default:
676 return -1;
677 }
678 }
679
680 static int
681 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
682 uint32_t lpos, uint32_t lneg, uint32_t cstack)
683 {
684 struct nouveau_bo *bo = NULL;
685 int ret;
686 uint64_t size = (lpos + lneg) * 32 + cstack;
687
688 if (size >= (1 << 20)) {
689 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
690 return -1;
691 }
692
693 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
694 size = align(size, 0x8000);
695 size *= screen->mp_count;
696
697 size = align(size, 1 << 17);
698
699 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
700 NULL, &bo);
701 if (ret)
702 return ret;
703 nouveau_bo_ref(NULL, &screen->tls);
704 screen->tls = bo;
705 return 0;
706 }
707
708 int
709 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
710 {
711 struct nouveau_pushbuf *push = screen->base.pushbuf;
712 struct nouveau_bo *bo;
713 int ret;
714
715 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
716 1 << 17, size, NULL, &bo);
717 if (ret)
718 return ret;
719
720 nouveau_bo_ref(NULL, &screen->text);
721 screen->text = bo;
722
723 nouveau_heap_destroy(&screen->lib_code);
724 nouveau_heap_destroy(&screen->text_heap);
725
726 /* XXX: getting a page fault at the end of the code buffer every few
727 * launches, don't use the last 256 bytes to work around them - prefetch ?
728 */
729 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
730
731 /* update the code segment setup */
732 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
733 PUSH_DATAh(push, screen->text->offset);
734 PUSH_DATA (push, screen->text->offset);
735 if (screen->compute) {
736 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
737 PUSH_DATAh(push, screen->text->offset);
738 PUSH_DATA (push, screen->text->offset);
739 }
740
741 return 0;
742 }
743
744 #define FAIL_SCREEN_INIT(str, err) \
745 do { \
746 NOUVEAU_ERR(str, err); \
747 goto fail; \
748 } while(0)
749
750 struct nouveau_screen *
751 nvc0_screen_create(struct nouveau_device *dev)
752 {
753 struct nvc0_screen *screen;
754 struct pipe_screen *pscreen;
755 struct nouveau_object *chan;
756 struct nouveau_pushbuf *push;
757 uint64_t value;
758 uint32_t obj_class;
759 uint32_t flags;
760 int ret;
761 unsigned i;
762
763 switch (dev->chipset & ~0xf) {
764 case 0xc0:
765 case 0xd0:
766 case 0xe0:
767 case 0xf0:
768 case 0x100:
769 case 0x110:
770 case 0x120:
771 case 0x130:
772 break;
773 default:
774 return NULL;
775 }
776
777 screen = CALLOC_STRUCT(nvc0_screen);
778 if (!screen)
779 return NULL;
780 pscreen = &screen->base.base;
781 pscreen->destroy = nvc0_screen_destroy;
782
783 ret = nouveau_screen_init(&screen->base, dev);
784 if (ret)
785 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
786 chan = screen->base.channel;
787 push = screen->base.pushbuf;
788 push->user_priv = screen;
789 push->rsvd_kick = 5;
790
791 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
792 PIPE_BIND_SHADER_BUFFER |
793 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
794 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
795 screen->base.sysmem_bindings |=
796 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
797
798 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
799 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
800 screen->base.vidmem_bindings = 0;
801 }
802
803 pscreen->context_create = nvc0_create;
804 pscreen->is_format_supported = nvc0_screen_is_format_supported;
805 pscreen->get_param = nvc0_screen_get_param;
806 pscreen->get_shader_param = nvc0_screen_get_shader_param;
807 pscreen->get_paramf = nvc0_screen_get_paramf;
808 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
809 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
810
811 nvc0_screen_init_resource_functions(pscreen);
812
813 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
814 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
815
816 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
817 if (screen->base.drm->version >= 0x01000202)
818 flags |= NOUVEAU_BO_COHERENT;
819
820 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
821 if (ret)
822 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
823 nouveau_bo_map(screen->fence.bo, 0, NULL);
824 screen->fence.map = screen->fence.bo->map;
825 screen->base.fence.emit = nvc0_screen_fence_emit;
826 screen->base.fence.update = nvc0_screen_fence_update;
827
828
829 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
830 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
831 if (ret)
832 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
833
834 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
835 PUSH_DATA (push, screen->nvsw->handle);
836
837 switch (dev->chipset & ~0xf) {
838 case 0x130:
839 case 0x120:
840 case 0x110:
841 case 0x100:
842 case 0xf0:
843 obj_class = NVF0_P2MF_CLASS;
844 break;
845 case 0xe0:
846 obj_class = NVE4_P2MF_CLASS;
847 break;
848 default:
849 obj_class = NVC0_M2MF_CLASS;
850 break;
851 }
852 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
853 &screen->m2mf);
854 if (ret)
855 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
856
857 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
858 PUSH_DATA (push, screen->m2mf->oclass);
859 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
860 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
861 PUSH_DATA (push, 0xa0b5);
862 }
863
864 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
865 &screen->eng2d);
866 if (ret)
867 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
868
869 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
870 PUSH_DATA (push, screen->eng2d->oclass);
871 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
872 PUSH_DATA (push, 0);
873 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
874 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
875 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
876 PUSH_DATA (push, 0);
877 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
878 PUSH_DATA (push, 0);
879 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
880 PUSH_DATA (push, 0x3f);
881 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
882 PUSH_DATA (push, 1);
883 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
884 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
885
886 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
887 PUSH_DATAh(push, screen->fence.bo->offset + 16);
888 PUSH_DATA (push, screen->fence.bo->offset + 16);
889
890 switch (dev->chipset & ~0xf) {
891 case 0x130:
892 obj_class = GP100_3D_CLASS;
893 break;
894 case 0x120:
895 obj_class = GM200_3D_CLASS;
896 break;
897 case 0x110:
898 obj_class = GM107_3D_CLASS;
899 break;
900 case 0x100:
901 case 0xf0:
902 obj_class = NVF0_3D_CLASS;
903 break;
904 case 0xe0:
905 switch (dev->chipset) {
906 case 0xea:
907 obj_class = NVEA_3D_CLASS;
908 break;
909 default:
910 obj_class = NVE4_3D_CLASS;
911 break;
912 }
913 break;
914 case 0xd0:
915 obj_class = NVC8_3D_CLASS;
916 break;
917 case 0xc0:
918 default:
919 switch (dev->chipset) {
920 case 0xc8:
921 obj_class = NVC8_3D_CLASS;
922 break;
923 case 0xc1:
924 obj_class = NVC1_3D_CLASS;
925 break;
926 default:
927 obj_class = NVC0_3D_CLASS;
928 break;
929 }
930 break;
931 }
932 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
933 &screen->eng3d);
934 if (ret)
935 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
936 screen->base.class_3d = obj_class;
937
938 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
939 PUSH_DATA (push, screen->eng3d->oclass);
940
941 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
942 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
943
944 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
945 /* kill shaders after about 1 second (at 100 MHz) */
946 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
947 PUSH_DATA (push, 0x17);
948 }
949
950 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
951 screen->base.drm->version >= 0x01000101);
952 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
953 for (i = 0; i < 8; ++i)
954 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
955
956 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
957 PUSH_DATA (push, 1);
958
959 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
960 PUSH_DATA (push, 0);
961 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
962 PUSH_DATA (push, 0);
963 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
964 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
965 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
966 PUSH_DATA (push, 0);
967 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
968 PUSH_DATA (push, 1);
969 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
970 PUSH_DATA (push, 1);
971 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
972 PUSH_DATA (push, 1);
973 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
974 PUSH_DATA (push, 0);
975 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
976 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
977 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
978 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
979 } else {
980 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
981 PUSH_DATA (push, 15);
982 }
983 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
984 PUSH_DATA (push, 8); /* 128 */
985 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
986 PUSH_DATA (push, 1);
987 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
988 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
989 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
990 }
991
992 nvc0_magic_3d_init(push, screen->eng3d->oclass);
993
994 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
995 if (ret)
996 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
997
998 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
999 &screen->uniform_bo);
1000 if (ret)
1001 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1002
1003 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1004
1005 for (i = 0; i < 5; ++i) {
1006 /* TIC and TSC entries for each unit (nve4+ only) */
1007 /* auxiliary constants (6 user clip planes, base instance id) */
1008 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1009 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1010 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1011 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1012 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1013 PUSH_DATA (push, (15 << 4) | 1);
1014 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1015 unsigned j;
1016 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1017 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1018 for (j = 0; j < 8; ++j)
1019 PUSH_DATA(push, j);
1020 } else {
1021 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1022 PUSH_DATA (push, 0x54);
1023 }
1024
1025 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1026 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1027 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1028 PUSH_DATA (push, 0); /* 0 */
1029 PUSH_DATA (push, 0);
1030 PUSH_DATA (push, 1); /* 1 */
1031 PUSH_DATA (push, 0);
1032 PUSH_DATA (push, 0); /* 2 */
1033 PUSH_DATA (push, 1);
1034 PUSH_DATA (push, 1); /* 3 */
1035 PUSH_DATA (push, 1);
1036 PUSH_DATA (push, 2); /* 4 */
1037 PUSH_DATA (push, 0);
1038 PUSH_DATA (push, 3); /* 5 */
1039 PUSH_DATA (push, 0);
1040 PUSH_DATA (push, 2); /* 6 */
1041 PUSH_DATA (push, 1);
1042 PUSH_DATA (push, 3); /* 7 */
1043 PUSH_DATA (push, 1);
1044 }
1045 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1046 PUSH_DATA (push, 0);
1047
1048 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1049 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1050 PUSH_DATA (push, 256);
1051 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1052 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1053 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1054 PUSH_DATA (push, 0);
1055 PUSH_DATAf(push, 0.0f);
1056 PUSH_DATAf(push, 0.0f);
1057 PUSH_DATAf(push, 0.0f);
1058 PUSH_DATAf(push, 0.0f);
1059 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1060 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1061 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1062
1063 if (screen->base.drm->version >= 0x01000101) {
1064 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1065 if (ret)
1066 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1067 } else {
1068 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1069 value = (8 << 8) | 4;
1070 else
1071 value = (16 << 8) | 4;
1072 }
1073 screen->gpc_count = value & 0x000000ff;
1074 screen->mp_count = value >> 8;
1075 screen->mp_count_compute = screen->mp_count;
1076
1077 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1078 if (ret)
1079 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1080
1081 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1082 PUSH_DATAh(push, screen->tls->offset);
1083 PUSH_DATA (push, screen->tls->offset);
1084 PUSH_DATA (push, screen->tls->size >> 32);
1085 PUSH_DATA (push, screen->tls->size);
1086 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1087 PUSH_DATA (push, 0);
1088 /* Reduce likelihood of collision with real buffers by placing the hole at
1089 * the top of the 4G area. This will have to be dealt with for real
1090 * eventually by blocking off that area from the VM.
1091 */
1092 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1093 PUSH_DATA (push, 0xff << 24);
1094
1095 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1096 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1097 &screen->poly_cache);
1098 if (ret)
1099 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1100
1101 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1102 PUSH_DATAh(push, screen->poly_cache->offset);
1103 PUSH_DATA (push, screen->poly_cache->offset);
1104 PUSH_DATA (push, 3);
1105 }
1106
1107 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1108 &screen->txc);
1109 if (ret)
1110 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1111
1112 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1113 PUSH_DATAh(push, screen->txc->offset);
1114 PUSH_DATA (push, screen->txc->offset);
1115 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1116 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1117 screen->tic.maxwell = true;
1118 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1119 screen->tic.maxwell =
1120 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1121 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1122 }
1123 }
1124
1125 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1126 PUSH_DATAh(push, screen->txc->offset + 65536);
1127 PUSH_DATA (push, screen->txc->offset + 65536);
1128 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1129
1130 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1131 PUSH_DATA (push, 0);
1132 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1133 PUSH_DATA (push, 0);
1134 PUSH_DATA (push, 0);
1135 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1136 PUSH_DATA (push, 0x3f);
1137
1138 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1139 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1140 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1141 for (i = 0; i < 8 * 2; ++i)
1142 PUSH_DATA(push, 0);
1143 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1144 PUSH_DATA (push, 0);
1145 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1146 PUSH_DATA (push, 0);
1147
1148 /* neither scissors, viewport nor stencil mask should affect clears */
1149 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1150 PUSH_DATA (push, 0);
1151
1152 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1153 PUSH_DATA (push, 1);
1154 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1155 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1156 PUSH_DATAf(push, 0.0f);
1157 PUSH_DATAf(push, 1.0f);
1158 }
1159 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1160 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1161
1162 /* We use scissors instead of exact view volume clipping,
1163 * so they're always enabled.
1164 */
1165 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1166 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1167 PUSH_DATA (push, 1);
1168 PUSH_DATA (push, 8192 << 16);
1169 PUSH_DATA (push, 8192 << 16);
1170 }
1171
1172 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1173
1174 i = 0;
1175 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1176 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1177 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1178 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1179 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1180 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1181 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1182 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1183 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1184 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1185 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1186 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1187 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1188
1189 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1190 PUSH_DATA (push, 1);
1191 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1192 PUSH_DATA (push, 1);
1193 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1194 PUSH_DATA (push, 0x40);
1195 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1196 PUSH_DATA (push, 0);
1197 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1198 PUSH_DATA (push, 0x30);
1199 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1200 PUSH_DATA (push, 3);
1201 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1202 PUSH_DATA (push, 0x20);
1203 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1204 PUSH_DATA (push, 0x00);
1205 screen->save_state.patch_vertices = 3;
1206
1207 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1208 PUSH_DATA (push, 0);
1209 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1210 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1211
1212 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1213
1214 if (nvc0_screen_init_compute(screen))
1215 goto fail;
1216
1217 PUSH_KICK (push);
1218
1219 screen->tic.entries = CALLOC(4096, sizeof(void *));
1220 screen->tsc.entries = screen->tic.entries + 2048;
1221
1222 if (!nvc0_blitter_create(screen))
1223 goto fail;
1224
1225 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1226
1227 return &screen->base;
1228
1229 fail:
1230 screen->base.base.context_create = NULL;
1231 return &screen->base;
1232 }
1233
1234 int
1235 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1236 {
1237 int i = screen->tic.next;
1238
1239 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1240 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1241
1242 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1243
1244 if (screen->tic.entries[i])
1245 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1246
1247 screen->tic.entries[i] = entry;
1248 return i;
1249 }
1250
1251 int
1252 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1253 {
1254 int i = screen->tsc.next;
1255
1256 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1257 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1258
1259 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1260
1261 if (screen->tsc.entries[i])
1262 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1263
1264 screen->tsc.entries[i] = entry;
1265 return i;
1266 }