src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    if (sample_count > 8)
  49       return false;
  50    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  51       return false;
  52
  53    if (!util_format_is_supported(format, bindings))
  54       return false;
  55
  56    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  57       if (util_format_get_blocksizebits(format) == 3 * 32)
  58          return false;
  59
  60    if (bindings & PIPE_BIND_LINEAR)
  61       if (util_format_is_depth_or_stencil(format) ||
  62           (target != PIPE_TEXTURE_1D &&
  63            target != PIPE_TEXTURE_2D &&
  64            target != PIPE_TEXTURE_RECT) ||
  65           sample_count > 1)
  66          return false;
  67
  68    /* transfers & shared are always supported */
  69    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  70                  PIPE_BIND_TRANSFER_WRITE |
  71                  PIPE_BIND_LINEAR |
  72                  PIPE_BIND_SHARED);
  73
  74    return (( nvc0_format_table[format].usage |
  75             nvc0_vertex_format[format].usage) & bindings) == bindings;
  76 }
  77
  78 static int
  79 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  80 {
  81    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  82    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  83
  84    switch (param) {
  85    /* non-boolean caps */
  86    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  87    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  88       return 15;
  89    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  90       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  91    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  92       return 2048;
  93    case PIPE_CAP_MIN_TEXEL_OFFSET:
  94       return -8;
  95    case PIPE_CAP_MAX_TEXEL_OFFSET:
  96       return 7;
  97    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  98       return -32;
  99    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 100       return 31;
 101    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 102       return 128 * 1024 * 1024;
 103    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 104       return 410;
 105    case PIPE_CAP_MAX_RENDER_TARGETS:
 106       return 8;
 107    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 108       return 1;
 109    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 110       return 4;
 111    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 112    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 113       return 128;
 114    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 115    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 116       return 1024;
 117    case PIPE_CAP_MAX_VERTEX_STREAMS:
 118       return 4;
 119    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 120       return 2048;
 121    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 122       return 256;
 123    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 124       return 16; /* 256 for binding as RT, but that's not possible in GL */
 125    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 126       return 16;
 127    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 128       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 129    case PIPE_CAP_MAX_VIEWPORTS:
 130       return NVC0_MAX_VIEWPORTS;
 131    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 132       return 4;
 133    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 134       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 135    case PIPE_CAP_ENDIANNESS:
 136       return PIPE_ENDIAN_LITTLE;
 137    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 138       return 30;
 139
 140    /* supported caps */
 141    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 142    case PIPE_CAP_TEXTURE_SWIZZLE:
 143    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 144    case PIPE_CAP_NPOT_TEXTURES:
 145    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 146    case PIPE_CAP_ANISOTROPIC_FILTER:
 147    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 148    case PIPE_CAP_CUBE_MAP_ARRAY:
 149    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 150    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 151    case PIPE_CAP_TWO_SIDED_STENCIL:
 152    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 153    case PIPE_CAP_POINT_SPRITE:
 154    case PIPE_CAP_TGSI_TEXCOORD:
 155    case PIPE_CAP_SM3:
 156    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 157    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 158    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 159    case PIPE_CAP_QUERY_TIMESTAMP:
 160    case PIPE_CAP_QUERY_TIME_ELAPSED:
 161    case PIPE_CAP_OCCLUSION_QUERY:
 162    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 163    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 164    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 165    case PIPE_CAP_INDEP_BLEND_ENABLE:
 166    case PIPE_CAP_INDEP_BLEND_FUNC:
 167    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 168    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 169    case PIPE_CAP_PRIMITIVE_RESTART:
 170    case PIPE_CAP_TGSI_INSTANCEID:
 171    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 172    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 173    case PIPE_CAP_CONDITIONAL_RENDER:
 174    case PIPE_CAP_TEXTURE_BARRIER:
 175    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 176    case PIPE_CAP_START_INSTANCE:
 177    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 178    case PIPE_CAP_DRAW_INDIRECT:
 179    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 180    case PIPE_CAP_USER_INDEX_BUFFERS:
 181    case PIPE_CAP_USER_VERTEX_BUFFERS:
 182    case PIPE_CAP_TEXTURE_QUERY_LOD:
 183    case PIPE_CAP_SAMPLE_SHADING:
 184    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 185    case PIPE_CAP_TEXTURE_GATHER_SM5:
 186    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 187    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 188    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 189    case PIPE_CAP_CLIP_HALFZ:
 190    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 191    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 192    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 193    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 194    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 195    case PIPE_CAP_TGSI_TXQS:
 196    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 197    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 198    case PIPE_CAP_SHAREABLE_SHADERS:
 199    case PIPE_CAP_CLEAR_TEXTURE:
 200    case PIPE_CAP_DRAW_PARAMETERS:
 201    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 202    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 203    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 204    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 205    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 206       return 1;
 207    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 208       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 209    case PIPE_CAP_COMPUTE:
 210       if (debug_get_bool_option("NVF0_COMPUTE", false))
 211          return 1;
 212       return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
 213    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 214       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 215
 216    /* unsupported caps */
 217    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 218    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 219    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 220    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 221    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 222    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 223    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 224    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 225    case PIPE_CAP_FAKE_SW_MSAA:
 226    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 227    case PIPE_CAP_VERTEXID_NOBASE:
 228    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 229    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 230    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 231    case PIPE_CAP_INVALIDATE_BUFFER:
 232    case PIPE_CAP_GENERATE_MIPMAP:
 233    case PIPE_CAP_STRING_MARKER:
 234    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 235    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 236    case PIPE_CAP_QUERY_MEMORY_INFO:
 237    case PIPE_CAP_PCI_GROUP:
 238    case PIPE_CAP_PCI_BUS:
 239    case PIPE_CAP_PCI_DEVICE:
 240    case PIPE_CAP_PCI_FUNCTION:
 241       return 0;
 242
 243    case PIPE_CAP_VENDOR_ID:
 244       return 0x10de;
 245    case PIPE_CAP_DEVICE_ID: {
 246       uint64_t device_id;
 247       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 248          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 249          return -1;
 250       }
 251       return device_id;
 252    }
 253    case PIPE_CAP_ACCELERATED:
 254       return 1;
 255    case PIPE_CAP_VIDEO_MEMORY:
 256       return dev->vram_size >> 20;
 257    case PIPE_CAP_UMA:
 258       return 0;
 259    }
 260
 261    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 262    return 0;
 263 }
 264
 265 static int
 266 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 267                              enum pipe_shader_cap param)
 268 {
 269    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 270
 271    switch (shader) {
 272    case PIPE_SHADER_VERTEX:
 273    case PIPE_SHADER_GEOMETRY:
 274    case PIPE_SHADER_FRAGMENT:
 275       break;
 276    case PIPE_SHADER_TESS_CTRL:
 277    case PIPE_SHADER_TESS_EVAL:
 278       if (class_3d >= GM107_3D_CLASS)
 279          return 0;
 280       break;
 281    case PIPE_SHADER_COMPUTE:
 282       if (!debug_get_bool_option("NVF0_COMPUTE", false))
 283          if (class_3d > NVE4_3D_CLASS)
 284             return 0;
 285       break;
 286    default:
 287       return 0;
 288    }
 289
 290    switch (param) {
 291    case PIPE_SHADER_CAP_PREFERRED_IR:
 292       return PIPE_SHADER_IR_TGSI;
 293    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 294       if (class_3d >= NVE4_3D_CLASS)
 295          return 0;
 296       return 1 << PIPE_SHADER_IR_TGSI;
 297    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 298    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 299    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 300    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 301       return 16384;
 302    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 303       return 16;
 304    case PIPE_SHADER_CAP_MAX_INPUTS:
 305       if (shader == PIPE_SHADER_VERTEX)
 306          return 32;
 307       /* NOTE: These only count our slots for GENERIC varyings.
 308        * The address space may be larger, but the actual hard limit seems to be
 309        * less than what the address space layout permits, so don't add TEXCOORD,
 310        * COLOR, etc. here.
 311        */
 312       if (shader == PIPE_SHADER_FRAGMENT)
 313          return 0x1f0 / 16;
 314       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 315        * and excludes 0x60 per-patch inputs.
 316        */
 317       return 0x200 / 16;
 318    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 319       return 32;
 320    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 321       return 65536;
 322    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 323       return NVC0_MAX_PIPE_CONSTBUFS;
 324    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 325       return shader != PIPE_SHADER_FRAGMENT;
 326    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 327       return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
 328    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 329    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 330       return 1;
 331    case PIPE_SHADER_CAP_MAX_PREDS:
 332       return 0;
 333    case PIPE_SHADER_CAP_MAX_TEMPS:
 334       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 335    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 336       return 1;
 337    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 338       return 1;
 339    case PIPE_SHADER_CAP_SUBROUTINES:
 340       return 1;
 341    case PIPE_SHADER_CAP_INTEGERS:
 342       return 1;
 343    case PIPE_SHADER_CAP_DOUBLES:
 344       return 1;
 345    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 346       return 1;
 347    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 348       return 1;
 349    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 350    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 351       return 0;
 352    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 353       return NVC0_MAX_BUFFERS;
 354    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 355       return 16; /* would be 32 in linked (OpenGL-style) mode */
 356    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 357       return 16; /* XXX not sure if more are really safe */
 358    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 359       return 32;
 360    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 361       return 0;
 362    default:
 363       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 364       return 0;
 365    }
 366 }
 367
 368 static float
 369 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 370 {
 371    switch (param) {
 372    case PIPE_CAPF_MAX_LINE_WIDTH:
 373    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 374       return 10.0f;
 375    case PIPE_CAPF_MAX_POINT_WIDTH:
 376       return 63.0f;
 377    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 378       return 63.375f;
 379    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 380       return 16.0f;
 381    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 382       return 15.0f;
 383    case PIPE_CAPF_GUARD_BAND_LEFT:
 384    case PIPE_CAPF_GUARD_BAND_TOP:
 385       return 0.0f;
 386    case PIPE_CAPF_GUARD_BAND_RIGHT:
 387    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 388       return 0.0f; /* that or infinity */
 389    }
 390
 391    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 392    return 0.0f;
 393 }
 394
 395 static int
 396 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 397                               enum pipe_compute_cap param, void *data)
 398 {
 399    struct nvc0_screen *screen = nvc0_screen(pscreen);
 400    const uint16_t obj_class = screen->compute->oclass;
 401
 402 #define RET(x) do {                  \
 403    if (data)                         \
 404       memcpy(data, x, sizeof(x));    \
 405    return sizeof(x);                 \
 406 } while (0)
 407
 408    switch (param) {
 409    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 410       RET((uint64_t []) { 3 });
 411    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 412       if (obj_class >= NVE4_COMPUTE_CLASS) {
 413          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 414       } else {
 415          RET(((uint64_t []) { 65535, 65535, 65535 }));
 416       }
 417    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 418       RET(((uint64_t []) { 1024, 1024, 64 }));
 419    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 420       RET((uint64_t []) { 1024 });
 421    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 422       RET((uint64_t []) { 1ULL << 40 });
 423    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 424       RET((uint64_t []) { 48 << 10 });
 425    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 426       RET((uint64_t []) { 512 << 10 });
 427    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 428       RET((uint64_t []) { 4096 });
 429    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 430       RET((uint32_t []) { 32 });
 431    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 432       RET((uint64_t []) { 1ULL << 40 });
 433    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 434       RET((uint32_t []) { 0 });
 435    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 436       RET((uint32_t []) { screen->mp_count_compute });
 437    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 438       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 439    default:
 440       return 0;
 441    }
 442
 443 #undef RET
 444 }
 445
 446 static void
 447 nvc0_screen_destroy(struct pipe_screen *pscreen)
 448 {
 449    struct nvc0_screen *screen = nvc0_screen(pscreen);
 450
 451    if (!nouveau_drm_screen_unref(&screen->base))
 452       return;
 453
 454    if (screen->base.fence.current) {
 455       struct nouveau_fence *current = NULL;
 456
 457       /* nouveau_fence_wait will create a new current fence, so wait on the
 458        * _current_ one, and remove both.
 459        */
 460       nouveau_fence_ref(screen->base.fence.current, &current);
 461       nouveau_fence_wait(current, NULL);
 462       nouveau_fence_ref(NULL, &current);
 463       nouveau_fence_ref(NULL, &screen->base.fence.current);
 464    }
 465    if (screen->base.pushbuf)
 466       screen->base.pushbuf->user_priv = NULL;
 467
 468    if (screen->blitter)
 469       nvc0_blitter_destroy(screen);
 470    if (screen->pm.prog) {
 471       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 472       nvc0_program_destroy(NULL, screen->pm.prog);
 473       FREE(screen->pm.prog);
 474    }
 475
 476    nouveau_bo_ref(NULL, &screen->text);
 477    nouveau_bo_ref(NULL, &screen->uniform_bo);
 478    nouveau_bo_ref(NULL, &screen->tls);
 479    nouveau_bo_ref(NULL, &screen->txc);
 480    nouveau_bo_ref(NULL, &screen->fence.bo);
 481    nouveau_bo_ref(NULL, &screen->poly_cache);
 482    nouveau_bo_ref(NULL, &screen->parm);
 483
 484    nouveau_heap_destroy(&screen->lib_code);
 485    nouveau_heap_destroy(&screen->text_heap);
 486
 487    FREE(screen->tic.entries);
 488
 489    nouveau_object_del(&screen->eng3d);
 490    nouveau_object_del(&screen->eng2d);
 491    nouveau_object_del(&screen->m2mf);
 492    nouveau_object_del(&screen->compute);
 493    nouveau_object_del(&screen->nvsw);
 494
 495    nouveau_screen_fini(&screen->base);
 496
 497    FREE(screen);
 498 }
 499
 500 static int
 501 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 502                      unsigned size, const uint32_t *data)
 503 {
 504    struct nouveau_pushbuf *push = screen->base.pushbuf;
 505
 506    size /= 4;
 507
 508    assert((pos + size) <= 0x800);
 509
 510    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 511    PUSH_DATA (push, (m - 0x3800) / 8);
 512    PUSH_DATA (push, pos);
 513    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 514    PUSH_DATA (push, pos);
 515    PUSH_DATAp(push, data, size);
 516
 517    return pos + size;
 518 }
 519
 520 static void
 521 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 522 {
 523    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 524    PUSH_DATA (push, 0xff);
 525    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 526    PUSH_DATA (push, 0xff);
 527    PUSH_DATA (push, 0xff);
 528    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 529    PUSH_DATA (push, 0xff);
 530    PUSH_DATA (push, 0xff);
 531    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 532    PUSH_DATA (push, 0x3f);
 533
 534    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 535    PUSH_DATA (push, (3 << 16) | 3);
 536    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 537    PUSH_DATA (push, (2 << 16) | 2);
 538
 539    if (obj_class < GM107_3D_CLASS) {
 540       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 541       PUSH_DATA (push, 0);
 542    }
 543    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 544    PUSH_DATA (push, 0x10);
 545    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 546    PUSH_DATA (push, 0x10);
 547    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 548    PUSH_DATA (push, 0x10);
 549    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 550    PUSH_DATA (push, 0x10);
 551    PUSH_DATA (push, 0x10);
 552    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 553    PUSH_DATA (push, 0x10);
 554    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 555    PUSH_DATA (push, 0xe);
 556
 557    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 558    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 559    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 560    PUSH_DATA (push, 0);
 561    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 562    PUSH_DATA (push, 3);
 563
 564    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 565    PUSH_DATA (push, 0x3fffff);
 566    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 567    PUSH_DATA (push, 1);
 568    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 569    PUSH_DATA (push, 1);
 570
 571    if (obj_class < GM107_3D_CLASS) {
 572       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 573       PUSH_DATA (push, 3);
 574
 575       if (obj_class >= NVE4_3D_CLASS) {
 576          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 577          PUSH_DATA (push, 1);
 578       }
 579    }
 580
 581    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 582     * are supposed to do */
 583 }
 584
 585 static void
 586 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 587 {
 588    struct nvc0_screen *screen = nvc0_screen(pscreen);
 589    struct nouveau_pushbuf *push = screen->base.pushbuf;
 590
 591    /* we need to do it after possible flush in MARK_RING */
 592    *sequence = ++screen->base.fence.sequence;
 593
 594    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 595    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 596    PUSH_DATAh(push, screen->fence.bo->offset);
 597    PUSH_DATA (push, screen->fence.bo->offset);
 598    PUSH_DATA (push, *sequence);
 599    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 600               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 601 }
 602
 603 static u32
 604 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 605 {
 606    struct nvc0_screen *screen = nvc0_screen(pscreen);
 607    return screen->fence.map[0];
 608 }
 609
 610 static int
 611 nvc0_screen_init_compute(struct nvc0_screen *screen)
 612 {
 613    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 614
 615    switch (screen->base.device->chipset & ~0xf) {
 616    case 0xc0:
 617    case 0xd0:
 618       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 619    case 0xe0:
 620       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 621    case 0xf0:
 622    case 0x100:
 623    case 0x110:
 624       if (debug_get_bool_option("NVF0_COMPUTE", false))
 625          return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 626    case 0x120:
 627       return 0;
 628    default:
 629       return -1;
 630    }
 631 }
 632
 633 bool
 634 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 635                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 636 {
 637    struct nouveau_bo *bo = NULL;
 638    int ret;
 639    uint64_t size = (lpos + lneg) * 32 + cstack;
 640
 641    if (size >= (1 << 20)) {
 642       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 643       return false;
 644    }
 645
 646    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 647    size  = align(size, 0x8000);
 648    size *= screen->mp_count;
 649
 650    size = align(size, 1 << 17);
 651
 652    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 653                         NULL, &bo);
 654    if (ret) {
 655       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 656       return false;
 657    }
 658    nouveau_bo_ref(NULL, &screen->tls);
 659    screen->tls = bo;
 660    return true;
 661 }
 662
 663 #define FAIL_SCREEN_INIT(str, err)                    \
 664    do {                                               \
 665       NOUVEAU_ERR(str, err);                          \
 666       goto fail;                                      \
 667    } while(0)
 668
 669 struct nouveau_screen *
 670 nvc0_screen_create(struct nouveau_device *dev)
 671 {
 672    struct nvc0_screen *screen;
 673    struct pipe_screen *pscreen;
 674    struct nouveau_object *chan;
 675    struct nouveau_pushbuf *push;
 676    uint64_t value;
 677    uint32_t obj_class;
 678    uint32_t flags;
 679    int ret;
 680    unsigned i;
 681
 682    switch (dev->chipset & ~0xf) {
 683    case 0xc0:
 684    case 0xd0:
 685    case 0xe0:
 686    case 0xf0:
 687    case 0x100:
 688    case 0x110:
 689    case 0x120:
 690       break;
 691    default:
 692       return NULL;
 693    }
 694
 695    screen = CALLOC_STRUCT(nvc0_screen);
 696    if (!screen)
 697       return NULL;
 698    pscreen = &screen->base.base;
 699    pscreen->destroy = nvc0_screen_destroy;
 700
 701    ret = nouveau_screen_init(&screen->base, dev);
 702    if (ret) {
 703       nvc0_screen_destroy(pscreen);
 704       return NULL;
 705    }
 706    chan = screen->base.channel;
 707    push = screen->base.pushbuf;
 708    push->user_priv = screen;
 709    push->rsvd_kick = 5;
 710
 711    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 712       PIPE_BIND_SHADER_BUFFER |
 713       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 714       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 715    screen->base.sysmem_bindings |=
 716       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 717
 718    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 719       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 720       screen->base.vidmem_bindings = 0;
 721    }
 722
 723    pscreen->context_create = nvc0_create;
 724    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 725    pscreen->get_param = nvc0_screen_get_param;
 726    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 727    pscreen->get_paramf = nvc0_screen_get_paramf;
 728    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 729    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 730
 731    nvc0_screen_init_resource_functions(pscreen);
 732
 733    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 734    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 735
 736    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 737    if (screen->base.drm->version >= 0x01000202)
 738       flags |= NOUVEAU_BO_COHERENT;
 739
 740    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 741    if (ret)
 742       goto fail;
 743    nouveau_bo_map(screen->fence.bo, 0, NULL);
 744    screen->fence.map = screen->fence.bo->map;
 745    screen->base.fence.emit = nvc0_screen_fence_emit;
 746    screen->base.fence.update = nvc0_screen_fence_update;
 747
 748
 749    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 750                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 751    if (ret)
 752       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 753
 754    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 755    PUSH_DATA (push, screen->nvsw->handle);
 756
 757    switch (dev->chipset & ~0xf) {
 758    case 0x120:
 759    case 0x110:
 760    case 0x100:
 761    case 0xf0:
 762       obj_class = NVF0_P2MF_CLASS;
 763       break;
 764    case 0xe0:
 765       obj_class = NVE4_P2MF_CLASS;
 766       break;
 767    default:
 768       obj_class = NVC0_M2MF_CLASS;
 769       break;
 770    }
 771    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 772                             &screen->m2mf);
 773    if (ret)
 774       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 775
 776    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 777    PUSH_DATA (push, screen->m2mf->oclass);
 778    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 779       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 780       PUSH_DATA (push, 0xa0b5);
 781    }
 782
 783    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 784                             &screen->eng2d);
 785    if (ret)
 786       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 787
 788    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 789    PUSH_DATA (push, screen->eng2d->oclass);
 790    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 791    PUSH_DATA (push, 0);
 792    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 793    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 794    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 795    PUSH_DATA (push, 0);
 796    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 797    PUSH_DATA (push, 0);
 798    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 799    PUSH_DATA (push, 0x3f);
 800    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 801    PUSH_DATA (push, 1);
 802    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 803    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 804
 805    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 806    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 807    PUSH_DATA (push, screen->fence.bo->offset + 16);
 808
 809    switch (dev->chipset & ~0xf) {
 810    case 0x120:
 811       obj_class = GM200_3D_CLASS;
 812       break;
 813    case 0x110:
 814       obj_class = GM107_3D_CLASS;
 815       break;
 816    case 0x100:
 817    case 0xf0:
 818       obj_class = NVF0_3D_CLASS;
 819       break;
 820    case 0xe0:
 821       switch (dev->chipset) {
 822       case 0xea:
 823          obj_class = NVEA_3D_CLASS;
 824          break;
 825       default:
 826          obj_class = NVE4_3D_CLASS;
 827          break;
 828       }
 829       break;
 830    case 0xd0:
 831       obj_class = NVC8_3D_CLASS;
 832       break;
 833    case 0xc0:
 834    default:
 835       switch (dev->chipset) {
 836       case 0xc8:
 837          obj_class = NVC8_3D_CLASS;
 838          break;
 839       case 0xc1:
 840          obj_class = NVC1_3D_CLASS;
 841          break;
 842       default:
 843          obj_class = NVC0_3D_CLASS;
 844          break;
 845       }
 846       break;
 847    }
 848    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 849                             &screen->eng3d);
 850    if (ret)
 851       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 852    screen->base.class_3d = obj_class;
 853
 854    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 855    PUSH_DATA (push, screen->eng3d->oclass);
 856
 857    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 858    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 859
 860    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 861       /* kill shaders after about 1 second (at 100 MHz) */
 862       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 863       PUSH_DATA (push, 0x17);
 864    }
 865
 866    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 867                     screen->base.drm->version >= 0x01000101);
 868    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 869    for (i = 0; i < 8; ++i)
 870            PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 871
 872    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 873    PUSH_DATA (push, 1);
 874
 875    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 876    PUSH_DATA (push, 0);
 877    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 878    PUSH_DATA (push, 0);
 879    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 880    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 881    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 882    PUSH_DATA (push, 0);
 883    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 884    PUSH_DATA (push, 1);
 885    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 886    PUSH_DATA (push, 1);
 887    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 888    PUSH_DATA (push, 1);
 889    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 890    PUSH_DATA (push, 0);
 891    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 892    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 893    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 894       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 895    } else {
 896       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 897       PUSH_DATA (push, 15);
 898    }
 899    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 900    PUSH_DATA (push, 8); /* 128 */
 901    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 902    PUSH_DATA (push, 1);
 903    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 904       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 905       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 906    }
 907
 908    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 909
 910    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
 911                         &screen->text);
 912    if (ret)
 913       goto fail;
 914
 915    /* XXX: getting a page fault at the end of the code buffer every few
 916     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 917     */
 918    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 919
 920    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
 921                         &screen->uniform_bo);
 922    if (ret)
 923       goto fail;
 924
 925    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
 926
 927    for (i = 0; i < 5; ++i) {
 928       /* TIC and TSC entries for each unit (nve4+ only) */
 929       /* auxiliary constants (6 user clip planes, base instance id) */
 930       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 931       PUSH_DATA (push, 1024);
 932       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 933       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 934       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 935       PUSH_DATA (push, (15 << 4) | 1);
 936       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 937          unsigned j;
 938          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 939          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
 940          for (j = 0; j < 8; ++j)
 941             PUSH_DATA(push, j);
 942       } else {
 943          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 944          PUSH_DATA (push, 0x54);
 945       }
 946    }
 947    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 948    PUSH_DATA (push, 0);
 949
 950    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 951    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 952    PUSH_DATA (push, 256);
 953    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 954    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 955    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 956    PUSH_DATA (push, 0);
 957    PUSH_DATAf(push, 0.0f);
 958    PUSH_DATAf(push, 0.0f);
 959    PUSH_DATAf(push, 0.0f);
 960    PUSH_DATAf(push, 0.0f);
 961    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 962    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 963    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 964
 965    if (screen->base.drm->version >= 0x01000101) {
 966       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 967       if (ret) {
 968          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 969          goto fail;
 970       }
 971    } else {
 972       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 973          value = (8 << 8) | 4;
 974       else
 975          value = (16 << 8) | 4;
 976    }
 977    screen->gpc_count = value & 0x000000ff;
 978    screen->mp_count = value >> 8;
 979    screen->mp_count_compute = screen->mp_count;
 980
 981    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 982
 983    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 984    PUSH_DATAh(push, screen->text->offset);
 985    PUSH_DATA (push, screen->text->offset);
 986    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 987    PUSH_DATAh(push, screen->tls->offset);
 988    PUSH_DATA (push, screen->tls->offset);
 989    PUSH_DATA (push, screen->tls->size >> 32);
 990    PUSH_DATA (push, screen->tls->size);
 991    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 992    PUSH_DATA (push, 0);
 993    /* Reduce likelihood of collision with real buffers by placing the hole at
 994     * the top of the 4G area. This will have to be dealt with for real
 995     * eventually by blocking off that area from the VM.
 996     */
 997    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 998    PUSH_DATA (push, 0xff << 24);
 999
1000    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1001       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1002                            &screen->poly_cache);
1003       if (ret)
1004          goto fail;
1005
1006       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1007       PUSH_DATAh(push, screen->poly_cache->offset);
1008       PUSH_DATA (push, screen->poly_cache->offset);
1009       PUSH_DATA (push, 3);
1010    }
1011
1012    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1013                         &screen->txc);
1014    if (ret)
1015       goto fail;
1016
1017    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1018    PUSH_DATAh(push, screen->txc->offset);
1019    PUSH_DATA (push, screen->txc->offset);
1020    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1021    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1022       screen->tic.maxwell = true;
1023       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1024          screen->tic.maxwell =
1025             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1026          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1027       }
1028    }
1029
1030    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1031    PUSH_DATAh(push, screen->txc->offset + 65536);
1032    PUSH_DATA (push, screen->txc->offset + 65536);
1033    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1034
1035    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1036    PUSH_DATA (push, 0);
1037    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1038    PUSH_DATA (push, 0);
1039    PUSH_DATA (push, 0);
1040    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1041    PUSH_DATA (push, 0x3f);
1042
1043    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1044    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1045    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1046    for (i = 0; i < 8 * 2; ++i)
1047       PUSH_DATA(push, 0);
1048    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1049    PUSH_DATA (push, 0);
1050    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1051    PUSH_DATA (push, 0);
1052
1053    /* neither scissors, viewport nor stencil mask should affect clears */
1054    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1055    PUSH_DATA (push, 0);
1056
1057    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1058    PUSH_DATA (push, 1);
1059    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1060       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1061       PUSH_DATAf(push, 0.0f);
1062       PUSH_DATAf(push, 1.0f);
1063    }
1064    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1065    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1066
1067    /* We use scissors instead of exact view volume clipping,
1068     * so they're always enabled.
1069     */
1070    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1071       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1072       PUSH_DATA (push, 1);
1073       PUSH_DATA (push, 8192 << 16);
1074       PUSH_DATA (push, 8192 << 16);
1075    }
1076
1077 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1078
1079    i = 0;
1080    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1081    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1082    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1083    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1084    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1085    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1086    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1087    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1088    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1089    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1090    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1091    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1092    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1093
1094    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1095    PUSH_DATA (push, 1);
1096    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1097    PUSH_DATA (push, 1);
1098    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1099    PUSH_DATA (push, 0x40);
1100    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1101    PUSH_DATA (push, 0);
1102    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1103    PUSH_DATA (push, 0x30);
1104    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1105    PUSH_DATA (push, 3);
1106    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1107    PUSH_DATA (push, 0x20);
1108    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1109    PUSH_DATA (push, 0x00);
1110    screen->save_state.patch_vertices = 3;
1111
1112    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1113    PUSH_DATA (push, 0);
1114    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1115    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1116
1117    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1118
1119    if (nvc0_screen_init_compute(screen))
1120       goto fail;
1121
1122    PUSH_KICK (push);
1123
1124    screen->tic.entries = CALLOC(4096, sizeof(void *));
1125    screen->tsc.entries = screen->tic.entries + 2048;
1126
1127    if (!nvc0_blitter_create(screen))
1128       goto fail;
1129
1130    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1131
1132    return &screen->base;
1133
1134 fail:
1135    screen->base.base.context_create = NULL;
1136    return &screen->base;
1137 }
1138
1139 int
1140 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1141 {
1142    int i = screen->tic.next;
1143
1144    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1145       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1146
1147    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1148
1149    if (screen->tic.entries[i])
1150       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1151
1152    screen->tic.entries[i] = entry;
1153    return i;
1154 }
1155
1156 int
1157 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1158 {
1159    int i = screen->tsc.next;
1160
1161    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1162       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1163
1164    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1165
1166    if (screen->tsc.entries[i])
1167       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1168
1169    screen->tsc.entries[i] = entry;
1170    return i;
1171 }