src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/mme/com9097.mme.h"
  36
  37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  39 #endif
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    if (sample_count > 8)
  49       return FALSE;
  50    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  51       return FALSE;
  52
  53    if (!util_format_is_supported(format, bindings))
  54       return FALSE;
  55
  56    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  57       if (util_format_get_blocksizebits(format) == 3 * 32)
  58          return FALSE;
  59
  60    /* transfers & shared are always supported */
  61    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  62                  PIPE_BIND_TRANSFER_WRITE |
  63                  PIPE_BIND_SHARED);
  64
  65    return (nvc0_format_table[format].usage & bindings) == bindings;
  66 }
  67
  68 static int
  69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  70 {
  71    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  72
  73    switch (param) {
  74    /* non-boolean caps */
  75    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  76    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  77       return 15;
  78    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  79       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  80    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  81       return 2048;
  82    case PIPE_CAP_MIN_TEXEL_OFFSET:
  83       return -8;
  84    case PIPE_CAP_MAX_TEXEL_OFFSET:
  85       return 7;
  86    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  87       return -32;
  88    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
  89       return 31;
  90    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  91       return 65536;
  92    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  93       return 400;
  94    case PIPE_CAP_MAX_RENDER_TARGETS:
  95       return 8;
  96    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  97       return 1;
  98    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
  99       return 4;
 100    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 101    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 102       return 128;
 103    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 104    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 105       return 1024;
 106    case PIPE_CAP_MAX_VERTEX_STREAMS:
 107       return 4;
 108    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 109       return 256;
 110    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 111       return 1; /* 256 for binding as RT, but that's not possible in GL */
 112    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 113       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 114    case PIPE_CAP_MAX_VIEWPORTS:
 115       return NVC0_MAX_VIEWPORTS;
 116    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 117       return 4;
 118    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 119       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 120    case PIPE_CAP_ENDIANNESS:
 121       return PIPE_ENDIAN_LITTLE;
 122
 123    /* supported caps */
 124    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 125    case PIPE_CAP_TEXTURE_SWIZZLE:
 126    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 127    case PIPE_CAP_NPOT_TEXTURES:
 128    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 129    case PIPE_CAP_ANISOTROPIC_FILTER:
 130    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 131    case PIPE_CAP_CUBE_MAP_ARRAY:
 132    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 133    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 134    case PIPE_CAP_TWO_SIDED_STENCIL:
 135    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 136    case PIPE_CAP_POINT_SPRITE:
 137    case PIPE_CAP_TGSI_TEXCOORD:
 138    case PIPE_CAP_SM3:
 139    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 140    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 141    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 142    case PIPE_CAP_QUERY_TIMESTAMP:
 143    case PIPE_CAP_QUERY_TIME_ELAPSED:
 144    case PIPE_CAP_OCCLUSION_QUERY:
 145    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 146    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 147    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 148    case PIPE_CAP_INDEP_BLEND_ENABLE:
 149    case PIPE_CAP_INDEP_BLEND_FUNC:
 150    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 151    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 152    case PIPE_CAP_PRIMITIVE_RESTART:
 153    case PIPE_CAP_TGSI_INSTANCEID:
 154    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 155    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 156    case PIPE_CAP_CONDITIONAL_RENDER:
 157    case PIPE_CAP_TEXTURE_BARRIER:
 158    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 159    case PIPE_CAP_START_INSTANCE:
 160    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 161    case PIPE_CAP_DRAW_INDIRECT:
 162    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 163    case PIPE_CAP_USER_INDEX_BUFFERS:
 164    case PIPE_CAP_USER_VERTEX_BUFFERS:
 165    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 166    case PIPE_CAP_TEXTURE_QUERY_LOD:
 167    case PIPE_CAP_SAMPLE_SHADING:
 168    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 169    case PIPE_CAP_TEXTURE_GATHER_SM5:
 170       return 1;
 171    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 172       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 173    case PIPE_CAP_COMPUTE:
 174       return (class_3d == NVE4_3D_CLASS) ? 1 : 0;
 175
 176    /* unsupported caps */
 177    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 178    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 179    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 180    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 181    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 182    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 183    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 184    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 185    case PIPE_CAP_FAKE_SW_MSAA:
 186    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 187       return 0;
 188    }
 189
 190    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 191    return 0;
 192 }
 193
 194 static int
 195 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 196                              enum pipe_shader_cap param)
 197 {
 198    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 199
 200    switch (shader) {
 201    case PIPE_SHADER_VERTEX:
 202       /*
 203    case PIPE_SHADER_TESSELLATION_CONTROL:
 204    case PIPE_SHADER_TESSELLATION_EVALUATION:
 205       */
 206    case PIPE_SHADER_GEOMETRY:
 207    case PIPE_SHADER_FRAGMENT:
 208       break;
 209    case PIPE_SHADER_COMPUTE:
 210       if (class_3d != NVE4_3D_CLASS)
 211          return 0;
 212       break;
 213    default:
 214       return 0;
 215    }
 216
 217    switch (param) {
 218    case PIPE_SHADER_CAP_PREFERRED_IR:
 219       return PIPE_SHADER_IR_TGSI;
 220    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 221    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 222    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 223    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 224       return 16384;
 225    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 226       return 16;
 227    case PIPE_SHADER_CAP_MAX_INPUTS:
 228       if (shader == PIPE_SHADER_VERTEX)
 229          return 32;
 230       /* NOTE: These only count our slots for GENERIC varyings.
 231        * The address space may be larger, but the actual hard limit seems to be
 232        * less than what the address space layout permits, so don't add TEXCOORD,
 233        * COLOR, etc. here.
 234        */
 235       if (shader == PIPE_SHADER_FRAGMENT)
 236          return 0x1f0 / 16;
 237       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 238        * and excludes 0x60 per-patch inputs.
 239        */
 240       return 0x200 / 16;
 241    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 242       return 65536;
 243    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 244       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 245          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 246       return NVC0_MAX_PIPE_CONSTBUFS;
 247    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 248    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 249       return shader != PIPE_SHADER_FRAGMENT;
 250    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 251    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 252       return 1;
 253    case PIPE_SHADER_CAP_MAX_PREDS:
 254       return 0;
 255    case PIPE_SHADER_CAP_MAX_TEMPS:
 256       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 257    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 258       return 1;
 259    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 260       return 0;
 261    case PIPE_SHADER_CAP_SUBROUTINES:
 262       return 1;
 263    case PIPE_SHADER_CAP_INTEGERS:
 264       return 1;
 265    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 266       return 16; /* would be 32 in linked (OpenGL-style) mode */
 267    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 268       return 16; /* XXX not sure if more are really safe */
 269    default:
 270       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 271       return 0;
 272    }
 273 }
 274
 275 static float
 276 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 277 {
 278    switch (param) {
 279    case PIPE_CAPF_MAX_LINE_WIDTH:
 280    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 281       return 10.0f;
 282    case PIPE_CAPF_MAX_POINT_WIDTH:
 283       return 63.0f;
 284    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 285       return 63.375f;
 286    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 287       return 16.0f;
 288    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 289       return 15.0f;
 290    case PIPE_CAPF_GUARD_BAND_LEFT:
 291    case PIPE_CAPF_GUARD_BAND_TOP:
 292       return 0.0f;
 293    case PIPE_CAPF_GUARD_BAND_RIGHT:
 294    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 295       return 0.0f; /* that or infinity */
 296    }
 297
 298    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 299    return 0.0f;
 300 }
 301
 302 static int
 303 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 304                               enum pipe_compute_cap param, void *data)
 305 {
 306    uint64_t *data64 = (uint64_t *)data;
 307    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
 308
 309    switch (param) {
 310    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 311       data64[0] = 3;
 312       return 8;
 313    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 314       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
 315       data64[1] = 65535;
 316       data64[2] = 65535;
 317       return 24;
 318    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 319       data64[0] = 1024;
 320       data64[1] = 1024;
 321       data64[2] = 64;
 322       return 24;
 323    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 324       data64[0] = 1024;
 325       return 8;
 326    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 327       data64[0] = (uint64_t)1 << 40;
 328       return 8;
 329    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 330       data64[0] = 48 << 10;
 331       return 8;
 332    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 333       data64[0] = 512 << 10;
 334       return 8;
 335    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 336       data64[0] = 4096;
 337       return 8;
 338    default:
 339       return 0;
 340    }
 341 }
 342
 343 static void
 344 nvc0_screen_destroy(struct pipe_screen *pscreen)
 345 {
 346    struct nvc0_screen *screen = nvc0_screen(pscreen);
 347
 348    if (!nouveau_drm_screen_unref(&screen->base))
 349       return;
 350
 351    if (screen->base.fence.current) {
 352       struct nouveau_fence *current = NULL;
 353
 354       /* nouveau_fence_wait will create a new current fence, so wait on the
 355        * _current_ one, and remove both.
 356        */
 357       nouveau_fence_ref(screen->base.fence.current, &current);
 358       nouveau_fence_wait(current);
 359       nouveau_fence_ref(NULL, &current);
 360       nouveau_fence_ref(NULL, &screen->base.fence.current);
 361    }
 362    if (screen->base.pushbuf)
 363       screen->base.pushbuf->user_priv = NULL;
 364
 365    if (screen->blitter)
 366       nvc0_blitter_destroy(screen);
 367    if (screen->pm.prog) {
 368       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 369       nvc0_program_destroy(NULL, screen->pm.prog);
 370    }
 371
 372    nouveau_bo_ref(NULL, &screen->text);
 373    nouveau_bo_ref(NULL, &screen->uniform_bo);
 374    nouveau_bo_ref(NULL, &screen->tls);
 375    nouveau_bo_ref(NULL, &screen->txc);
 376    nouveau_bo_ref(NULL, &screen->fence.bo);
 377    nouveau_bo_ref(NULL, &screen->poly_cache);
 378    nouveau_bo_ref(NULL, &screen->parm);
 379
 380    nouveau_heap_destroy(&screen->lib_code);
 381    nouveau_heap_destroy(&screen->text_heap);
 382
 383    FREE(screen->tic.entries);
 384
 385    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 386
 387    nouveau_object_del(&screen->eng3d);
 388    nouveau_object_del(&screen->eng2d);
 389    nouveau_object_del(&screen->m2mf);
 390    nouveau_object_del(&screen->compute);
 391    nouveau_object_del(&screen->nvsw);
 392
 393    nouveau_screen_fini(&screen->base);
 394
 395    FREE(screen);
 396 }
 397
 398 static int
 399 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 400                      unsigned size, const uint32_t *data)
 401 {
 402    struct nouveau_pushbuf *push = screen->base.pushbuf;
 403
 404    size /= 4;
 405
 406    assert((pos + size) <= 0x800);
 407
 408    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 409    PUSH_DATA (push, (m - 0x3800) / 8);
 410    PUSH_DATA (push, pos);
 411    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 412    PUSH_DATA (push, pos);
 413    PUSH_DATAp(push, data, size);
 414
 415    return pos + size;
 416 }
 417
 418 static void
 419 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 420 {
 421    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 422    PUSH_DATA (push, 0xff);
 423    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 424    PUSH_DATA (push, 0xff);
 425    PUSH_DATA (push, 0xff);
 426    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 427    PUSH_DATA (push, 0xff);
 428    PUSH_DATA (push, 0xff);
 429    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 430    PUSH_DATA (push, 0x3f);
 431
 432    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 433    PUSH_DATA (push, (3 << 16) | 3);
 434    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 435    PUSH_DATA (push, (2 << 16) | 2);
 436
 437    if (obj_class < GM107_3D_CLASS) {
 438       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 439       PUSH_DATA (push, 0);
 440    }
 441    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 442    PUSH_DATA (push, 0x10);
 443    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 444    PUSH_DATA (push, 0x10);
 445    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 446    PUSH_DATA (push, 0x10);
 447    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 448    PUSH_DATA (push, 0x10);
 449    PUSH_DATA (push, 0x10);
 450    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 451    PUSH_DATA (push, 0x10);
 452    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 453    PUSH_DATA (push, 0xe);
 454
 455    BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
 456    PUSH_DATA (push, 1 << 12);
 457    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 458    PUSH_DATA (push, 0);
 459    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 460    PUSH_DATA (push, 3);
 461
 462    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 463    PUSH_DATA (push, 0x3fffff);
 464    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 465    PUSH_DATA (push, 1);
 466    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 467    PUSH_DATA (push, 1);
 468
 469    if (obj_class < GM107_3D_CLASS) {
 470       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 471       PUSH_DATA (push, 3);
 472
 473       if (obj_class >= NVE4_3D_CLASS) {
 474          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 475          PUSH_DATA (push, 1);
 476       }
 477    }
 478
 479    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 480     * are supposed to do */
 481 }
 482
 483 static void
 484 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 485 {
 486    struct nvc0_screen *screen = nvc0_screen(pscreen);
 487    struct nouveau_pushbuf *push = screen->base.pushbuf;
 488
 489    /* we need to do it after possible flush in MARK_RING */
 490    *sequence = ++screen->base.fence.sequence;
 491
 492    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
 493    PUSH_DATAh(push, screen->fence.bo->offset);
 494    PUSH_DATA (push, screen->fence.bo->offset);
 495    PUSH_DATA (push, *sequence);
 496    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 497               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 498 }
 499
 500 static u32
 501 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 502 {
 503    struct nvc0_screen *screen = nvc0_screen(pscreen);
 504    return screen->fence.map[0];
 505 }
 506
 507 static int
 508 nvc0_screen_init_compute(struct nvc0_screen *screen)
 509 {
 510    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 511
 512    switch (screen->base.device->chipset & ~0xf) {
 513    case 0xc0:
 514    case 0xd0:
 515       /* Using COMPUTE has weird effects on 3D state, we need to
 516        * investigate this further before enabling it by default.
 517        */
 518       if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
 519          return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 520       return 0;
 521    case 0xe0:
 522       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 523    case 0xf0:
 524    case 0x100:
 525    case 0x110:
 526       return 0;
 527    default:
 528       return -1;
 529    }
 530 }
 531
 532 boolean
 533 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 534                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 535 {
 536    struct nouveau_bo *bo = NULL;
 537    int ret;
 538    uint64_t size = (lpos + lneg) * 32 + cstack;
 539
 540    if (size >= (1 << 20)) {
 541       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 542       return FALSE;
 543    }
 544
 545    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 546    size  = align(size, 0x8000);
 547    size *= screen->mp_count;
 548
 549    size = align(size, 1 << 17);
 550
 551    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
 552                         NULL, &bo);
 553    if (ret) {
 554       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 555       return FALSE;
 556    }
 557    nouveau_bo_ref(NULL, &screen->tls);
 558    screen->tls = bo;
 559    return TRUE;
 560 }
 561
 562 #define FAIL_SCREEN_INIT(str, err)                    \
 563    do {                                               \
 564       NOUVEAU_ERR(str, err);                          \
 565       nvc0_screen_destroy(pscreen);                   \
 566       return NULL;                                    \
 567    } while(0)
 568
 569 struct pipe_screen *
 570 nvc0_screen_create(struct nouveau_device *dev)
 571 {
 572    struct nvc0_screen *screen;
 573    struct pipe_screen *pscreen;
 574    struct nouveau_object *chan;
 575    struct nouveau_pushbuf *push;
 576    uint64_t value;
 577    uint32_t obj_class;
 578    int ret;
 579    unsigned i;
 580    union nouveau_bo_config mm_config;
 581
 582    switch (dev->chipset & ~0xf) {
 583    case 0xc0:
 584    case 0xd0:
 585    case 0xe0:
 586    case 0xf0:
 587    case 0x100:
 588    case 0x110:
 589       break;
 590    default:
 591       return NULL;
 592    }
 593
 594    screen = CALLOC_STRUCT(nvc0_screen);
 595    if (!screen)
 596       return NULL;
 597    pscreen = &screen->base.base;
 598
 599    ret = nouveau_screen_init(&screen->base, dev);
 600    if (ret) {
 601       nvc0_screen_destroy(pscreen);
 602       return NULL;
 603    }
 604    chan = screen->base.channel;
 605    push = screen->base.pushbuf;
 606    push->user_priv = screen;
 607    push->rsvd_kick = 5;
 608
 609    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 610       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 611       PIPE_BIND_COMMAND_ARGS_BUFFER;
 612    screen->base.sysmem_bindings |=
 613       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 614
 615    pscreen->destroy = nvc0_screen_destroy;
 616    pscreen->context_create = nvc0_create;
 617    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 618    pscreen->get_param = nvc0_screen_get_param;
 619    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 620    pscreen->get_paramf = nvc0_screen_get_paramf;
 621    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 622
 623    nvc0_screen_init_resource_functions(pscreen);
 624
 625    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 626    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 627
 628    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
 629                         &screen->fence.bo);
 630    if (ret)
 631       goto fail;
 632    nouveau_bo_map(screen->fence.bo, 0, NULL);
 633    screen->fence.map = screen->fence.bo->map;
 634    screen->base.fence.emit = nvc0_screen_fence_emit;
 635    screen->base.fence.update = nvc0_screen_fence_update;
 636
 637
 638    ret = nouveau_object_new(chan,
 639                             (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
 640                             NULL, 0, &screen->nvsw);
 641    if (ret)
 642       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 643
 644
 645    switch (dev->chipset & ~0xf) {
 646    case 0x110:
 647    case 0x100:
 648    case 0xf0:
 649       obj_class = NVF0_P2MF_CLASS;
 650       break;
 651    case 0xe0:
 652       obj_class = NVE4_P2MF_CLASS;
 653       break;
 654    default:
 655       obj_class = NVC0_M2MF_CLASS;
 656       break;
 657    }
 658    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 659                             &screen->m2mf);
 660    if (ret)
 661       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 662
 663    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 664    PUSH_DATA (push, screen->m2mf->oclass);
 665    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 666       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 667       PUSH_DATA (push, 0xa0b5);
 668    }
 669
 670    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 671                             &screen->eng2d);
 672    if (ret)
 673       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 674
 675    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 676    PUSH_DATA (push, screen->eng2d->oclass);
 677    BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
 678    PUSH_DATA (push, 0);
 679    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 680    PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
 681    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 682    PUSH_DATA (push, 0);
 683    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 684    PUSH_DATA (push, 0);
 685    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 686    PUSH_DATA (push, 0x3f);
 687    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 688    PUSH_DATA (push, 1);
 689    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 690    PUSH_DATA (push, NVC0_2D_COND_MODE_ALWAYS);
 691
 692    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 693    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 694    PUSH_DATA (push, screen->fence.bo->offset + 16);
 695
 696    switch (dev->chipset & ~0xf) {
 697    case 0x110:
 698       obj_class = GM107_3D_CLASS;
 699       break;
 700    case 0x100:
 701    case 0xf0:
 702       obj_class = NVF0_3D_CLASS;
 703       break;
 704    case 0xe0:
 705       switch (dev->chipset) {
 706       case 0xea:
 707          obj_class = NVEA_3D_CLASS;
 708          break;
 709       default:
 710          obj_class = NVE4_3D_CLASS;
 711          break;
 712       }
 713       break;
 714    case 0xd0:
 715       obj_class = NVC8_3D_CLASS;
 716       break;
 717    case 0xc0:
 718    default:
 719       switch (dev->chipset) {
 720       case 0xc8:
 721          obj_class = NVC8_3D_CLASS;
 722          break;
 723       case 0xc1:
 724          obj_class = NVC1_3D_CLASS;
 725          break;
 726       default:
 727          obj_class = NVC0_3D_CLASS;
 728          break;
 729       }
 730       break;
 731    }
 732    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 733                             &screen->eng3d);
 734    if (ret)
 735       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 736    screen->base.class_3d = obj_class;
 737
 738    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 739    PUSH_DATA (push, screen->eng3d->oclass);
 740
 741    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 742    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 743
 744    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 745       /* kill shaders after about 1 second (at 100 MHz) */
 746       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 747       PUSH_DATA (push, 0x17);
 748    }
 749
 750    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
 751    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 752    for (i = 0; i < 8; ++i)
 753            PUSH_DATA(push, dev->drm_version >= 0x01000101);
 754
 755    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 756    PUSH_DATA (push, 1);
 757
 758    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 759    PUSH_DATA (push, 0);
 760    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 761    PUSH_DATA (push, 0);
 762    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 763    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 764    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 765    PUSH_DATA (push, 0);
 766    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 767    PUSH_DATA (push, 1);
 768    BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
 769    PUSH_DATA (push, 0);
 770    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 771    PUSH_DATA (push, 1);
 772    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 773    PUSH_DATA (push, 1);
 774    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 775    PUSH_DATA (push, 0);
 776    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 777       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 778       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 779    } else {
 780       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 781       PUSH_DATA (push, 15);
 782    }
 783    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 784    PUSH_DATA (push, 8); /* 128 */
 785    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 786    PUSH_DATA (push, 1);
 787    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 788       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 789       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 790    }
 791
 792    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 793
 794    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 795                         &screen->text);
 796    if (ret)
 797       goto fail;
 798
 799    /* XXX: getting a page fault at the end of the code buffer every few
 800     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 801     */
 802    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 803
 804    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
 805                         &screen->uniform_bo);
 806    if (ret)
 807       goto fail;
 808
 809    PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 810
 811    for (i = 0; i < 5; ++i) {
 812       /* TIC and TSC entries for each unit (nve4+ only) */
 813       /* auxiliary constants (6 user clip planes, base instance id) */
 814       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 815       PUSH_DATA (push, 512);
 816       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 817       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 818       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 819       PUSH_DATA (push, (15 << 4) | 1);
 820       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 821          unsigned j;
 822          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 823          PUSH_DATA (push, 0);
 824          for (j = 0; j < 8; ++j)
 825             PUSH_DATA(push, j);
 826       } else {
 827          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 828          PUSH_DATA (push, 0x54);
 829       }
 830    }
 831    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 832    PUSH_DATA (push, 0);
 833
 834    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 835    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 836    PUSH_DATA (push, 256);
 837    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 838    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 839    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 840    PUSH_DATA (push, 0);
 841    PUSH_DATAf(push, 0.0f);
 842    PUSH_DATAf(push, 0.0f);
 843    PUSH_DATAf(push, 0.0f);
 844    PUSH_DATAf(push, 0.0f);
 845    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 846    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 847    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 848
 849    if (dev->drm_version >= 0x01000101) {
 850       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 851       if (ret) {
 852          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 853          goto fail;
 854       }
 855    } else {
 856       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 857          value = (8 << 8) | 4;
 858       else
 859          value = (16 << 8) | 4;
 860    }
 861    screen->mp_count = value >> 8;
 862    screen->mp_count_compute = screen->mp_count;
 863
 864    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 865
 866    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 867    PUSH_DATAh(push, screen->text->offset);
 868    PUSH_DATA (push, screen->text->offset);
 869    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 870    PUSH_DATAh(push, screen->tls->offset);
 871    PUSH_DATA (push, screen->tls->offset);
 872    PUSH_DATA (push, screen->tls->size >> 32);
 873    PUSH_DATA (push, screen->tls->size);
 874    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 875    PUSH_DATA (push, 0);
 876    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 877    PUSH_DATA (push, 0);
 878
 879    if (screen->eng3d->oclass < GM107_3D_CLASS) {
 880       ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 881                            &screen->poly_cache);
 882       if (ret)
 883          goto fail;
 884
 885       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 886       PUSH_DATAh(push, screen->poly_cache->offset);
 887       PUSH_DATA (push, screen->poly_cache->offset);
 888       PUSH_DATA (push, 3);
 889    }
 890
 891    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
 892                         &screen->txc);
 893    if (ret)
 894       goto fail;
 895
 896    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 897    PUSH_DATAh(push, screen->txc->offset);
 898    PUSH_DATA (push, screen->txc->offset);
 899    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 900
 901    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 902    PUSH_DATAh(push, screen->txc->offset + 65536);
 903    PUSH_DATA (push, screen->txc->offset + 65536);
 904    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 905
 906    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 907    PUSH_DATA (push, 0);
 908    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 909    PUSH_DATA (push, 0);
 910    PUSH_DATA (push, 0);
 911    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 912    PUSH_DATA (push, 0x3f);
 913
 914    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 915    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 916    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 917    for (i = 0; i < 8 * 2; ++i)
 918       PUSH_DATA(push, 0);
 919    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 920    PUSH_DATA (push, 0);
 921    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 922    PUSH_DATA (push, 0);
 923
 924    /* neither scissors, viewport nor stencil mask should affect clears */
 925    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 926    PUSH_DATA (push, 0);
 927
 928    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 929    PUSH_DATA (push, 1);
 930    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
 931       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
 932       PUSH_DATAf(push, 0.0f);
 933       PUSH_DATAf(push, 1.0f);
 934    }
 935    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 936    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 937
 938    /* We use scissors instead of exact view volume clipping,
 939     * so they're always enabled.
 940     */
 941    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
 942       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
 943       PUSH_DATA (push, 1);
 944       PUSH_DATA (push, 8192 << 16);
 945       PUSH_DATA (push, 8192 << 16);
 946    }
 947
 948 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 949
 950    i = 0;
 951    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
 952    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
 953    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
 954    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
 955    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
 956    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
 957    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
 958    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
 959    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
 960
 961    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
 962    PUSH_DATA (push, 1);
 963    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
 964    PUSH_DATA (push, 1);
 965    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 966    PUSH_DATA (push, 0x40);
 967    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
 968    PUSH_DATA (push, 0);
 969    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 970    PUSH_DATA (push, 0x30);
 971    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
 972    PUSH_DATA (push, 3);
 973    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
 974    PUSH_DATA (push, 0x20);
 975    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
 976    PUSH_DATA (push, 0x00);
 977
 978    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
 979    PUSH_DATA (push, 0);
 980    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
 981    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
 982
 983    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
 984
 985    if (nvc0_screen_init_compute(screen))
 986       goto fail;
 987
 988    PUSH_KICK (push);
 989
 990    screen->tic.entries = CALLOC(4096, sizeof(void *));
 991    screen->tsc.entries = screen->tic.entries + 2048;
 992
 993    mm_config.nvc0.tile_mode = 0;
 994    mm_config.nvc0.memtype = 0xfe0;
 995    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
 996
 997    if (!nvc0_blitter_create(screen))
 998       goto fail;
 999
1000    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
1001
1002    return pscreen;
1003
1004 fail:
1005    nvc0_screen_destroy(pscreen);
1006    return NULL;
1007 }
1008
1009 int
1010 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1011 {
1012    int i = screen->tic.next;
1013
1014    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1015       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1016
1017    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1018
1019    if (screen->tic.entries[i])
1020       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1021
1022    screen->tic.entries[i] = entry;
1023    return i;
1024 }
1025
1026 int
1027 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1028 {
1029    int i = screen->tsc.next;
1030
1031    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1032       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1033
1034    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1035
1036    if (screen->tsc.entries[i])
1037       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1038
1039    screen->tsc.entries[i] = entry;
1040    return i;
1041 }