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Merge remote-tracking branch 'jekstrand/wip/i965-uniforms' into vulkan
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 if (sample_count > 8)
48 return false;
49 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
50 return false;
51
52 if (!util_format_is_supported(format, bindings))
53 return false;
54
55 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
56 if (util_format_get_blocksizebits(format) == 3 * 32)
57 return false;
58
59 /* transfers & shared are always supported */
60 bindings &= ~(PIPE_BIND_TRANSFER_READ |
61 PIPE_BIND_TRANSFER_WRITE |
62 PIPE_BIND_SHARED);
63
64 return (nvc0_format_table[format].usage & bindings) == bindings;
65 }
66
67 static int
68 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
69 {
70 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
71 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
72
73 switch (param) {
74 /* non-boolean caps */
75 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
76 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
77 return 15;
78 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
79 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
80 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
81 return 2048;
82 case PIPE_CAP_MIN_TEXEL_OFFSET:
83 return -8;
84 case PIPE_CAP_MAX_TEXEL_OFFSET:
85 return 7;
86 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
87 return -32;
88 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
89 return 31;
90 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
91 return 128 * 1024 * 1024;
92 case PIPE_CAP_GLSL_FEATURE_LEVEL:
93 return 410;
94 case PIPE_CAP_MAX_RENDER_TARGETS:
95 return 8;
96 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
97 return 1;
98 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
99 return 4;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
101 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
102 return 128;
103 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
104 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
105 return 1024;
106 case PIPE_CAP_MAX_VERTEX_STREAMS:
107 return 4;
108 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
109 return 2048;
110 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
111 return 256;
112 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
113 return 1; /* 256 for binding as RT, but that's not possible in GL */
114 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
115 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
116 case PIPE_CAP_MAX_VIEWPORTS:
117 return NVC0_MAX_VIEWPORTS;
118 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
119 return 4;
120 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
121 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
122 case PIPE_CAP_ENDIANNESS:
123 return PIPE_ENDIAN_LITTLE;
124 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
125 return 30;
126
127 /* supported caps */
128 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
129 case PIPE_CAP_TEXTURE_SWIZZLE:
130 case PIPE_CAP_TEXTURE_SHADOW_MAP:
131 case PIPE_CAP_NPOT_TEXTURES:
132 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
133 case PIPE_CAP_ANISOTROPIC_FILTER:
134 case PIPE_CAP_SEAMLESS_CUBE_MAP:
135 case PIPE_CAP_CUBE_MAP_ARRAY:
136 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
137 case PIPE_CAP_TEXTURE_MULTISAMPLE:
138 case PIPE_CAP_TWO_SIDED_STENCIL:
139 case PIPE_CAP_DEPTH_CLIP_DISABLE:
140 case PIPE_CAP_POINT_SPRITE:
141 case PIPE_CAP_TGSI_TEXCOORD:
142 case PIPE_CAP_SM3:
143 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
144 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
145 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
146 case PIPE_CAP_QUERY_TIMESTAMP:
147 case PIPE_CAP_QUERY_TIME_ELAPSED:
148 case PIPE_CAP_OCCLUSION_QUERY:
149 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
150 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
151 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
152 case PIPE_CAP_INDEP_BLEND_ENABLE:
153 case PIPE_CAP_INDEP_BLEND_FUNC:
154 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
155 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
156 case PIPE_CAP_PRIMITIVE_RESTART:
157 case PIPE_CAP_TGSI_INSTANCEID:
158 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
159 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
160 case PIPE_CAP_CONDITIONAL_RENDER:
161 case PIPE_CAP_TEXTURE_BARRIER:
162 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
163 case PIPE_CAP_START_INSTANCE:
164 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
165 case PIPE_CAP_DRAW_INDIRECT:
166 case PIPE_CAP_USER_CONSTANT_BUFFERS:
167 case PIPE_CAP_USER_INDEX_BUFFERS:
168 case PIPE_CAP_USER_VERTEX_BUFFERS:
169 case PIPE_CAP_TEXTURE_QUERY_LOD:
170 case PIPE_CAP_SAMPLE_SHADING:
171 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
172 case PIPE_CAP_TEXTURE_GATHER_SM5:
173 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
174 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
175 case PIPE_CAP_SAMPLER_VIEW_TARGET:
176 case PIPE_CAP_CLIP_HALFZ:
177 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
178 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
179 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
180 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
181 case PIPE_CAP_DEPTH_BOUNDS_TEST:
182 case PIPE_CAP_TGSI_TXQS:
183 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
184 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
185 case PIPE_CAP_SHAREABLE_SHADERS:
186 case PIPE_CAP_CLEAR_TEXTURE:
187 case PIPE_CAP_DRAW_PARAMETERS:
188 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
189 case PIPE_CAP_MULTI_DRAW_INDIRECT:
190 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
191 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
192 return 1;
193 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
194 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
195 case PIPE_CAP_COMPUTE:
196 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
197 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
198 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
199
200 /* unsupported caps */
201 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
202 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
203 case PIPE_CAP_SHADER_STENCIL_EXPORT:
204 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
205 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
206 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
207 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
208 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
209 case PIPE_CAP_FAKE_SW_MSAA:
210 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
211 case PIPE_CAP_VERTEXID_NOBASE:
212 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
213 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
214 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
215 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
216 case PIPE_CAP_INVALIDATE_BUFFER:
217 case PIPE_CAP_GENERATE_MIPMAP:
218 return 0;
219
220 case PIPE_CAP_VENDOR_ID:
221 return 0x10de;
222 case PIPE_CAP_DEVICE_ID: {
223 uint64_t device_id;
224 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
225 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
226 return -1;
227 }
228 return device_id;
229 }
230 case PIPE_CAP_ACCELERATED:
231 return 1;
232 case PIPE_CAP_VIDEO_MEMORY:
233 return dev->vram_size >> 20;
234 case PIPE_CAP_UMA:
235 return 0;
236 }
237
238 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
239 return 0;
240 }
241
242 static int
243 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
244 enum pipe_shader_cap param)
245 {
246 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
247
248 switch (shader) {
249 case PIPE_SHADER_VERTEX:
250 case PIPE_SHADER_GEOMETRY:
251 case PIPE_SHADER_FRAGMENT:
252 break;
253 case PIPE_SHADER_TESS_CTRL:
254 case PIPE_SHADER_TESS_EVAL:
255 if (class_3d >= GM107_3D_CLASS)
256 return 0;
257 break;
258 case PIPE_SHADER_COMPUTE:
259 if (class_3d > NVE4_3D_CLASS)
260 return 0;
261 break;
262 default:
263 return 0;
264 }
265
266 switch (param) {
267 case PIPE_SHADER_CAP_PREFERRED_IR:
268 return PIPE_SHADER_IR_TGSI;
269 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
270 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
271 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
272 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
273 return 16384;
274 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
275 return 16;
276 case PIPE_SHADER_CAP_MAX_INPUTS:
277 if (shader == PIPE_SHADER_VERTEX)
278 return 32;
279 /* NOTE: These only count our slots for GENERIC varyings.
280 * The address space may be larger, but the actual hard limit seems to be
281 * less than what the address space layout permits, so don't add TEXCOORD,
282 * COLOR, etc. here.
283 */
284 if (shader == PIPE_SHADER_FRAGMENT)
285 return 0x1f0 / 16;
286 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
287 * and excludes 0x60 per-patch inputs.
288 */
289 return 0x200 / 16;
290 case PIPE_SHADER_CAP_MAX_OUTPUTS:
291 return 32;
292 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
293 return 65536;
294 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
295 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
296 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
297 return NVC0_MAX_PIPE_CONSTBUFS;
298 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
299 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
300 return shader != PIPE_SHADER_FRAGMENT;
301 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
302 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
303 return 1;
304 case PIPE_SHADER_CAP_MAX_PREDS:
305 return 0;
306 case PIPE_SHADER_CAP_MAX_TEMPS:
307 return NVC0_CAP_MAX_PROGRAM_TEMPS;
308 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
309 return 1;
310 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
311 return 0;
312 case PIPE_SHADER_CAP_SUBROUTINES:
313 return 1;
314 case PIPE_SHADER_CAP_INTEGERS:
315 return 1;
316 case PIPE_SHADER_CAP_DOUBLES:
317 return 1;
318 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
319 return 1;
320 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
321 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
322 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
323 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
324 return 0;
325 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
326 return 16; /* would be 32 in linked (OpenGL-style) mode */
327 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
328 return 16; /* XXX not sure if more are really safe */
329 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
330 return 32;
331 default:
332 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
333 return 0;
334 }
335 }
336
337 static float
338 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
339 {
340 switch (param) {
341 case PIPE_CAPF_MAX_LINE_WIDTH:
342 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
343 return 10.0f;
344 case PIPE_CAPF_MAX_POINT_WIDTH:
345 return 63.0f;
346 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
347 return 63.375f;
348 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
349 return 16.0f;
350 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
351 return 15.0f;
352 case PIPE_CAPF_GUARD_BAND_LEFT:
353 case PIPE_CAPF_GUARD_BAND_TOP:
354 return 0.0f;
355 case PIPE_CAPF_GUARD_BAND_RIGHT:
356 case PIPE_CAPF_GUARD_BAND_BOTTOM:
357 return 0.0f; /* that or infinity */
358 }
359
360 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
361 return 0.0f;
362 }
363
364 static int
365 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
366 enum pipe_compute_cap param, void *data)
367 {
368 struct nvc0_screen *screen = nvc0_screen(pscreen);
369 const uint16_t obj_class = screen->compute->oclass;
370
371 #define RET(x) do { \
372 if (data) \
373 memcpy(data, x, sizeof(x)); \
374 return sizeof(x); \
375 } while (0)
376
377 switch (param) {
378 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
379 RET((uint64_t []) { 3 });
380 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
381 if (obj_class >= NVE4_COMPUTE_CLASS) {
382 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
383 } else {
384 RET(((uint64_t []) { 65535, 65535, 65535 }));
385 }
386 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
387 RET(((uint64_t []) { 1024, 1024, 64 }));
388 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
389 RET((uint64_t []) { 1024 });
390 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
391 RET((uint64_t []) { 1ULL << 40 });
392 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
393 RET((uint64_t []) { 48 << 10 });
394 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
395 RET((uint64_t []) { 512 << 10 });
396 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
397 RET((uint64_t []) { 4096 });
398 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
399 RET((uint32_t []) { 32 });
400 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
401 RET((uint64_t []) { 1ULL << 40 });
402 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
403 RET((uint32_t []) { 0 });
404 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
405 RET((uint32_t []) { screen->mp_count_compute });
406 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
407 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
408 default:
409 return 0;
410 }
411
412 #undef RET
413 }
414
415 static void
416 nvc0_screen_destroy(struct pipe_screen *pscreen)
417 {
418 struct nvc0_screen *screen = nvc0_screen(pscreen);
419
420 if (!nouveau_drm_screen_unref(&screen->base))
421 return;
422
423 if (screen->base.fence.current) {
424 struct nouveau_fence *current = NULL;
425
426 /* nouveau_fence_wait will create a new current fence, so wait on the
427 * _current_ one, and remove both.
428 */
429 nouveau_fence_ref(screen->base.fence.current, &current);
430 nouveau_fence_wait(current, NULL);
431 nouveau_fence_ref(NULL, &current);
432 nouveau_fence_ref(NULL, &screen->base.fence.current);
433 }
434 if (screen->base.pushbuf)
435 screen->base.pushbuf->user_priv = NULL;
436
437 if (screen->blitter)
438 nvc0_blitter_destroy(screen);
439 if (screen->pm.prog) {
440 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
441 nvc0_program_destroy(NULL, screen->pm.prog);
442 FREE(screen->pm.prog);
443 }
444
445 nouveau_bo_ref(NULL, &screen->text);
446 nouveau_bo_ref(NULL, &screen->uniform_bo);
447 nouveau_bo_ref(NULL, &screen->tls);
448 nouveau_bo_ref(NULL, &screen->txc);
449 nouveau_bo_ref(NULL, &screen->fence.bo);
450 nouveau_bo_ref(NULL, &screen->poly_cache);
451 nouveau_bo_ref(NULL, &screen->parm);
452
453 nouveau_heap_destroy(&screen->lib_code);
454 nouveau_heap_destroy(&screen->text_heap);
455
456 FREE(screen->tic.entries);
457
458 nouveau_object_del(&screen->eng3d);
459 nouveau_object_del(&screen->eng2d);
460 nouveau_object_del(&screen->m2mf);
461 nouveau_object_del(&screen->compute);
462 nouveau_object_del(&screen->nvsw);
463
464 nouveau_screen_fini(&screen->base);
465
466 FREE(screen);
467 }
468
469 static int
470 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
471 unsigned size, const uint32_t *data)
472 {
473 struct nouveau_pushbuf *push = screen->base.pushbuf;
474
475 size /= 4;
476
477 assert((pos + size) <= 0x800);
478
479 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
480 PUSH_DATA (push, (m - 0x3800) / 8);
481 PUSH_DATA (push, pos);
482 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
483 PUSH_DATA (push, pos);
484 PUSH_DATAp(push, data, size);
485
486 return pos + size;
487 }
488
489 static void
490 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
491 {
492 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
493 PUSH_DATA (push, 0xff);
494 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
495 PUSH_DATA (push, 0xff);
496 PUSH_DATA (push, 0xff);
497 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
498 PUSH_DATA (push, 0xff);
499 PUSH_DATA (push, 0xff);
500 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
501 PUSH_DATA (push, 0x3f);
502
503 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
504 PUSH_DATA (push, (3 << 16) | 3);
505 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
506 PUSH_DATA (push, (2 << 16) | 2);
507
508 if (obj_class < GM107_3D_CLASS) {
509 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
510 PUSH_DATA (push, 0);
511 }
512 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
513 PUSH_DATA (push, 0x10);
514 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
515 PUSH_DATA (push, 0x10);
516 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
517 PUSH_DATA (push, 0x10);
518 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
519 PUSH_DATA (push, 0x10);
520 PUSH_DATA (push, 0x10);
521 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
522 PUSH_DATA (push, 0x10);
523 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
524 PUSH_DATA (push, 0xe);
525
526 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
527 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
528 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
529 PUSH_DATA (push, 0);
530 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
531 PUSH_DATA (push, 3);
532
533 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
534 PUSH_DATA (push, 0x3fffff);
535 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
536 PUSH_DATA (push, 1);
537 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
538 PUSH_DATA (push, 1);
539
540 if (obj_class < GM107_3D_CLASS) {
541 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
542 PUSH_DATA (push, 3);
543
544 if (obj_class >= NVE4_3D_CLASS) {
545 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
546 PUSH_DATA (push, 1);
547 }
548 }
549
550 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
551 * are supposed to do */
552 }
553
554 static void
555 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
556 {
557 struct nvc0_screen *screen = nvc0_screen(pscreen);
558 struct nouveau_pushbuf *push = screen->base.pushbuf;
559
560 /* we need to do it after possible flush in MARK_RING */
561 *sequence = ++screen->base.fence.sequence;
562
563 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
564 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
565 PUSH_DATAh(push, screen->fence.bo->offset);
566 PUSH_DATA (push, screen->fence.bo->offset);
567 PUSH_DATA (push, *sequence);
568 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
569 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
570 }
571
572 static u32
573 nvc0_screen_fence_update(struct pipe_screen *pscreen)
574 {
575 struct nvc0_screen *screen = nvc0_screen(pscreen);
576 return screen->fence.map[0];
577 }
578
579 static int
580 nvc0_screen_init_compute(struct nvc0_screen *screen)
581 {
582 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
583
584 switch (screen->base.device->chipset & ~0xf) {
585 case 0xc0:
586 case 0xd0:
587 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
588 case 0xe0:
589 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
590 case 0xf0:
591 case 0x100:
592 case 0x110:
593 return 0;
594 default:
595 return -1;
596 }
597 }
598
599 bool
600 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
601 uint32_t lpos, uint32_t lneg, uint32_t cstack)
602 {
603 struct nouveau_bo *bo = NULL;
604 int ret;
605 uint64_t size = (lpos + lneg) * 32 + cstack;
606
607 if (size >= (1 << 20)) {
608 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
609 return false;
610 }
611
612 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
613 size = align(size, 0x8000);
614 size *= screen->mp_count;
615
616 size = align(size, 1 << 17);
617
618 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
619 NULL, &bo);
620 if (ret) {
621 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
622 return false;
623 }
624 nouveau_bo_ref(NULL, &screen->tls);
625 screen->tls = bo;
626 return true;
627 }
628
629 #define FAIL_SCREEN_INIT(str, err) \
630 do { \
631 NOUVEAU_ERR(str, err); \
632 goto fail; \
633 } while(0)
634
635 struct nouveau_screen *
636 nvc0_screen_create(struct nouveau_device *dev)
637 {
638 struct nvc0_screen *screen;
639 struct pipe_screen *pscreen;
640 struct nouveau_object *chan;
641 struct nouveau_pushbuf *push;
642 uint64_t value;
643 uint32_t obj_class;
644 uint32_t flags;
645 int ret;
646 unsigned i;
647
648 switch (dev->chipset & ~0xf) {
649 case 0xc0:
650 case 0xd0:
651 case 0xe0:
652 case 0xf0:
653 case 0x100:
654 case 0x110:
655 break;
656 default:
657 return NULL;
658 }
659
660 screen = CALLOC_STRUCT(nvc0_screen);
661 if (!screen)
662 return NULL;
663 pscreen = &screen->base.base;
664 pscreen->destroy = nvc0_screen_destroy;
665
666 ret = nouveau_screen_init(&screen->base, dev);
667 if (ret) {
668 nvc0_screen_destroy(pscreen);
669 return NULL;
670 }
671 chan = screen->base.channel;
672 push = screen->base.pushbuf;
673 push->user_priv = screen;
674 push->rsvd_kick = 5;
675
676 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
677 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
678 PIPE_BIND_COMMAND_ARGS_BUFFER;
679 screen->base.sysmem_bindings |=
680 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
681
682 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
683 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
684 screen->base.vidmem_bindings = 0;
685 }
686
687 pscreen->context_create = nvc0_create;
688 pscreen->is_format_supported = nvc0_screen_is_format_supported;
689 pscreen->get_param = nvc0_screen_get_param;
690 pscreen->get_shader_param = nvc0_screen_get_shader_param;
691 pscreen->get_paramf = nvc0_screen_get_paramf;
692 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
693 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
694
695 nvc0_screen_init_resource_functions(pscreen);
696
697 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
698 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
699
700 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
701 if (screen->base.drm->version >= 0x01000202)
702 flags |= NOUVEAU_BO_COHERENT;
703
704 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
705 if (ret)
706 goto fail;
707 nouveau_bo_map(screen->fence.bo, 0, NULL);
708 screen->fence.map = screen->fence.bo->map;
709 screen->base.fence.emit = nvc0_screen_fence_emit;
710 screen->base.fence.update = nvc0_screen_fence_update;
711
712
713 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
714 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
715 if (ret)
716 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
717
718 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
719 PUSH_DATA (push, screen->nvsw->handle);
720
721 switch (dev->chipset & ~0xf) {
722 case 0x110:
723 case 0x100:
724 case 0xf0:
725 obj_class = NVF0_P2MF_CLASS;
726 break;
727 case 0xe0:
728 obj_class = NVE4_P2MF_CLASS;
729 break;
730 default:
731 obj_class = NVC0_M2MF_CLASS;
732 break;
733 }
734 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
735 &screen->m2mf);
736 if (ret)
737 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
738
739 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
740 PUSH_DATA (push, screen->m2mf->oclass);
741 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
742 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
743 PUSH_DATA (push, 0xa0b5);
744 }
745
746 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
747 &screen->eng2d);
748 if (ret)
749 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
750
751 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
752 PUSH_DATA (push, screen->eng2d->oclass);
753 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
754 PUSH_DATA (push, 0);
755 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
756 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
757 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
758 PUSH_DATA (push, 0);
759 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
760 PUSH_DATA (push, 0);
761 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
762 PUSH_DATA (push, 0x3f);
763 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
764 PUSH_DATA (push, 1);
765 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
766 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
767
768 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
769 PUSH_DATAh(push, screen->fence.bo->offset + 16);
770 PUSH_DATA (push, screen->fence.bo->offset + 16);
771
772 switch (dev->chipset & ~0xf) {
773 case 0x110:
774 obj_class = GM107_3D_CLASS;
775 break;
776 case 0x100:
777 case 0xf0:
778 obj_class = NVF0_3D_CLASS;
779 break;
780 case 0xe0:
781 switch (dev->chipset) {
782 case 0xea:
783 obj_class = NVEA_3D_CLASS;
784 break;
785 default:
786 obj_class = NVE4_3D_CLASS;
787 break;
788 }
789 break;
790 case 0xd0:
791 obj_class = NVC8_3D_CLASS;
792 break;
793 case 0xc0:
794 default:
795 switch (dev->chipset) {
796 case 0xc8:
797 obj_class = NVC8_3D_CLASS;
798 break;
799 case 0xc1:
800 obj_class = NVC1_3D_CLASS;
801 break;
802 default:
803 obj_class = NVC0_3D_CLASS;
804 break;
805 }
806 break;
807 }
808 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
809 &screen->eng3d);
810 if (ret)
811 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
812 screen->base.class_3d = obj_class;
813
814 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
815 PUSH_DATA (push, screen->eng3d->oclass);
816
817 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
818 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
819
820 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
821 /* kill shaders after about 1 second (at 100 MHz) */
822 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
823 PUSH_DATA (push, 0x17);
824 }
825
826 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
827 screen->base.drm->version >= 0x01000101);
828 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
829 for (i = 0; i < 8; ++i)
830 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
831
832 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
833 PUSH_DATA (push, 1);
834
835 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
836 PUSH_DATA (push, 0);
837 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
838 PUSH_DATA (push, 0);
839 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
840 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
841 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
842 PUSH_DATA (push, 0);
843 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
844 PUSH_DATA (push, 1);
845 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
846 PUSH_DATA (push, 1);
847 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
848 PUSH_DATA (push, 1);
849 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
850 PUSH_DATA (push, 0);
851 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
852 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
853 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
854 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
855 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
856 } else {
857 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
858 PUSH_DATA (push, 15);
859 }
860 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
861 PUSH_DATA (push, 8); /* 128 */
862 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
863 PUSH_DATA (push, 1);
864 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
865 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
866 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
867 }
868
869 nvc0_magic_3d_init(push, screen->eng3d->oclass);
870
871 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
872 &screen->text);
873 if (ret)
874 goto fail;
875
876 /* XXX: getting a page fault at the end of the code buffer every few
877 * launches, don't use the last 256 bytes to work around them - prefetch ?
878 */
879 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
880
881 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
882 &screen->uniform_bo);
883 if (ret)
884 goto fail;
885
886 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
887
888 for (i = 0; i < 5; ++i) {
889 /* TIC and TSC entries for each unit (nve4+ only) */
890 /* auxiliary constants (6 user clip planes, base instance id) */
891 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
892 PUSH_DATA (push, 512);
893 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
894 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
895 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
896 PUSH_DATA (push, (15 << 4) | 1);
897 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
898 unsigned j;
899 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
900 PUSH_DATA (push, 0);
901 for (j = 0; j < 8; ++j)
902 PUSH_DATA(push, j);
903 } else {
904 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
905 PUSH_DATA (push, 0x54);
906 }
907 }
908 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
909 PUSH_DATA (push, 0);
910
911 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
912 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
913 PUSH_DATA (push, 256);
914 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
915 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
916 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
917 PUSH_DATA (push, 0);
918 PUSH_DATAf(push, 0.0f);
919 PUSH_DATAf(push, 0.0f);
920 PUSH_DATAf(push, 0.0f);
921 PUSH_DATAf(push, 0.0f);
922 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
923 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
924 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
925
926 if (screen->base.drm->version >= 0x01000101) {
927 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
928 if (ret) {
929 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
930 goto fail;
931 }
932 } else {
933 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
934 value = (8 << 8) | 4;
935 else
936 value = (16 << 8) | 4;
937 }
938 screen->gpc_count = value & 0x000000ff;
939 screen->mp_count = value >> 8;
940 screen->mp_count_compute = screen->mp_count;
941
942 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
943
944 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
945 PUSH_DATAh(push, screen->text->offset);
946 PUSH_DATA (push, screen->text->offset);
947 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
948 PUSH_DATAh(push, screen->tls->offset);
949 PUSH_DATA (push, screen->tls->offset);
950 PUSH_DATA (push, screen->tls->size >> 32);
951 PUSH_DATA (push, screen->tls->size);
952 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
953 PUSH_DATA (push, 0);
954 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
955 PUSH_DATA (push, 0);
956
957 if (screen->eng3d->oclass < GM107_3D_CLASS) {
958 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
959 &screen->poly_cache);
960 if (ret)
961 goto fail;
962
963 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
964 PUSH_DATAh(push, screen->poly_cache->offset);
965 PUSH_DATA (push, screen->poly_cache->offset);
966 PUSH_DATA (push, 3);
967 }
968
969 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
970 &screen->txc);
971 if (ret)
972 goto fail;
973
974 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
975 PUSH_DATAh(push, screen->txc->offset);
976 PUSH_DATA (push, screen->txc->offset);
977 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
978
979 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
980 PUSH_DATAh(push, screen->txc->offset + 65536);
981 PUSH_DATA (push, screen->txc->offset + 65536);
982 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
983
984 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
985 PUSH_DATA (push, 0);
986 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
987 PUSH_DATA (push, 0);
988 PUSH_DATA (push, 0);
989 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
990 PUSH_DATA (push, 0x3f);
991
992 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
993 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
994 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
995 for (i = 0; i < 8 * 2; ++i)
996 PUSH_DATA(push, 0);
997 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
998 PUSH_DATA (push, 0);
999 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1000 PUSH_DATA (push, 0);
1001
1002 /* neither scissors, viewport nor stencil mask should affect clears */
1003 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1004 PUSH_DATA (push, 0);
1005
1006 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1007 PUSH_DATA (push, 1);
1008 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1009 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1010 PUSH_DATAf(push, 0.0f);
1011 PUSH_DATAf(push, 1.0f);
1012 }
1013 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1014 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1015
1016 /* We use scissors instead of exact view volume clipping,
1017 * so they're always enabled.
1018 */
1019 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1020 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1021 PUSH_DATA (push, 1);
1022 PUSH_DATA (push, 8192 << 16);
1023 PUSH_DATA (push, 8192 << 16);
1024 }
1025
1026 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1027
1028 i = 0;
1029 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1030 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1031 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1032 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1033 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1034 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1035 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1036 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1037 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1038 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1039 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1040
1041 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1042 PUSH_DATA (push, 1);
1043 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1044 PUSH_DATA (push, 1);
1045 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1046 PUSH_DATA (push, 0x40);
1047 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1048 PUSH_DATA (push, 0);
1049 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1050 PUSH_DATA (push, 0x30);
1051 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1052 PUSH_DATA (push, 3);
1053 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1054 PUSH_DATA (push, 0x20);
1055 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1056 PUSH_DATA (push, 0x00);
1057 screen->save_state.patch_vertices = 3;
1058
1059 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1060 PUSH_DATA (push, 0);
1061 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1062 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1063
1064 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1065
1066 if (nvc0_screen_init_compute(screen))
1067 goto fail;
1068
1069 PUSH_KICK (push);
1070
1071 screen->tic.entries = CALLOC(4096, sizeof(void *));
1072 screen->tsc.entries = screen->tic.entries + 2048;
1073
1074 if (!nvc0_blitter_create(screen))
1075 goto fail;
1076
1077 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1078
1079 return &screen->base;
1080
1081 fail:
1082 screen->base.base.context_create = NULL;
1083 return &screen->base;
1084 }
1085
1086 int
1087 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1088 {
1089 int i = screen->tic.next;
1090
1091 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1092 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1093
1094 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1095
1096 if (screen->tic.entries[i])
1097 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1098
1099 screen->tic.entries[i] = entry;
1100 return i;
1101 }
1102
1103 int
1104 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1105 {
1106 int i = screen->tsc.next;
1107
1108 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1109 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1110
1111 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1112
1113 if (screen->tsc.entries[i])
1114 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1115
1116 screen->tsc.entries[i] = entry;
1117 return i;
1118 }