gallium: add a cap to enable double rounding opcodes
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include "util/u_format.h"
26 #include "util/u_format_s3tc.h"
27 #include "pipe/p_screen.h"
28
29 #include "vl/vl_decoder.h"
30 #include "vl/vl_video_buffer.h"
31
32 #include "nouveau_vp3_video.h"
33
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_screen.h"
36
37 #include "nvc0/mme/com9097.mme.h"
38
39 static boolean
40 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
41 enum pipe_format format,
42 enum pipe_texture_target target,
43 unsigned sample_count,
44 unsigned bindings)
45 {
46 if (sample_count > 8)
47 return FALSE;
48 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
49 return FALSE;
50
51 if (!util_format_is_supported(format, bindings))
52 return FALSE;
53
54 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
55 if (util_format_get_blocksizebits(format) == 3 * 32)
56 return FALSE;
57
58 /* transfers & shared are always supported */
59 bindings &= ~(PIPE_BIND_TRANSFER_READ |
60 PIPE_BIND_TRANSFER_WRITE |
61 PIPE_BIND_SHARED);
62
63 return (nvc0_format_table[format].usage & bindings) == bindings;
64 }
65
66 static int
67 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
68 {
69 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
70 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
71
72 switch (param) {
73 /* non-boolean caps */
74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
76 return 15;
77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
78 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
80 return 2048;
81 case PIPE_CAP_MIN_TEXEL_OFFSET:
82 return -8;
83 case PIPE_CAP_MAX_TEXEL_OFFSET:
84 return 7;
85 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
86 return -32;
87 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
88 return 31;
89 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
90 return 65536;
91 case PIPE_CAP_GLSL_FEATURE_LEVEL:
92 return 400;
93 case PIPE_CAP_MAX_RENDER_TARGETS:
94 return 8;
95 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
96 return 1;
97 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
98 return 4;
99 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
100 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
101 return 128;
102 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
103 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
104 return 1024;
105 case PIPE_CAP_MAX_VERTEX_STREAMS:
106 return 4;
107 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
108 return 2048;
109 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
110 return 256;
111 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
112 return 1; /* 256 for binding as RT, but that's not possible in GL */
113 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
114 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
115 case PIPE_CAP_MAX_VIEWPORTS:
116 return NVC0_MAX_VIEWPORTS;
117 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
118 return 4;
119 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
120 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
121 case PIPE_CAP_ENDIANNESS:
122 return PIPE_ENDIAN_LITTLE;
123
124 /* supported caps */
125 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
126 case PIPE_CAP_TEXTURE_SWIZZLE:
127 case PIPE_CAP_TEXTURE_SHADOW_MAP:
128 case PIPE_CAP_NPOT_TEXTURES:
129 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
130 case PIPE_CAP_ANISOTROPIC_FILTER:
131 case PIPE_CAP_SEAMLESS_CUBE_MAP:
132 case PIPE_CAP_CUBE_MAP_ARRAY:
133 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
134 case PIPE_CAP_TEXTURE_MULTISAMPLE:
135 case PIPE_CAP_TWO_SIDED_STENCIL:
136 case PIPE_CAP_DEPTH_CLIP_DISABLE:
137 case PIPE_CAP_POINT_SPRITE:
138 case PIPE_CAP_TGSI_TEXCOORD:
139 case PIPE_CAP_SM3:
140 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
141 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
142 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
143 case PIPE_CAP_QUERY_TIMESTAMP:
144 case PIPE_CAP_QUERY_TIME_ELAPSED:
145 case PIPE_CAP_OCCLUSION_QUERY:
146 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
147 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
148 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
149 case PIPE_CAP_INDEP_BLEND_ENABLE:
150 case PIPE_CAP_INDEP_BLEND_FUNC:
151 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
152 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
153 case PIPE_CAP_PRIMITIVE_RESTART:
154 case PIPE_CAP_TGSI_INSTANCEID:
155 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
156 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
157 case PIPE_CAP_CONDITIONAL_RENDER:
158 case PIPE_CAP_TEXTURE_BARRIER:
159 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
160 case PIPE_CAP_START_INSTANCE:
161 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
162 case PIPE_CAP_DRAW_INDIRECT:
163 case PIPE_CAP_USER_CONSTANT_BUFFERS:
164 case PIPE_CAP_USER_INDEX_BUFFERS:
165 case PIPE_CAP_USER_VERTEX_BUFFERS:
166 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
167 case PIPE_CAP_TEXTURE_QUERY_LOD:
168 case PIPE_CAP_SAMPLE_SHADING:
169 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
170 case PIPE_CAP_TEXTURE_GATHER_SM5:
171 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
172 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
173 case PIPE_CAP_SAMPLER_VIEW_TARGET:
174 case PIPE_CAP_CLIP_HALFZ:
175 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
176 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
177 return 1;
178 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
179 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
180 case PIPE_CAP_COMPUTE:
181 return (class_3d == NVE4_3D_CLASS) ? 1 : 0;
182
183 /* unsupported caps */
184 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
185 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
186 case PIPE_CAP_SHADER_STENCIL_EXPORT:
187 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
188 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
189 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
190 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
191 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
192 case PIPE_CAP_FAKE_SW_MSAA:
193 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
194 case PIPE_CAP_VERTEXID_NOBASE:
195 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
196 return 0;
197
198 case PIPE_CAP_VENDOR_ID:
199 return 0x10de;
200 case PIPE_CAP_DEVICE_ID: {
201 uint64_t device_id;
202 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
203 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
204 return -1;
205 }
206 return device_id;
207 }
208 case PIPE_CAP_ACCELERATED:
209 return 1;
210 case PIPE_CAP_VIDEO_MEMORY:
211 return dev->vram_size >> 20;
212 case PIPE_CAP_UMA:
213 return 0;
214 }
215
216 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
217 return 0;
218 }
219
220 static int
221 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
222 enum pipe_shader_cap param)
223 {
224 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
225
226 switch (shader) {
227 case PIPE_SHADER_VERTEX:
228 /*
229 case PIPE_SHADER_TESSELLATION_CONTROL:
230 case PIPE_SHADER_TESSELLATION_EVALUATION:
231 */
232 case PIPE_SHADER_GEOMETRY:
233 case PIPE_SHADER_FRAGMENT:
234 break;
235 case PIPE_SHADER_COMPUTE:
236 if (class_3d != NVE4_3D_CLASS)
237 return 0;
238 break;
239 default:
240 return 0;
241 }
242
243 switch (param) {
244 case PIPE_SHADER_CAP_PREFERRED_IR:
245 return PIPE_SHADER_IR_TGSI;
246 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
247 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
248 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
249 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
250 return 16384;
251 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
252 return 16;
253 case PIPE_SHADER_CAP_MAX_INPUTS:
254 if (shader == PIPE_SHADER_VERTEX)
255 return 32;
256 /* NOTE: These only count our slots for GENERIC varyings.
257 * The address space may be larger, but the actual hard limit seems to be
258 * less than what the address space layout permits, so don't add TEXCOORD,
259 * COLOR, etc. here.
260 */
261 if (shader == PIPE_SHADER_FRAGMENT)
262 return 0x1f0 / 16;
263 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
264 * and excludes 0x60 per-patch inputs.
265 */
266 return 0x200 / 16;
267 case PIPE_SHADER_CAP_MAX_OUTPUTS:
268 return 32;
269 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
270 return 65536;
271 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
272 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
273 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
274 return NVC0_MAX_PIPE_CONSTBUFS;
275 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
276 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
277 return shader != PIPE_SHADER_FRAGMENT;
278 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
279 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
280 return 1;
281 case PIPE_SHADER_CAP_MAX_PREDS:
282 return 0;
283 case PIPE_SHADER_CAP_MAX_TEMPS:
284 return NVC0_CAP_MAX_PROGRAM_TEMPS;
285 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
286 return 1;
287 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
288 return 0;
289 case PIPE_SHADER_CAP_SUBROUTINES:
290 return 1;
291 case PIPE_SHADER_CAP_INTEGERS:
292 return 1;
293 case PIPE_SHADER_CAP_DOUBLES:
294 return 0;
295 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
296 return 0;
297 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
298 return 16; /* would be 32 in linked (OpenGL-style) mode */
299 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
300 return 16; /* XXX not sure if more are really safe */
301 default:
302 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
303 return 0;
304 }
305 }
306
307 static float
308 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
309 {
310 switch (param) {
311 case PIPE_CAPF_MAX_LINE_WIDTH:
312 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
313 return 10.0f;
314 case PIPE_CAPF_MAX_POINT_WIDTH:
315 return 63.0f;
316 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
317 return 63.375f;
318 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
319 return 16.0f;
320 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
321 return 15.0f;
322 case PIPE_CAPF_GUARD_BAND_LEFT:
323 case PIPE_CAPF_GUARD_BAND_TOP:
324 return 0.0f;
325 case PIPE_CAPF_GUARD_BAND_RIGHT:
326 case PIPE_CAPF_GUARD_BAND_BOTTOM:
327 return 0.0f; /* that or infinity */
328 }
329
330 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
331 return 0.0f;
332 }
333
334 static int
335 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
336 enum pipe_compute_cap param, void *data)
337 {
338 uint64_t *data64 = (uint64_t *)data;
339 const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
340
341 switch (param) {
342 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
343 data64[0] = 3;
344 return 8;
345 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
346 data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
347 data64[1] = 65535;
348 data64[2] = 65535;
349 return 24;
350 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
351 data64[0] = 1024;
352 data64[1] = 1024;
353 data64[2] = 64;
354 return 24;
355 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
356 data64[0] = 1024;
357 return 8;
358 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
359 data64[0] = (uint64_t)1 << 40;
360 return 8;
361 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
362 data64[0] = 48 << 10;
363 return 8;
364 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
365 data64[0] = 512 << 10;
366 return 8;
367 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
368 data64[0] = 4096;
369 return 8;
370 default:
371 return 0;
372 }
373 }
374
375 static void
376 nvc0_screen_destroy(struct pipe_screen *pscreen)
377 {
378 struct nvc0_screen *screen = nvc0_screen(pscreen);
379
380 if (!nouveau_drm_screen_unref(&screen->base))
381 return;
382
383 if (screen->base.fence.current) {
384 struct nouveau_fence *current = NULL;
385
386 /* nouveau_fence_wait will create a new current fence, so wait on the
387 * _current_ one, and remove both.
388 */
389 nouveau_fence_ref(screen->base.fence.current, &current);
390 nouveau_fence_wait(current);
391 nouveau_fence_ref(NULL, &current);
392 nouveau_fence_ref(NULL, &screen->base.fence.current);
393 }
394 if (screen->base.pushbuf)
395 screen->base.pushbuf->user_priv = NULL;
396
397 if (screen->blitter)
398 nvc0_blitter_destroy(screen);
399 if (screen->pm.prog) {
400 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
401 nvc0_program_destroy(NULL, screen->pm.prog);
402 }
403
404 nouveau_bo_ref(NULL, &screen->text);
405 nouveau_bo_ref(NULL, &screen->uniform_bo);
406 nouveau_bo_ref(NULL, &screen->tls);
407 nouveau_bo_ref(NULL, &screen->txc);
408 nouveau_bo_ref(NULL, &screen->fence.bo);
409 nouveau_bo_ref(NULL, &screen->poly_cache);
410 nouveau_bo_ref(NULL, &screen->parm);
411
412 nouveau_heap_destroy(&screen->lib_code);
413 nouveau_heap_destroy(&screen->text_heap);
414
415 FREE(screen->tic.entries);
416
417 nouveau_object_del(&screen->eng3d);
418 nouveau_object_del(&screen->eng2d);
419 nouveau_object_del(&screen->m2mf);
420 nouveau_object_del(&screen->compute);
421 nouveau_object_del(&screen->nvsw);
422
423 nouveau_screen_fini(&screen->base);
424
425 FREE(screen);
426 }
427
428 static int
429 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
430 unsigned size, const uint32_t *data)
431 {
432 struct nouveau_pushbuf *push = screen->base.pushbuf;
433
434 size /= 4;
435
436 assert((pos + size) <= 0x800);
437
438 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
439 PUSH_DATA (push, (m - 0x3800) / 8);
440 PUSH_DATA (push, pos);
441 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
442 PUSH_DATA (push, pos);
443 PUSH_DATAp(push, data, size);
444
445 return pos + size;
446 }
447
448 static void
449 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
450 {
451 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
452 PUSH_DATA (push, 0xff);
453 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
454 PUSH_DATA (push, 0xff);
455 PUSH_DATA (push, 0xff);
456 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
457 PUSH_DATA (push, 0xff);
458 PUSH_DATA (push, 0xff);
459 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
460 PUSH_DATA (push, 0x3f);
461
462 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
463 PUSH_DATA (push, (3 << 16) | 3);
464 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
465 PUSH_DATA (push, (2 << 16) | 2);
466
467 if (obj_class < GM107_3D_CLASS) {
468 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
469 PUSH_DATA (push, 0);
470 }
471 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
472 PUSH_DATA (push, 0x10);
473 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
474 PUSH_DATA (push, 0x10);
475 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
476 PUSH_DATA (push, 0x10);
477 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
478 PUSH_DATA (push, 0x10);
479 PUSH_DATA (push, 0x10);
480 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
481 PUSH_DATA (push, 0x10);
482 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
483 PUSH_DATA (push, 0xe);
484
485 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
486 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
487 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
488 PUSH_DATA (push, 0);
489 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
490 PUSH_DATA (push, 3);
491
492 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
493 PUSH_DATA (push, 0x3fffff);
494 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
495 PUSH_DATA (push, 1);
496 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
497 PUSH_DATA (push, 1);
498
499 if (obj_class < GM107_3D_CLASS) {
500 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
501 PUSH_DATA (push, 3);
502
503 if (obj_class >= NVE4_3D_CLASS) {
504 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
505 PUSH_DATA (push, 1);
506 }
507 }
508
509 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
510 * are supposed to do */
511 }
512
513 static void
514 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
515 {
516 struct nvc0_screen *screen = nvc0_screen(pscreen);
517 struct nouveau_pushbuf *push = screen->base.pushbuf;
518
519 /* we need to do it after possible flush in MARK_RING */
520 *sequence = ++screen->base.fence.sequence;
521
522 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
523 PUSH_DATAh(push, screen->fence.bo->offset);
524 PUSH_DATA (push, screen->fence.bo->offset);
525 PUSH_DATA (push, *sequence);
526 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
527 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
528 }
529
530 static u32
531 nvc0_screen_fence_update(struct pipe_screen *pscreen)
532 {
533 struct nvc0_screen *screen = nvc0_screen(pscreen);
534 return screen->fence.map[0];
535 }
536
537 static int
538 nvc0_screen_init_compute(struct nvc0_screen *screen)
539 {
540 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
541
542 switch (screen->base.device->chipset & ~0xf) {
543 case 0xc0:
544 case 0xd0:
545 /* Using COMPUTE has weird effects on 3D state, we need to
546 * investigate this further before enabling it by default.
547 */
548 if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
549 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
550 return 0;
551 case 0xe0:
552 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
553 case 0xf0:
554 case 0x100:
555 case 0x110:
556 return 0;
557 default:
558 return -1;
559 }
560 }
561
562 boolean
563 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
564 uint32_t lpos, uint32_t lneg, uint32_t cstack)
565 {
566 struct nouveau_bo *bo = NULL;
567 int ret;
568 uint64_t size = (lpos + lneg) * 32 + cstack;
569
570 if (size >= (1 << 20)) {
571 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
572 return FALSE;
573 }
574
575 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
576 size = align(size, 0x8000);
577 size *= screen->mp_count;
578
579 size = align(size, 1 << 17);
580
581 ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
582 NULL, &bo);
583 if (ret) {
584 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
585 return FALSE;
586 }
587 nouveau_bo_ref(NULL, &screen->tls);
588 screen->tls = bo;
589 return TRUE;
590 }
591
592 #define FAIL_SCREEN_INIT(str, err) \
593 do { \
594 NOUVEAU_ERR(str, err); \
595 nvc0_screen_destroy(pscreen); \
596 return NULL; \
597 } while(0)
598
599 struct pipe_screen *
600 nvc0_screen_create(struct nouveau_device *dev)
601 {
602 struct nvc0_screen *screen;
603 struct pipe_screen *pscreen;
604 struct nouveau_object *chan;
605 struct nouveau_pushbuf *push;
606 uint64_t value;
607 uint32_t obj_class;
608 int ret;
609 unsigned i;
610
611 switch (dev->chipset & ~0xf) {
612 case 0xc0:
613 case 0xd0:
614 case 0xe0:
615 case 0xf0:
616 case 0x100:
617 case 0x110:
618 break;
619 default:
620 return NULL;
621 }
622
623 screen = CALLOC_STRUCT(nvc0_screen);
624 if (!screen)
625 return NULL;
626 pscreen = &screen->base.base;
627
628 ret = nouveau_screen_init(&screen->base, dev);
629 if (ret) {
630 nvc0_screen_destroy(pscreen);
631 return NULL;
632 }
633 chan = screen->base.channel;
634 push = screen->base.pushbuf;
635 push->user_priv = screen;
636 push->rsvd_kick = 5;
637
638 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
639 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
640 PIPE_BIND_COMMAND_ARGS_BUFFER;
641 screen->base.sysmem_bindings |=
642 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
643
644 pscreen->destroy = nvc0_screen_destroy;
645 pscreen->context_create = nvc0_create;
646 pscreen->is_format_supported = nvc0_screen_is_format_supported;
647 pscreen->get_param = nvc0_screen_get_param;
648 pscreen->get_shader_param = nvc0_screen_get_shader_param;
649 pscreen->get_paramf = nvc0_screen_get_paramf;
650 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
651
652 nvc0_screen_init_resource_functions(pscreen);
653
654 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
655 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
656
657 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
658 &screen->fence.bo);
659 if (ret)
660 goto fail;
661 nouveau_bo_map(screen->fence.bo, 0, NULL);
662 screen->fence.map = screen->fence.bo->map;
663 screen->base.fence.emit = nvc0_screen_fence_emit;
664 screen->base.fence.update = nvc0_screen_fence_update;
665
666
667 ret = nouveau_object_new(chan,
668 (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
669 NULL, 0, &screen->nvsw);
670 if (ret)
671 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
672
673
674 switch (dev->chipset & ~0xf) {
675 case 0x110:
676 case 0x100:
677 case 0xf0:
678 obj_class = NVF0_P2MF_CLASS;
679 break;
680 case 0xe0:
681 obj_class = NVE4_P2MF_CLASS;
682 break;
683 default:
684 obj_class = NVC0_M2MF_CLASS;
685 break;
686 }
687 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
688 &screen->m2mf);
689 if (ret)
690 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
691
692 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
693 PUSH_DATA (push, screen->m2mf->oclass);
694 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
695 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
696 PUSH_DATA (push, 0xa0b5);
697 }
698
699 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
700 &screen->eng2d);
701 if (ret)
702 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
703
704 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
705 PUSH_DATA (push, screen->eng2d->oclass);
706 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
707 PUSH_DATA (push, 0);
708 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
709 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
710 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
711 PUSH_DATA (push, 0);
712 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
713 PUSH_DATA (push, 0);
714 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
715 PUSH_DATA (push, 0x3f);
716 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
717 PUSH_DATA (push, 1);
718 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
719 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
720
721 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
722 PUSH_DATAh(push, screen->fence.bo->offset + 16);
723 PUSH_DATA (push, screen->fence.bo->offset + 16);
724
725 switch (dev->chipset & ~0xf) {
726 case 0x110:
727 obj_class = GM107_3D_CLASS;
728 break;
729 case 0x100:
730 case 0xf0:
731 obj_class = NVF0_3D_CLASS;
732 break;
733 case 0xe0:
734 switch (dev->chipset) {
735 case 0xea:
736 obj_class = NVEA_3D_CLASS;
737 break;
738 default:
739 obj_class = NVE4_3D_CLASS;
740 break;
741 }
742 break;
743 case 0xd0:
744 obj_class = NVC8_3D_CLASS;
745 break;
746 case 0xc0:
747 default:
748 switch (dev->chipset) {
749 case 0xc8:
750 obj_class = NVC8_3D_CLASS;
751 break;
752 case 0xc1:
753 obj_class = NVC1_3D_CLASS;
754 break;
755 default:
756 obj_class = NVC0_3D_CLASS;
757 break;
758 }
759 break;
760 }
761 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
762 &screen->eng3d);
763 if (ret)
764 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
765 screen->base.class_3d = obj_class;
766
767 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
768 PUSH_DATA (push, screen->eng3d->oclass);
769
770 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
771 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
772
773 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
774 /* kill shaders after about 1 second (at 100 MHz) */
775 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
776 PUSH_DATA (push, 0x17);
777 }
778
779 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
780 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
781 for (i = 0; i < 8; ++i)
782 PUSH_DATA(push, dev->drm_version >= 0x01000101);
783
784 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
785 PUSH_DATA (push, 1);
786
787 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
788 PUSH_DATA (push, 0);
789 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
790 PUSH_DATA (push, 0);
791 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
792 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
793 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
794 PUSH_DATA (push, 0);
795 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
796 PUSH_DATA (push, 1);
797 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
798 PUSH_DATA (push, 1);
799 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
800 PUSH_DATA (push, 1);
801 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
802 PUSH_DATA (push, 0);
803 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
804 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
805 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
806 } else {
807 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
808 PUSH_DATA (push, 15);
809 }
810 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
811 PUSH_DATA (push, 8); /* 128 */
812 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
813 PUSH_DATA (push, 1);
814 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
815 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
816 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
817 }
818
819 nvc0_magic_3d_init(push, screen->eng3d->oclass);
820
821 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
822 &screen->text);
823 if (ret)
824 goto fail;
825
826 /* XXX: getting a page fault at the end of the code buffer every few
827 * launches, don't use the last 256 bytes to work around them - prefetch ?
828 */
829 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
830
831 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
832 &screen->uniform_bo);
833 if (ret)
834 goto fail;
835
836 PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
837
838 for (i = 0; i < 5; ++i) {
839 /* TIC and TSC entries for each unit (nve4+ only) */
840 /* auxiliary constants (6 user clip planes, base instance id) */
841 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
842 PUSH_DATA (push, 512);
843 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
844 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
845 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
846 PUSH_DATA (push, (15 << 4) | 1);
847 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
848 unsigned j;
849 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
850 PUSH_DATA (push, 0);
851 for (j = 0; j < 8; ++j)
852 PUSH_DATA(push, j);
853 } else {
854 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
855 PUSH_DATA (push, 0x54);
856 }
857 }
858 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
859 PUSH_DATA (push, 0);
860
861 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
862 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
863 PUSH_DATA (push, 256);
864 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
865 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
866 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
867 PUSH_DATA (push, 0);
868 PUSH_DATAf(push, 0.0f);
869 PUSH_DATAf(push, 0.0f);
870 PUSH_DATAf(push, 0.0f);
871 PUSH_DATAf(push, 0.0f);
872 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
873 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
874 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
875
876 if (dev->drm_version >= 0x01000101) {
877 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
878 if (ret) {
879 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
880 goto fail;
881 }
882 } else {
883 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
884 value = (8 << 8) | 4;
885 else
886 value = (16 << 8) | 4;
887 }
888 screen->mp_count = value >> 8;
889 screen->mp_count_compute = screen->mp_count;
890
891 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
892
893 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
894 PUSH_DATAh(push, screen->text->offset);
895 PUSH_DATA (push, screen->text->offset);
896 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
897 PUSH_DATAh(push, screen->tls->offset);
898 PUSH_DATA (push, screen->tls->offset);
899 PUSH_DATA (push, screen->tls->size >> 32);
900 PUSH_DATA (push, screen->tls->size);
901 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
902 PUSH_DATA (push, 0);
903 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
904 PUSH_DATA (push, 0);
905
906 if (screen->eng3d->oclass < GM107_3D_CLASS) {
907 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
908 &screen->poly_cache);
909 if (ret)
910 goto fail;
911
912 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
913 PUSH_DATAh(push, screen->poly_cache->offset);
914 PUSH_DATA (push, screen->poly_cache->offset);
915 PUSH_DATA (push, 3);
916 }
917
918 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
919 &screen->txc);
920 if (ret)
921 goto fail;
922
923 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
924 PUSH_DATAh(push, screen->txc->offset);
925 PUSH_DATA (push, screen->txc->offset);
926 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
927
928 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
929 PUSH_DATAh(push, screen->txc->offset + 65536);
930 PUSH_DATA (push, screen->txc->offset + 65536);
931 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
932
933 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
934 PUSH_DATA (push, 0);
935 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
936 PUSH_DATA (push, 0);
937 PUSH_DATA (push, 0);
938 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
939 PUSH_DATA (push, 0x3f);
940
941 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
942 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
943 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
944 for (i = 0; i < 8 * 2; ++i)
945 PUSH_DATA(push, 0);
946 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
947 PUSH_DATA (push, 0);
948 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
949 PUSH_DATA (push, 0);
950
951 /* neither scissors, viewport nor stencil mask should affect clears */
952 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
953 PUSH_DATA (push, 0);
954
955 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
956 PUSH_DATA (push, 1);
957 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
958 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
959 PUSH_DATAf(push, 0.0f);
960 PUSH_DATAf(push, 1.0f);
961 }
962 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
963 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
964
965 /* We use scissors instead of exact view volume clipping,
966 * so they're always enabled.
967 */
968 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
969 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
970 PUSH_DATA (push, 1);
971 PUSH_DATA (push, 8192 << 16);
972 PUSH_DATA (push, 8192 << 16);
973 }
974
975 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
976
977 i = 0;
978 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
979 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
980 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
981 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
982 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
983 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
984 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
985 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
986 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
987
988 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
989 PUSH_DATA (push, 1);
990 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
991 PUSH_DATA (push, 1);
992 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
993 PUSH_DATA (push, 0x40);
994 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
995 PUSH_DATA (push, 0);
996 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
997 PUSH_DATA (push, 0x30);
998 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
999 PUSH_DATA (push, 3);
1000 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1001 PUSH_DATA (push, 0x20);
1002 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1003 PUSH_DATA (push, 0x00);
1004
1005 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1006 PUSH_DATA (push, 0);
1007 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1008 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1009
1010 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1011
1012 if (nvc0_screen_init_compute(screen))
1013 goto fail;
1014
1015 PUSH_KICK (push);
1016
1017 screen->tic.entries = CALLOC(4096, sizeof(void *));
1018 screen->tsc.entries = screen->tic.entries + 2048;
1019
1020 if (!nvc0_blitter_create(screen))
1021 goto fail;
1022
1023 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
1024
1025 return pscreen;
1026
1027 fail:
1028 nvc0_screen_destroy(pscreen);
1029 return NULL;
1030 }
1031
1032 int
1033 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1034 {
1035 int i = screen->tic.next;
1036
1037 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1038 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1039
1040 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1041
1042 if (screen->tic.entries[i])
1043 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1044
1045 screen->tic.entries[i] = entry;
1046 return i;
1047 }
1048
1049 int
1050 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1051 {
1052 int i = screen->tsc.next;
1053
1054 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1055 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1056
1057 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1058
1059 if (screen->tsc.entries[i])
1060 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1061
1062 screen->tsc.entries[i] = entry;
1063 return i;
1064 }