src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30 #include "compiler/nir/nir.h"
  31
  32 #include "nouveau_vp3_video.h"
  33
  34 #include "nvc0/nvc0_context.h"
  35 #include "nvc0/nvc0_screen.h"
  36
  37 #include "nvc0/mme/com9097.mme.h"
  38 #include "nvc0/mme/com90c0.mme.h"
  39
  40 #include "nv50/g80_texture.xml.h"
  41
  42 static bool
  43 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  44                                 enum pipe_format format,
  45                                 enum pipe_texture_target target,
  46                                 unsigned sample_count,
  47                                 unsigned storage_sample_count,
  48                                 unsigned bindings)
  49 {
  50    const struct util_format_description *desc = util_format_description(format);
  51
  52    if (sample_count > 8)
  53       return false;
  54    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  55       return false;
  56
  57    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  58       return false;
  59
  60    /* Short-circuit the rest of the logic -- this is used by the state tracker
  61     * to determine valid MS levels in a no-attachments scenario.
  62     */
  63    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  64       return true;
  65
  66    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  67       if (util_format_get_blocksizebits(format) == 3 * 32)
  68          return false;
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  79     */
  80    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  81         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  82        /* The claim is that this should work on GM107 but it doesn't. Need to
  83         * test further and figure out if it's a nouveau issue or a HW one.
  84        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  85         */
  86        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  87       return false;
  88
  89    /* shared is always supported */
  90    bindings &= ~(PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  94       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  95           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
  96          /* This should work on Fermi, but for currently unknown reasons it
  97           * does not and results in breaking reads from pbos. */
  98          return false;
  99       }
 100    }
 101
 102    return (( nvc0_format_table[format].usage |
 103             nvc0_vertex_format[format].usage) & bindings) == bindings;
 104 }
 105
 106 static int
 107 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 108 {
 109    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 110    const struct nouveau_screen *screen = nouveau_screen(pscreen);
 111    struct nouveau_device *dev = screen->device;
 112
 113    switch (param) {
 114    /* non-boolean caps */
 115    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 116       return 16384;
 117    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 118       return 15;
 119    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 120       return 12;
 121    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 122       return 2048;
 123    case PIPE_CAP_MIN_TEXEL_OFFSET:
 124       return -8;
 125    case PIPE_CAP_MAX_TEXEL_OFFSET:
 126       return 7;
 127    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 128       return -32;
 129    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 130       return 31;
 131    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 132       return 128 * 1024 * 1024;
 133    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 134       return 430;
 135    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 136       return 430;
 137    case PIPE_CAP_MAX_RENDER_TARGETS:
 138       return 8;
 139    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 140       return 1;
 141    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 142    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 143       return 8;
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 145       return 4;
 146    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 147    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 148       return 128;
 149    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 150    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 151       return 1024;
 152    case PIPE_CAP_MAX_VERTEX_STREAMS:
 153       return 4;
 154    case PIPE_CAP_MAX_GS_INVOCATIONS:
 155       return 32;
 156    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 157       return 1 << 27;
 158    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 159       return 2048;
 160    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 161       return 2047;
 162    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 163       return 256;
 164    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 165       if (class_3d < GM107_3D_CLASS)
 166          return 256; /* IMAGE bindings require alignment to 256 */
 167       return 16;
 168    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 169       return 16;
 170    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 171       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 172    case PIPE_CAP_MAX_VIEWPORTS:
 173       return NVC0_MAX_VIEWPORTS;
 174    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 175       return 4;
 176    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 177       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 178    case PIPE_CAP_ENDIANNESS:
 179       return PIPE_ENDIAN_LITTLE;
 180    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 181       return 30;
 182    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 183       return NVC0_MAX_WINDOW_RECTANGLES;
 184    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 185       return class_3d >= GM200_3D_CLASS ? 8 : 0;
 186    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 187       return 64 * 1024 * 1024;
 188    case PIPE_CAP_MAX_VARYINGS:
 189       /* NOTE: These only count our slots for GENERIC varyings.
 190        * The address space may be larger, but the actual hard limit seems to be
 191        * less than what the address space layout permits, so don't add TEXCOORD,
 192        * COLOR, etc. here.
 193        */
 194       return 0x1f0 / 16;
 195
 196    /* supported caps */
 197    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 198    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 199    case PIPE_CAP_TEXTURE_SWIZZLE:
 200    case PIPE_CAP_NPOT_TEXTURES:
 201    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 202    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 203    case PIPE_CAP_ANISOTROPIC_FILTER:
 204    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 205    case PIPE_CAP_CUBE_MAP_ARRAY:
 206    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 207    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 208    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 209    case PIPE_CAP_POINT_SPRITE:
 210    case PIPE_CAP_TGSI_TEXCOORD:
 211    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 212    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 213    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 214    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 215    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 216    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 217    case PIPE_CAP_QUERY_TIMESTAMP:
 218    case PIPE_CAP_QUERY_TIME_ELAPSED:
 219    case PIPE_CAP_OCCLUSION_QUERY:
 220    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 221    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 222    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 223    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 224    case PIPE_CAP_INDEP_BLEND_ENABLE:
 225    case PIPE_CAP_INDEP_BLEND_FUNC:
 226    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 227    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 228    case PIPE_CAP_PRIMITIVE_RESTART:
 229    case PIPE_CAP_TGSI_INSTANCEID:
 230    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 231    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 232    case PIPE_CAP_CONDITIONAL_RENDER:
 233    case PIPE_CAP_TEXTURE_BARRIER:
 234    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 235    case PIPE_CAP_START_INSTANCE:
 236    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 237    case PIPE_CAP_DRAW_INDIRECT:
 238    case PIPE_CAP_USER_VERTEX_BUFFERS:
 239    case PIPE_CAP_TEXTURE_QUERY_LOD:
 240    case PIPE_CAP_SAMPLE_SHADING:
 241    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 242    case PIPE_CAP_TEXTURE_GATHER_SM5:
 243    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 244    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 245    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 246    case PIPE_CAP_CLIP_HALFZ:
 247    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 248    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 249    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 250    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 251    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 252    case PIPE_CAP_TGSI_TXQS:
 253    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 254    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 255    case PIPE_CAP_SHAREABLE_SHADERS:
 256    case PIPE_CAP_CLEAR_TEXTURE:
 257    case PIPE_CAP_DRAW_PARAMETERS:
 258    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 259    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 260    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 261    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 262    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 263    case PIPE_CAP_INVALIDATE_BUFFER:
 264    case PIPE_CAP_STRING_MARKER:
 265    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 266    case PIPE_CAP_CULL_DISTANCE:
 267    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 268    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 269    case PIPE_CAP_TGSI_VOTE:
 270    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 271    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 272    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 273    case PIPE_CAP_DOUBLES:
 274    case PIPE_CAP_INT64:
 275    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 276    case PIPE_CAP_TGSI_CLOCK:
 277    case PIPE_CAP_COMPUTE:
 278    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 279    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 280    case PIPE_CAP_QUERY_SO_OVERFLOW:
 281    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 282    case PIPE_CAP_TGSI_DIV:
 283       return 1;
 284    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 285       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 286    case PIPE_CAP_FBFETCH:
 287       return class_3d >= NVE4_3D_CLASS ? 1 : 0; /* needs testing on fermi */
 288    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 289    case PIPE_CAP_TGSI_BALLOT:
 290       return class_3d >= NVE4_3D_CLASS;
 291    case PIPE_CAP_BINDLESS_TEXTURE:
 292       return class_3d >= NVE4_3D_CLASS;
 293    case PIPE_CAP_TGSI_ATOMFADD:
 294       return class_3d < GM107_3D_CLASS; /* needs additional lowering */
 295    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 296    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 297    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 298    case PIPE_CAP_POST_DEPTH_COVERAGE:
 299    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 300    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 301    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 302    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 303       return class_3d >= GM200_3D_CLASS;
 304    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 305       return class_3d >= GP100_3D_CLASS;
 306
 307    /* caps has to be turned on with nir */
 308    case PIPE_CAP_INT64_DIVMOD:
 309       return screen->prefer_nir ? 1 : 0;
 310
 311    /* unsupported caps */
 312    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 313    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 314    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 315    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 316    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 317    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 318    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 319    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 320    case PIPE_CAP_FAKE_SW_MSAA:
 321    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 322    case PIPE_CAP_VERTEXID_NOBASE:
 323    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 324    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 325    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 326    case PIPE_CAP_GENERATE_MIPMAP:
 327    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 328    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 329    case PIPE_CAP_QUERY_MEMORY_INFO:
 330    case PIPE_CAP_PCI_GROUP:
 331    case PIPE_CAP_PCI_BUS:
 332    case PIPE_CAP_PCI_DEVICE:
 333    case PIPE_CAP_PCI_FUNCTION:
 334    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 335    case PIPE_CAP_NATIVE_FENCE_FD:
 336    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 337    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 338    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 339    case PIPE_CAP_MEMOBJ:
 340    case PIPE_CAP_LOAD_CONSTBUF:
 341    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 342    case PIPE_CAP_TILE_RASTER_ORDER:
 343    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 344    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 345    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 346    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 347    case PIPE_CAP_FENCE_SIGNAL:
 348    case PIPE_CAP_CONSTBUF0_FLAGS:
 349    case PIPE_CAP_PACKED_UNIFORMS:
 350    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 351    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 352    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 353    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 354    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 355    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 356    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 357    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 358    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 359    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 360    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 361    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 362    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 363    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 364    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 365    case PIPE_CAP_FBFETCH_COHERENT:
 366    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
 367    case PIPE_CAP_TGSI_ATOMINC_WRAP:
 368       return 0;
 369
 370    case PIPE_CAP_VENDOR_ID:
 371       return 0x10de;
 372    case PIPE_CAP_DEVICE_ID: {
 373       uint64_t device_id;
 374       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 375          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 376          return -1;
 377       }
 378       return device_id;
 379    }
 380    case PIPE_CAP_ACCELERATED:
 381       return 1;
 382    case PIPE_CAP_VIDEO_MEMORY:
 383       return dev->vram_size >> 20;
 384    case PIPE_CAP_UMA:
 385       return 0;
 386
 387    default:
 388       debug_printf("%s: unhandled cap %d\n", __func__, param);
 389       /* fallthrough */
 390    /* caps where we want the default value */
 391    case PIPE_CAP_DMABUF:
 392    case PIPE_CAP_ESSL_FEATURE_LEVEL:
 393    case PIPE_CAP_MAX_FRAMES_IN_FLIGHT:
 394       return u_pipe_screen_get_param_defaults(pscreen, param);
 395    }
 396 }
 397
 398 static int
 399 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 400                              enum pipe_shader_type shader,
 401                              enum pipe_shader_cap param)
 402 {
 403    const struct nouveau_screen *screen = nouveau_screen(pscreen);
 404    const uint16_t class_3d = screen->class_3d;
 405
 406    switch (shader) {
 407    case PIPE_SHADER_VERTEX:
 408    case PIPE_SHADER_GEOMETRY:
 409    case PIPE_SHADER_FRAGMENT:
 410    case PIPE_SHADER_COMPUTE:
 411    case PIPE_SHADER_TESS_CTRL:
 412    case PIPE_SHADER_TESS_EVAL:
 413       break;
 414    default:
 415       return 0;
 416    }
 417
 418    switch (param) {
 419    case PIPE_SHADER_CAP_PREFERRED_IR:
 420       return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
 421    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 422       return 1 << PIPE_SHADER_IR_TGSI |
 423              1 << PIPE_SHADER_IR_NIR;
 424    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 425    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 426    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 427    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 428       return 16384;
 429    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 430       return 16;
 431    case PIPE_SHADER_CAP_MAX_INPUTS:
 432       return 0x200 / 16;
 433    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 434       return 32;
 435    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 436       return NVC0_MAX_CONSTBUF_SIZE;
 437    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 438       return NVC0_MAX_PIPE_CONSTBUFS;
 439    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 440       return shader != PIPE_SHADER_FRAGMENT;
 441    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 442    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 443    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 444       return 1;
 445    case PIPE_SHADER_CAP_MAX_TEMPS:
 446       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 447    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 448       return 1;
 449    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 450       return 1;
 451    case PIPE_SHADER_CAP_SUBROUTINES:
 452       return 1;
 453    case PIPE_SHADER_CAP_INTEGERS:
 454       return 1;
 455    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 456       return 1;
 457    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 458       return 1;
 459    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 460       return 1;
 461    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 462    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 463    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 464    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 465    case PIPE_SHADER_CAP_INT64_ATOMICS:
 466    case PIPE_SHADER_CAP_FP16:
 467    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 468    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 469       return 0;
 470    case PIPE_SHADER_CAP_SCALAR_ISA:
 471       return 1;
 472    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 473       return NVC0_MAX_BUFFERS;
 474    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 475       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 476    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 477       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 478    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 479       return 32;
 480    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 481       if (class_3d >= NVE4_3D_CLASS)
 482          return NVC0_MAX_IMAGES;
 483       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 484          return NVC0_MAX_IMAGES;
 485       return 0;
 486    default:
 487       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 488       return 0;
 489    }
 490 }
 491
 492 static float
 493 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 494 {
 495    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 496
 497    switch (param) {
 498    case PIPE_CAPF_MAX_LINE_WIDTH:
 499    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 500       return 10.0f;
 501    case PIPE_CAPF_MAX_POINT_WIDTH:
 502       return 63.0f;
 503    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 504       return 63.375f;
 505    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 506       return 16.0f;
 507    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 508       return 15.0f;
 509    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 510       return 0.0f;
 511    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 512       return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
 513    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 514       return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
 515    }
 516
 517    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 518    return 0.0f;
 519 }
 520
 521 static int
 522 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 523                               enum pipe_shader_ir ir_type,
 524                               enum pipe_compute_cap param, void *data)
 525 {
 526    struct nvc0_screen *screen = nvc0_screen(pscreen);
 527    const uint16_t obj_class = screen->compute->oclass;
 528
 529 #define RET(x) do {                  \
 530    if (data)                         \
 531       memcpy(data, x, sizeof(x));    \
 532    return sizeof(x);                 \
 533 } while (0)
 534
 535    switch (param) {
 536    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 537       RET((uint64_t []) { 3 });
 538    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 539       if (obj_class >= NVE4_COMPUTE_CLASS) {
 540          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 541       } else {
 542          RET(((uint64_t []) { 65535, 65535, 65535 }));
 543       }
 544    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 545       RET(((uint64_t []) { 1024, 1024, 64 }));
 546    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 547       RET((uint64_t []) { 1024 });
 548    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 549       if (obj_class >= NVE4_COMPUTE_CLASS) {
 550          RET((uint64_t []) { 1024 });
 551       } else {
 552          RET((uint64_t []) { 512 });
 553       }
 554    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 555       RET((uint64_t []) { 1ULL << 40 });
 556    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 557       switch (obj_class) {
 558       case GM200_COMPUTE_CLASS:
 559          RET((uint64_t []) { 96 << 10 });
 560          break;
 561       case GM107_COMPUTE_CLASS:
 562          RET((uint64_t []) { 64 << 10 });
 563          break;
 564       default:
 565          RET((uint64_t []) { 48 << 10 });
 566          break;
 567       }
 568    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 569       RET((uint64_t []) { 512 << 10 });
 570    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 571       RET((uint64_t []) { 4096 });
 572    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 573       RET((uint32_t []) { 32 });
 574    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 575       RET((uint64_t []) { 1ULL << 40 });
 576    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 577       RET((uint32_t []) { 0 });
 578    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 579       RET((uint32_t []) { screen->mp_count_compute });
 580    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 581       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 582    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 583       RET((uint32_t []) { 64 });
 584    default:
 585       return 0;
 586    }
 587
 588 #undef RET
 589 }
 590
 591 static void
 592 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
 593                                   unsigned sample_count,
 594                                   unsigned *width, unsigned *height)
 595 {
 596    switch (sample_count) {
 597    case 0:
 598    case 1:
 599       /* this could be 4x4, but the GL state tracker makes it difficult to
 600        * create a 1x MSAA texture and smaller grids save CB space */
 601       *width = 2;
 602       *height = 4;
 603       break;
 604    case 2:
 605       *width = 2;
 606       *height = 4;
 607       break;
 608    case 4:
 609       *width = 2;
 610       *height = 2;
 611       break;
 612    case 8:
 613       *width = 1;
 614       *height = 2;
 615       break;
 616    default:
 617       assert(0);
 618    }
 619 }
 620
 621 static void
 622 nvc0_screen_destroy(struct pipe_screen *pscreen)
 623 {
 624    struct nvc0_screen *screen = nvc0_screen(pscreen);
 625
 626    if (!nouveau_drm_screen_unref(&screen->base))
 627       return;
 628
 629    if (screen->base.fence.current) {
 630       struct nouveau_fence *current = NULL;
 631
 632       /* nouveau_fence_wait will create a new current fence, so wait on the
 633        * _current_ one, and remove both.
 634        */
 635       nouveau_fence_ref(screen->base.fence.current, &current);
 636       nouveau_fence_wait(current, NULL);
 637       nouveau_fence_ref(NULL, &current);
 638       nouveau_fence_ref(NULL, &screen->base.fence.current);
 639    }
 640    if (screen->base.pushbuf)
 641       screen->base.pushbuf->user_priv = NULL;
 642
 643    if (screen->blitter)
 644       nvc0_blitter_destroy(screen);
 645    if (screen->pm.prog) {
 646       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 647       nvc0_program_destroy(NULL, screen->pm.prog);
 648       FREE(screen->pm.prog);
 649    }
 650
 651    nouveau_bo_ref(NULL, &screen->text);
 652    nouveau_bo_ref(NULL, &screen->uniform_bo);
 653    nouveau_bo_ref(NULL, &screen->tls);
 654    nouveau_bo_ref(NULL, &screen->txc);
 655    nouveau_bo_ref(NULL, &screen->fence.bo);
 656    nouveau_bo_ref(NULL, &screen->poly_cache);
 657
 658    nouveau_heap_destroy(&screen->lib_code);
 659    nouveau_heap_destroy(&screen->text_heap);
 660
 661    FREE(screen->tic.entries);
 662
 663    nouveau_object_del(&screen->eng3d);
 664    nouveau_object_del(&screen->eng2d);
 665    nouveau_object_del(&screen->m2mf);
 666    nouveau_object_del(&screen->compute);
 667    nouveau_object_del(&screen->nvsw);
 668
 669    nouveau_screen_fini(&screen->base);
 670
 671    FREE(screen);
 672 }
 673
 674 static int
 675 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 676                      unsigned size, const uint32_t *data)
 677 {
 678    struct nouveau_pushbuf *push = screen->base.pushbuf;
 679
 680    size /= 4;
 681
 682    assert((pos + size) <= 0x800);
 683
 684    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 685    PUSH_DATA (push, (m - 0x3800) / 8);
 686    PUSH_DATA (push, pos);
 687    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 688    PUSH_DATA (push, pos);
 689    PUSH_DATAp(push, data, size);
 690
 691    return pos + size;
 692 }
 693
 694 static void
 695 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 696 {
 697    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 698    PUSH_DATA (push, 0xff);
 699    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 700    PUSH_DATA (push, 0xff);
 701    PUSH_DATA (push, 0xff);
 702    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 703    PUSH_DATA (push, 0xff);
 704    PUSH_DATA (push, 0xff);
 705    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 706    PUSH_DATA (push, 0x3f);
 707
 708    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 709    PUSH_DATA (push, (3 << 16) | 3);
 710    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 711    PUSH_DATA (push, (2 << 16) | 2);
 712
 713    if (obj_class < GM107_3D_CLASS) {
 714       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 715       PUSH_DATA (push, 0);
 716    }
 717    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 718    PUSH_DATA (push, 0x10);
 719    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 720    PUSH_DATA (push, 0x10);
 721    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 722    PUSH_DATA (push, 0x10);
 723    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 724    PUSH_DATA (push, 0x10);
 725    PUSH_DATA (push, 0x10);
 726    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 727    PUSH_DATA (push, 0x10);
 728    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 729    PUSH_DATA (push, 0xe);
 730
 731    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 732    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 733    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 734    PUSH_DATA (push, 0);
 735    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 736    PUSH_DATA (push, 3);
 737
 738    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 739    PUSH_DATA (push, 0x3fffff);
 740    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 741    PUSH_DATA (push, 1);
 742    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 743    PUSH_DATA (push, 1);
 744
 745    if (obj_class < GM107_3D_CLASS) {
 746       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 747       PUSH_DATA (push, 3);
 748
 749       if (obj_class >= NVE4_3D_CLASS) {
 750          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 751          PUSH_DATA (push, 1);
 752       }
 753    }
 754
 755    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 756     * are supposed to do */
 757 }
 758
 759 static void
 760 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 761 {
 762    struct nvc0_screen *screen = nvc0_screen(pscreen);
 763    struct nouveau_pushbuf *push = screen->base.pushbuf;
 764
 765    /* we need to do it after possible flush in MARK_RING */
 766    *sequence = ++screen->base.fence.sequence;
 767
 768    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 769    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 770    PUSH_DATAh(push, screen->fence.bo->offset);
 771    PUSH_DATA (push, screen->fence.bo->offset);
 772    PUSH_DATA (push, *sequence);
 773    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 774               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 775 }
 776
 777 static u32
 778 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 779 {
 780    struct nvc0_screen *screen = nvc0_screen(pscreen);
 781    return screen->fence.map[0];
 782 }
 783
 784 static int
 785 nvc0_screen_init_compute(struct nvc0_screen *screen)
 786 {
 787    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 788
 789    switch (screen->base.device->chipset & ~0xf) {
 790    case 0xc0:
 791    case 0xd0:
 792       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 793    case 0xe0:
 794    case 0xf0:
 795    case 0x100:
 796    case 0x110:
 797    case 0x120:
 798    case 0x130:
 799       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 800    default:
 801       return -1;
 802    }
 803 }
 804
 805 static int
 806 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 807                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 808 {
 809    struct nouveau_bo *bo = NULL;
 810    int ret;
 811    uint64_t size = (lpos + lneg) * 32 + cstack;
 812
 813    if (size >= (1 << 20)) {
 814       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 815       return -1;
 816    }
 817
 818    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 819    size  = align(size, 0x8000);
 820    size *= screen->mp_count;
 821
 822    size = align(size, 1 << 17);
 823
 824    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 825                         NULL, &bo);
 826    if (ret)
 827       return ret;
 828
 829    /* Make sure that the pushbuf has acquired a reference to the old tls
 830     * segment, as it may have commands that will reference it.
 831     */
 832    if (screen->tls)
 833       PUSH_REFN(screen->base.pushbuf, screen->tls,
 834                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
 835    nouveau_bo_ref(NULL, &screen->tls);
 836    screen->tls = bo;
 837    return 0;
 838 }
 839
 840 int
 841 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 842 {
 843    struct nouveau_pushbuf *push = screen->base.pushbuf;
 844    struct nouveau_bo *bo;
 845    int ret;
 846
 847    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 848                         1 << 17, size, NULL, &bo);
 849    if (ret)
 850       return ret;
 851
 852    /* Make sure that the pushbuf has acquired a reference to the old text
 853     * segment, as it may have commands that will reference it.
 854     */
 855    if (screen->text)
 856       PUSH_REFN(push, screen->text,
 857                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
 858    nouveau_bo_ref(NULL, &screen->text);
 859    screen->text = bo;
 860
 861    nouveau_heap_destroy(&screen->lib_code);
 862    nouveau_heap_destroy(&screen->text_heap);
 863
 864    /* XXX: getting a page fault at the end of the code buffer every few
 865     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 866     */
 867    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 868
 869    /* update the code segment setup */
 870    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 871    PUSH_DATAh(push, screen->text->offset);
 872    PUSH_DATA (push, screen->text->offset);
 873    if (screen->compute) {
 874       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 875       PUSH_DATAh(push, screen->text->offset);
 876       PUSH_DATA (push, screen->text->offset);
 877    }
 878
 879    return 0;
 880 }
 881
 882 void
 883 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
 884                        int stage, int index, int size, uint64_t addr)
 885 {
 886    assert(stage != 5);
 887
 888    struct nouveau_pushbuf *push = screen->base.pushbuf;
 889
 890    if (screen->base.class_3d >= GM107_3D_CLASS) {
 891       struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
 892
 893       // TODO: Better figure out the conditions in which this is needed
 894       bool serialize = binding->addr == addr && binding->size != size;
 895       if (can_serialize)
 896          serialize = serialize && *can_serialize;
 897       if (serialize) {
 898          IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 899          if (can_serialize)
 900             *can_serialize = false;
 901       }
 902
 903       binding->addr = addr;
 904       binding->size = size;
 905    }
 906
 907    if (size >= 0) {
 908       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 909       PUSH_DATA (push, size);
 910       PUSH_DATAh(push, addr);
 911       PUSH_DATA (push, addr);
 912    }
 913    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
 914 }
 915
 916 static const nir_shader_compiler_options nir_options = {
 917    .lower_fdiv = false,
 918    .lower_ffma = false,
 919    .fuse_ffma = false, /* nir doesn't track mad vs fma */
 920    .lower_flrp32 = true,
 921    .lower_flrp64 = true,
 922    .lower_fpow = false,
 923    .lower_fsat = false,
 924    .lower_fsqrt = false, // TODO: only before gm200
 925    .lower_fmod = true,
 926    .lower_bitfield_extract = false,
 927    .lower_bitfield_extract_to_shifts = false,
 928    .lower_bitfield_insert = false,
 929    .lower_bitfield_insert_to_shifts = false,
 930    .lower_bitfield_reverse = false,
 931    .lower_bit_count = false,
 932    .lower_ifind_msb = false,
 933    .lower_find_lsb = false,
 934    .lower_uadd_carry = true, // TODO
 935    .lower_usub_borrow = true, // TODO
 936    .lower_mul_high = false,
 937    .lower_negate = false,
 938    .lower_sub = false, // TODO
 939    .lower_scmp = true, // TODO: not implemented yet
 940    .lower_idiv = true,
 941    .lower_isign = false, // TODO
 942    .fdot_replicates = false, // TODO
 943    .lower_ffloor = false, // TODO
 944    .lower_ffract = true,
 945    .lower_fceil = false, // TODO
 946    .lower_ldexp = true,
 947    .lower_pack_half_2x16 = true,
 948    .lower_pack_unorm_2x16 = true,
 949    .lower_pack_snorm_2x16 = true,
 950    .lower_pack_unorm_4x8 = true,
 951    .lower_pack_snorm_4x8 = true,
 952    .lower_unpack_half_2x16 = true,
 953    .lower_unpack_unorm_2x16 = true,
 954    .lower_unpack_snorm_2x16 = true,
 955    .lower_unpack_unorm_4x8 = true,
 956    .lower_unpack_snorm_4x8 = true,
 957    .lower_extract_byte = true,
 958    .lower_extract_word = true,
 959    .lower_all_io_to_temps = false,
 960    .vertex_id_zero_based = false,
 961    .lower_base_vertex = false,
 962    .lower_helper_invocation = false,
 963    .lower_cs_local_index_from_id = true,
 964    .lower_cs_local_id_from_index = false,
 965    .lower_device_index_to_zero = false, // TODO
 966    .lower_wpos_pntc = false, // TODO
 967    .lower_hadd = true, // TODO
 968    .lower_add_sat = true, // TODO
 969    .use_interpolated_input_intrinsics = true,
 970    .lower_mul_2x32_64 = true, // TODO
 971    .max_unroll_iterations = 32,
 972    .lower_int64_options = nir_lower_divmod64, // TODO
 973    .lower_doubles_options = nir_lower_dmod, // TODO
 974 };
 975
 976 static const void *
 977 nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
 978                                  enum pipe_shader_ir ir,
 979                                  enum pipe_shader_type shader)
 980 {
 981    if (ir == PIPE_SHADER_IR_NIR)
 982       return &nir_options;
 983    return NULL;
 984 }
 985
 986 #define FAIL_SCREEN_INIT(str, err)                    \
 987    do {                                               \
 988       NOUVEAU_ERR(str, err);                          \
 989       goto fail;                                      \
 990    } while(0)
 991
 992 struct nouveau_screen *
 993 nvc0_screen_create(struct nouveau_device *dev)
 994 {
 995    struct nvc0_screen *screen;
 996    struct pipe_screen *pscreen;
 997    struct nouveau_object *chan;
 998    struct nouveau_pushbuf *push;
 999    uint64_t value;
1000    uint32_t obj_class;
1001    uint32_t flags;
1002    int ret;
1003    unsigned i;
1004
1005    switch (dev->chipset & ~0xf) {
1006    case 0xc0:
1007    case 0xd0:
1008    case 0xe0:
1009    case 0xf0:
1010    case 0x100:
1011    case 0x110:
1012    case 0x120:
1013    case 0x130:
1014       break;
1015    default:
1016       return NULL;
1017    }
1018
1019    screen = CALLOC_STRUCT(nvc0_screen);
1020    if (!screen)
1021       return NULL;
1022    pscreen = &screen->base.base;
1023    pscreen->destroy = nvc0_screen_destroy;
1024
1025    ret = nouveau_screen_init(&screen->base, dev);
1026    if (ret)
1027       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
1028    chan = screen->base.channel;
1029    push = screen->base.pushbuf;
1030    push->user_priv = screen;
1031    push->rsvd_kick = 5;
1032
1033    /* TODO: could this be higher on Kepler+? how does reclocking vs no
1034     * reclocking affect performance?
1035     * TODO: could this be higher on Fermi?
1036     */
1037    if (dev->chipset >= 0xe0)
1038       screen->base.transfer_pushbuf_threshold = 1024;
1039
1040    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
1041       PIPE_BIND_SHADER_BUFFER |
1042       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
1043       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
1044    screen->base.sysmem_bindings |=
1045       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
1046
1047    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
1048       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
1049       screen->base.vidmem_bindings = 0;
1050    }
1051
1052    pscreen->context_create = nvc0_create;
1053    pscreen->is_format_supported = nvc0_screen_is_format_supported;
1054    pscreen->get_param = nvc0_screen_get_param;
1055    pscreen->get_shader_param = nvc0_screen_get_shader_param;
1056    pscreen->get_paramf = nvc0_screen_get_paramf;
1057    pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
1058    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
1059    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
1060    /* nir stuff */
1061    pscreen->get_compiler_options = nvc0_screen_get_compiler_options;
1062
1063    nvc0_screen_init_resource_functions(pscreen);
1064
1065    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1066    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1067
1068    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
1069    if (screen->base.drm->version >= 0x01000202)
1070       flags |= NOUVEAU_BO_COHERENT;
1071
1072    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
1073    if (ret)
1074       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
1075    nouveau_bo_map(screen->fence.bo, 0, NULL);
1076    screen->fence.map = screen->fence.bo->map;
1077    screen->base.fence.emit = nvc0_screen_fence_emit;
1078    screen->base.fence.update = nvc0_screen_fence_update;
1079
1080
1081    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
1082                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
1083    if (ret)
1084       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
1085
1086    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
1087    PUSH_DATA (push, screen->nvsw->handle);
1088
1089    switch (dev->chipset & ~0xf) {
1090    case 0x130:
1091    case 0x120:
1092    case 0x110:
1093    case 0x100:
1094    case 0xf0:
1095       obj_class = NVF0_P2MF_CLASS;
1096       break;
1097    case 0xe0:
1098       obj_class = NVE4_P2MF_CLASS;
1099       break;
1100    default:
1101       obj_class = NVC0_M2MF_CLASS;
1102       break;
1103    }
1104    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
1105                             &screen->m2mf);
1106    if (ret)
1107       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
1108
1109    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
1110    PUSH_DATA (push, screen->m2mf->oclass);
1111    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1112       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1113       PUSH_DATA (push, 0xa0b5);
1114    }
1115
1116    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1117                             &screen->eng2d);
1118    if (ret)
1119       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1120
1121    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1122    PUSH_DATA (push, screen->eng2d->oclass);
1123    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1124    PUSH_DATA (push, 0);
1125    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1126    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1127    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1128    PUSH_DATA (push, 0);
1129    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1130    PUSH_DATA (push, 0);
1131    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1132    PUSH_DATA (push, 0x3f);
1133    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1134    PUSH_DATA (push, 1);
1135    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1136    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1137
1138    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1139    PUSH_DATAh(push, screen->fence.bo->offset + 16);
1140    PUSH_DATA (push, screen->fence.bo->offset + 16);
1141
1142    switch (dev->chipset & ~0xf) {
1143    case 0x130:
1144       switch (dev->chipset) {
1145       case 0x130:
1146       case 0x13b:
1147          obj_class = GP100_3D_CLASS;
1148          break;
1149       default:
1150          obj_class = GP102_3D_CLASS;
1151          break;
1152       }
1153       break;
1154    case 0x120:
1155       obj_class = GM200_3D_CLASS;
1156       break;
1157    case 0x110:
1158       obj_class = GM107_3D_CLASS;
1159       break;
1160    case 0x100:
1161    case 0xf0:
1162       obj_class = NVF0_3D_CLASS;
1163       break;
1164    case 0xe0:
1165       switch (dev->chipset) {
1166       case 0xea:
1167          obj_class = NVEA_3D_CLASS;
1168          break;
1169       default:
1170          obj_class = NVE4_3D_CLASS;
1171          break;
1172       }
1173       break;
1174    case 0xd0:
1175       obj_class = NVC8_3D_CLASS;
1176       break;
1177    case 0xc0:
1178    default:
1179       switch (dev->chipset) {
1180       case 0xc8:
1181          obj_class = NVC8_3D_CLASS;
1182          break;
1183       case 0xc1:
1184          obj_class = NVC1_3D_CLASS;
1185          break;
1186       default:
1187          obj_class = NVC0_3D_CLASS;
1188          break;
1189       }
1190       break;
1191    }
1192    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1193                             &screen->eng3d);
1194    if (ret)
1195       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1196    screen->base.class_3d = obj_class;
1197
1198    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1199    PUSH_DATA (push, screen->eng3d->oclass);
1200
1201    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1202    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1203
1204    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1205       /* kill shaders after about 1 second (at 100 MHz) */
1206       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1207       PUSH_DATA (push, 0x17);
1208    }
1209
1210    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1211                     screen->base.drm->version >= 0x01000101);
1212    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1213    for (i = 0; i < 8; ++i)
1214       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1215
1216    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1217    PUSH_DATA (push, 1);
1218
1219    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1220    PUSH_DATA (push, 0);
1221    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1222    PUSH_DATA (push, 0);
1223    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1224    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1225    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1226    PUSH_DATA (push, 0);
1227    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1228    PUSH_DATA (push, 1);
1229    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1230    PUSH_DATA (push, 1);
1231    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1232    PUSH_DATA (push, 1);
1233    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1234    PUSH_DATA (push, 0);
1235    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1236    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1237    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1238       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1239    } else {
1240       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1241       PUSH_DATA (push, 15);
1242    }
1243    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1244    PUSH_DATA (push, 8); /* 128 */
1245    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1246    PUSH_DATA (push, 1);
1247    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1248       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1249       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1250    }
1251
1252    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1253
1254    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1255    if (ret)
1256       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1257
1258    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1259    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1260                         &screen->uniform_bo);
1261    if (ret)
1262       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1263
1264    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1265
1266    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1267    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1268    PUSH_DATA (push, 256);
1269    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1270    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1271    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1272    PUSH_DATA (push, 0);
1273    PUSH_DATAf(push, 0.0f);
1274    PUSH_DATAf(push, 0.0f);
1275    PUSH_DATAf(push, 0.0f);
1276    PUSH_DATAf(push, 0.0f);
1277    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1278    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1279    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1280
1281    if (screen->base.drm->version >= 0x01000101) {
1282       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1283       if (ret)
1284          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1285    } else {
1286       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1287          value = (8 << 8) | 4;
1288       else
1289          value = (16 << 8) | 4;
1290    }
1291    screen->gpc_count = value & 0x000000ff;
1292    screen->mp_count = value >> 8;
1293    screen->mp_count_compute = screen->mp_count;
1294
1295    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1296    if (ret)
1297       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1298
1299    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1300    PUSH_DATAh(push, screen->tls->offset);
1301    PUSH_DATA (push, screen->tls->offset);
1302    PUSH_DATA (push, screen->tls->size >> 32);
1303    PUSH_DATA (push, screen->tls->size);
1304    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1305    PUSH_DATA (push, 0);
1306    /* Reduce likelihood of collision with real buffers by placing the hole at
1307     * the top of the 4G area. This will have to be dealt with for real
1308     * eventually by blocking off that area from the VM.
1309     */
1310    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1311    PUSH_DATA (push, 0xff << 24);
1312
1313    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1314       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1315                            &screen->poly_cache);
1316       if (ret)
1317          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1318
1319       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1320       PUSH_DATAh(push, screen->poly_cache->offset);
1321       PUSH_DATA (push, screen->poly_cache->offset);
1322       PUSH_DATA (push, 3);
1323    }
1324
1325    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1326                         &screen->txc);
1327    if (ret)
1328       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1329
1330    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1331    PUSH_DATAh(push, screen->txc->offset);
1332    PUSH_DATA (push, screen->txc->offset);
1333    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1334    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1335       screen->tic.maxwell = true;
1336       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1337          screen->tic.maxwell =
1338             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1339          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1340       }
1341    }
1342
1343    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1344    PUSH_DATAh(push, screen->txc->offset + 65536);
1345    PUSH_DATA (push, screen->txc->offset + 65536);
1346    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1347
1348    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1349    PUSH_DATA (push, 0);
1350    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1351    PUSH_DATA (push, 0);
1352    PUSH_DATA (push, 0);
1353    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1354    PUSH_DATA (push, 0x3f);
1355
1356    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1357    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1358    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1359    for (i = 0; i < 8 * 2; ++i)
1360       PUSH_DATA(push, 0);
1361    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1362    PUSH_DATA (push, 0);
1363    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1364    PUSH_DATA (push, 0);
1365
1366    /* neither scissors, viewport nor stencil mask should affect clears */
1367    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1368    PUSH_DATA (push, 0);
1369
1370    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1371    PUSH_DATA (push, 1);
1372    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1373       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1374       PUSH_DATAf(push, 0.0f);
1375       PUSH_DATAf(push, 1.0f);
1376    }
1377    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1378    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1379
1380    /* We use scissors instead of exact view volume clipping,
1381     * so they're always enabled.
1382     */
1383    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1384       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1385       PUSH_DATA (push, 1);
1386       PUSH_DATA (push, 16384 << 16);
1387       PUSH_DATA (push, 16384 << 16);
1388    }
1389
1390 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1391
1392    i = 0;
1393    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1394    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1395    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1396    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1397    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1398    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1399    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1400    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1401    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1402    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1403    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1404    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1405    MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1406    MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
1407    MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
1408    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1409
1410    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1411    PUSH_DATA (push, 1);
1412    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1413    PUSH_DATA (push, 1);
1414    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1415    PUSH_DATA (push, 0x40);
1416    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1417    PUSH_DATA (push, 0);
1418    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1419    PUSH_DATA (push, 0x30);
1420    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1421    PUSH_DATA (push, 3);
1422    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1423    PUSH_DATA (push, 0x20);
1424    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1425    PUSH_DATA (push, 0x00);
1426    screen->save_state.patch_vertices = 3;
1427
1428    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1429    PUSH_DATA (push, 0);
1430    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1431    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1432
1433    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1434
1435    if (nvc0_screen_init_compute(screen))
1436       goto fail;
1437
1438    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1439    for (i = 0; i < 5; ++i) {
1440       unsigned j = 0;
1441       for (j = 0; j < 16; j++)
1442          screen->cb_bindings[i][j].size = -1;
1443
1444       /* TIC and TSC entries for each unit (nve4+ only) */
1445       /* auxiliary constants (6 user clip planes, base instance id) */
1446       nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1447                              screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1448       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1449          unsigned j;
1450          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1451          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1452          for (j = 0; j < 8; ++j)
1453             PUSH_DATA(push, j);
1454       } else {
1455          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1456          PUSH_DATA (push, 0x54);
1457       }
1458
1459       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1460       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1461       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1462       PUSH_DATA (push, 0); /* 0 */
1463       PUSH_DATA (push, 0);
1464       PUSH_DATA (push, 1); /* 1 */
1465       PUSH_DATA (push, 0);
1466       PUSH_DATA (push, 0); /* 2 */
1467       PUSH_DATA (push, 1);
1468       PUSH_DATA (push, 1); /* 3 */
1469       PUSH_DATA (push, 1);
1470       PUSH_DATA (push, 2); /* 4 */
1471       PUSH_DATA (push, 0);
1472       PUSH_DATA (push, 3); /* 5 */
1473       PUSH_DATA (push, 0);
1474       PUSH_DATA (push, 2); /* 6 */
1475       PUSH_DATA (push, 1);
1476       PUSH_DATA (push, 3); /* 7 */
1477       PUSH_DATA (push, 1);
1478    }
1479    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1480    PUSH_DATA (push, 0);
1481
1482    PUSH_KICK (push);
1483
1484    screen->tic.entries = CALLOC(
1485          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1486          sizeof(void *));
1487    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1488    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1489
1490    if (!nvc0_blitter_create(screen))
1491       goto fail;
1492
1493    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1494
1495    return &screen->base;
1496
1497 fail:
1498    screen->base.base.context_create = NULL;
1499    return &screen->base;
1500 }
1501
1502 int
1503 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1504 {
1505    int i = screen->tic.next;
1506
1507    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1508       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1509
1510    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1511
1512    if (screen->tic.entries[i])
1513       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1514
1515    screen->tic.entries[i] = entry;
1516    return i;
1517 }
1518
1519 int
1520 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1521 {
1522    int i = screen->tsc.next;
1523
1524    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1525       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1526
1527    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1528
1529    if (screen->tsc.entries[i])
1530       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1531
1532    screen->tsc.entries[i] = entry;
1533    return i;
1534 }