src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    if (sample_count > 8)
  49       return false;
  50    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  51       return false;
  52
  53    if (!util_format_is_supported(format, bindings))
  54       return false;
  55
  56    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  57       if (util_format_get_blocksizebits(format) == 3 * 32)
  58          return false;
  59
  60    if (bindings & PIPE_BIND_LINEAR)
  61       if (util_format_is_depth_or_stencil(format) ||
  62           (target != PIPE_TEXTURE_1D &&
  63            target != PIPE_TEXTURE_2D &&
  64            target != PIPE_TEXTURE_RECT) ||
  65           sample_count > 1)
  66          return false;
  67
  68    /* transfers & shared are always supported */
  69    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  70                  PIPE_BIND_TRANSFER_WRITE |
  71                  PIPE_BIND_LINEAR |
  72                  PIPE_BIND_SHARED);
  73
  74    return (( nvc0_format_table[format].usage |
  75             nvc0_vertex_format[format].usage) & bindings) == bindings;
  76 }
  77
  78 static int
  79 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  80 {
  81    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  82    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  83
  84    switch (param) {
  85    /* non-boolean caps */
  86    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  87    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  88       return 15;
  89    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  90       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  91    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  92       return 2048;
  93    case PIPE_CAP_MIN_TEXEL_OFFSET:
  94       return -8;
  95    case PIPE_CAP_MAX_TEXEL_OFFSET:
  96       return 7;
  97    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  98       return -32;
  99    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 100       return 31;
 101    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 102       return 128 * 1024 * 1024;
 103    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 104       return 410;
 105    case PIPE_CAP_MAX_RENDER_TARGETS:
 106       return 8;
 107    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 108       return 1;
 109    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 110       return 4;
 111    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 112    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 113       return 128;
 114    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 115    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 116       return 1024;
 117    case PIPE_CAP_MAX_VERTEX_STREAMS:
 118       return 4;
 119    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 120       return 2048;
 121    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 122       return 256;
 123    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 124       return 16; /* 256 for binding as RT, but that's not possible in GL */
 125    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 126       return 16;
 127    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 128       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 129    case PIPE_CAP_MAX_VIEWPORTS:
 130       return NVC0_MAX_VIEWPORTS;
 131    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 132       return 4;
 133    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 134       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 135    case PIPE_CAP_ENDIANNESS:
 136       return PIPE_ENDIAN_LITTLE;
 137    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 138       return 30;
 139
 140    /* supported caps */
 141    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 142    case PIPE_CAP_TEXTURE_SWIZZLE:
 143    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 144    case PIPE_CAP_NPOT_TEXTURES:
 145    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 146    case PIPE_CAP_ANISOTROPIC_FILTER:
 147    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 148    case PIPE_CAP_CUBE_MAP_ARRAY:
 149    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 150    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 151    case PIPE_CAP_TWO_SIDED_STENCIL:
 152    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 153    case PIPE_CAP_POINT_SPRITE:
 154    case PIPE_CAP_TGSI_TEXCOORD:
 155    case PIPE_CAP_SM3:
 156    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 157    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 158    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 159    case PIPE_CAP_QUERY_TIMESTAMP:
 160    case PIPE_CAP_QUERY_TIME_ELAPSED:
 161    case PIPE_CAP_OCCLUSION_QUERY:
 162    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 163    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 164    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 165    case PIPE_CAP_INDEP_BLEND_ENABLE:
 166    case PIPE_CAP_INDEP_BLEND_FUNC:
 167    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 168    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 169    case PIPE_CAP_PRIMITIVE_RESTART:
 170    case PIPE_CAP_TGSI_INSTANCEID:
 171    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 172    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 173    case PIPE_CAP_CONDITIONAL_RENDER:
 174    case PIPE_CAP_TEXTURE_BARRIER:
 175    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 176    case PIPE_CAP_START_INSTANCE:
 177    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 178    case PIPE_CAP_DRAW_INDIRECT:
 179    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 180    case PIPE_CAP_USER_INDEX_BUFFERS:
 181    case PIPE_CAP_USER_VERTEX_BUFFERS:
 182    case PIPE_CAP_TEXTURE_QUERY_LOD:
 183    case PIPE_CAP_SAMPLE_SHADING:
 184    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 185    case PIPE_CAP_TEXTURE_GATHER_SM5:
 186    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 187    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 188    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 189    case PIPE_CAP_CLIP_HALFZ:
 190    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 191    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 192    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 193    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 194    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 195    case PIPE_CAP_TGSI_TXQS:
 196    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 197    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 198    case PIPE_CAP_SHAREABLE_SHADERS:
 199    case PIPE_CAP_CLEAR_TEXTURE:
 200    case PIPE_CAP_DRAW_PARAMETERS:
 201    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 202    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 203    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 204    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 205    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 206       return 1;
 207    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 208       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 209    case PIPE_CAP_COMPUTE:
 210       if (debug_get_bool_option("NVF0_COMPUTE", false))
 211          return 1;
 212       return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
 213    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 214       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 215
 216    /* unsupported caps */
 217    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 218    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 219    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 220    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 221    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 222    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 223    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 224    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 225    case PIPE_CAP_FAKE_SW_MSAA:
 226    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 227    case PIPE_CAP_VERTEXID_NOBASE:
 228    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 229    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 230    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 231    case PIPE_CAP_INVALIDATE_BUFFER:
 232    case PIPE_CAP_GENERATE_MIPMAP:
 233    case PIPE_CAP_STRING_MARKER:
 234    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 235    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 236    case PIPE_CAP_QUERY_MEMORY_INFO:
 237    case PIPE_CAP_PCI_GROUP:
 238    case PIPE_CAP_PCI_BUS:
 239    case PIPE_CAP_PCI_DEVICE:
 240    case PIPE_CAP_PCI_FUNCTION:
 241       return 0;
 242
 243    case PIPE_CAP_VENDOR_ID:
 244       return 0x10de;
 245    case PIPE_CAP_DEVICE_ID: {
 246       uint64_t device_id;
 247       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 248          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 249          return -1;
 250       }
 251       return device_id;
 252    }
 253    case PIPE_CAP_ACCELERATED:
 254       return 1;
 255    case PIPE_CAP_VIDEO_MEMORY:
 256       return dev->vram_size >> 20;
 257    case PIPE_CAP_UMA:
 258       return 0;
 259    }
 260
 261    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 262    return 0;
 263 }
 264
 265 static int
 266 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 267                              enum pipe_shader_cap param)
 268 {
 269    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 270
 271    switch (shader) {
 272    case PIPE_SHADER_VERTEX:
 273    case PIPE_SHADER_GEOMETRY:
 274    case PIPE_SHADER_FRAGMENT:
 275       break;
 276    case PIPE_SHADER_TESS_CTRL:
 277    case PIPE_SHADER_TESS_EVAL:
 278       if (class_3d >= GM107_3D_CLASS)
 279          return 0;
 280       break;
 281    case PIPE_SHADER_COMPUTE:
 282       if (!debug_get_bool_option("NVF0_COMPUTE", false))
 283          if (class_3d > NVE4_3D_CLASS)
 284             return 0;
 285       break;
 286    default:
 287       return 0;
 288    }
 289
 290    switch (param) {
 291    case PIPE_SHADER_CAP_PREFERRED_IR:
 292       return PIPE_SHADER_IR_TGSI;
 293    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 294       if (class_3d == NVF0_3D_CLASS &&
 295           !debug_get_bool_option("NVF0_COMPUTE", false))
 296          return 0;
 297       return 1 << PIPE_SHADER_IR_TGSI;
 298    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 299    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 300    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 301    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 302       return 16384;
 303    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 304       return 16;
 305    case PIPE_SHADER_CAP_MAX_INPUTS:
 306       if (shader == PIPE_SHADER_VERTEX)
 307          return 32;
 308       /* NOTE: These only count our slots for GENERIC varyings.
 309        * The address space may be larger, but the actual hard limit seems to be
 310        * less than what the address space layout permits, so don't add TEXCOORD,
 311        * COLOR, etc. here.
 312        */
 313       if (shader == PIPE_SHADER_FRAGMENT)
 314          return 0x1f0 / 16;
 315       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 316        * and excludes 0x60 per-patch inputs.
 317        */
 318       return 0x200 / 16;
 319    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 320       return 32;
 321    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 322       return 65536;
 323    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 324       return NVC0_MAX_PIPE_CONSTBUFS;
 325    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 326       return shader != PIPE_SHADER_FRAGMENT;
 327    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 328       return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
 329    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 330    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 331       return 1;
 332    case PIPE_SHADER_CAP_MAX_PREDS:
 333       return 0;
 334    case PIPE_SHADER_CAP_MAX_TEMPS:
 335       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 336    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 337       return 1;
 338    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 339       return 1;
 340    case PIPE_SHADER_CAP_SUBROUTINES:
 341       return 1;
 342    case PIPE_SHADER_CAP_INTEGERS:
 343       return 1;
 344    case PIPE_SHADER_CAP_DOUBLES:
 345       return 1;
 346    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 347       return 1;
 348    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 349       return 1;
 350    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 351    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 352       return 0;
 353    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 354       return NVC0_MAX_BUFFERS;
 355    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 356       return 16; /* would be 32 in linked (OpenGL-style) mode */
 357    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 358       return 16; /* XXX not sure if more are really safe */
 359    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 360       return 32;
 361    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 362       return 0;
 363    default:
 364       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 365       return 0;
 366    }
 367 }
 368
 369 static float
 370 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 371 {
 372    switch (param) {
 373    case PIPE_CAPF_MAX_LINE_WIDTH:
 374    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 375       return 10.0f;
 376    case PIPE_CAPF_MAX_POINT_WIDTH:
 377       return 63.0f;
 378    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 379       return 63.375f;
 380    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 381       return 16.0f;
 382    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 383       return 15.0f;
 384    case PIPE_CAPF_GUARD_BAND_LEFT:
 385    case PIPE_CAPF_GUARD_BAND_TOP:
 386       return 0.0f;
 387    case PIPE_CAPF_GUARD_BAND_RIGHT:
 388    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 389       return 0.0f; /* that or infinity */
 390    }
 391
 392    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 393    return 0.0f;
 394 }
 395
 396 static int
 397 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 398                               enum pipe_compute_cap param, void *data)
 399 {
 400    struct nvc0_screen *screen = nvc0_screen(pscreen);
 401    const uint16_t obj_class = screen->compute->oclass;
 402
 403 #define RET(x) do {                  \
 404    if (data)                         \
 405       memcpy(data, x, sizeof(x));    \
 406    return sizeof(x);                 \
 407 } while (0)
 408
 409    switch (param) {
 410    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 411       RET((uint64_t []) { 3 });
 412    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 413       if (obj_class >= NVE4_COMPUTE_CLASS) {
 414          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 415       } else {
 416          RET(((uint64_t []) { 65535, 65535, 65535 }));
 417       }
 418    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 419       RET(((uint64_t []) { 1024, 1024, 64 }));
 420    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 421       RET((uint64_t []) { 1024 });
 422    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 423       RET((uint64_t []) { 1ULL << 40 });
 424    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 425       RET((uint64_t []) { 48 << 10 });
 426    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 427       RET((uint64_t []) { 512 << 10 });
 428    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 429       RET((uint64_t []) { 4096 });
 430    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 431       RET((uint32_t []) { 32 });
 432    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 433       RET((uint64_t []) { 1ULL << 40 });
 434    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 435       RET((uint32_t []) { 0 });
 436    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 437       RET((uint32_t []) { screen->mp_count_compute });
 438    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 439       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 440    default:
 441       return 0;
 442    }
 443
 444 #undef RET
 445 }
 446
 447 static void
 448 nvc0_screen_destroy(struct pipe_screen *pscreen)
 449 {
 450    struct nvc0_screen *screen = nvc0_screen(pscreen);
 451
 452    if (!nouveau_drm_screen_unref(&screen->base))
 453       return;
 454
 455    if (screen->base.fence.current) {
 456       struct nouveau_fence *current = NULL;
 457
 458       /* nouveau_fence_wait will create a new current fence, so wait on the
 459        * _current_ one, and remove both.
 460        */
 461       nouveau_fence_ref(screen->base.fence.current, &current);
 462       nouveau_fence_wait(current, NULL);
 463       nouveau_fence_ref(NULL, &current);
 464       nouveau_fence_ref(NULL, &screen->base.fence.current);
 465    }
 466    if (screen->base.pushbuf)
 467       screen->base.pushbuf->user_priv = NULL;
 468
 469    if (screen->blitter)
 470       nvc0_blitter_destroy(screen);
 471    if (screen->pm.prog) {
 472       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 473       nvc0_program_destroy(NULL, screen->pm.prog);
 474       FREE(screen->pm.prog);
 475    }
 476
 477    nouveau_bo_ref(NULL, &screen->text);
 478    nouveau_bo_ref(NULL, &screen->uniform_bo);
 479    nouveau_bo_ref(NULL, &screen->tls);
 480    nouveau_bo_ref(NULL, &screen->txc);
 481    nouveau_bo_ref(NULL, &screen->fence.bo);
 482    nouveau_bo_ref(NULL, &screen->poly_cache);
 483    nouveau_bo_ref(NULL, &screen->parm);
 484
 485    nouveau_heap_destroy(&screen->lib_code);
 486    nouveau_heap_destroy(&screen->text_heap);
 487
 488    FREE(screen->tic.entries);
 489
 490    nouveau_object_del(&screen->eng3d);
 491    nouveau_object_del(&screen->eng2d);
 492    nouveau_object_del(&screen->m2mf);
 493    nouveau_object_del(&screen->compute);
 494    nouveau_object_del(&screen->nvsw);
 495
 496    nouveau_screen_fini(&screen->base);
 497
 498    FREE(screen);
 499 }
 500
 501 static int
 502 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 503                      unsigned size, const uint32_t *data)
 504 {
 505    struct nouveau_pushbuf *push = screen->base.pushbuf;
 506
 507    size /= 4;
 508
 509    assert((pos + size) <= 0x800);
 510
 511    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 512    PUSH_DATA (push, (m - 0x3800) / 8);
 513    PUSH_DATA (push, pos);
 514    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 515    PUSH_DATA (push, pos);
 516    PUSH_DATAp(push, data, size);
 517
 518    return pos + size;
 519 }
 520
 521 static void
 522 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 523 {
 524    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 525    PUSH_DATA (push, 0xff);
 526    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 527    PUSH_DATA (push, 0xff);
 528    PUSH_DATA (push, 0xff);
 529    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 530    PUSH_DATA (push, 0xff);
 531    PUSH_DATA (push, 0xff);
 532    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 533    PUSH_DATA (push, 0x3f);
 534
 535    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 536    PUSH_DATA (push, (3 << 16) | 3);
 537    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 538    PUSH_DATA (push, (2 << 16) | 2);
 539
 540    if (obj_class < GM107_3D_CLASS) {
 541       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 542       PUSH_DATA (push, 0);
 543    }
 544    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 545    PUSH_DATA (push, 0x10);
 546    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 547    PUSH_DATA (push, 0x10);
 548    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 549    PUSH_DATA (push, 0x10);
 550    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 551    PUSH_DATA (push, 0x10);
 552    PUSH_DATA (push, 0x10);
 553    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 554    PUSH_DATA (push, 0x10);
 555    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 556    PUSH_DATA (push, 0xe);
 557
 558    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 559    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 560    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 561    PUSH_DATA (push, 0);
 562    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 563    PUSH_DATA (push, 3);
 564
 565    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 566    PUSH_DATA (push, 0x3fffff);
 567    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 568    PUSH_DATA (push, 1);
 569    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 570    PUSH_DATA (push, 1);
 571
 572    if (obj_class < GM107_3D_CLASS) {
 573       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 574       PUSH_DATA (push, 3);
 575
 576       if (obj_class >= NVE4_3D_CLASS) {
 577          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 578          PUSH_DATA (push, 1);
 579       }
 580    }
 581
 582    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 583     * are supposed to do */
 584 }
 585
 586 static void
 587 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 588 {
 589    struct nvc0_screen *screen = nvc0_screen(pscreen);
 590    struct nouveau_pushbuf *push = screen->base.pushbuf;
 591
 592    /* we need to do it after possible flush in MARK_RING */
 593    *sequence = ++screen->base.fence.sequence;
 594
 595    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 596    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 597    PUSH_DATAh(push, screen->fence.bo->offset);
 598    PUSH_DATA (push, screen->fence.bo->offset);
 599    PUSH_DATA (push, *sequence);
 600    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 601               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 602 }
 603
 604 static u32
 605 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 606 {
 607    struct nvc0_screen *screen = nvc0_screen(pscreen);
 608    return screen->fence.map[0];
 609 }
 610
 611 static int
 612 nvc0_screen_init_compute(struct nvc0_screen *screen)
 613 {
 614    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 615
 616    switch (screen->base.device->chipset & ~0xf) {
 617    case 0xc0:
 618    case 0xd0:
 619       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 620    case 0xe0:
 621       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 622    case 0xf0:
 623    case 0x100:
 624    case 0x110:
 625       if (debug_get_bool_option("NVF0_COMPUTE", false))
 626          return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 627    case 0x120:
 628       return 0;
 629    default:
 630       return -1;
 631    }
 632 }
 633
 634 bool
 635 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 636                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 637 {
 638    struct nouveau_bo *bo = NULL;
 639    int ret;
 640    uint64_t size = (lpos + lneg) * 32 + cstack;
 641
 642    if (size >= (1 << 20)) {
 643       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 644       return false;
 645    }
 646
 647    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 648    size  = align(size, 0x8000);
 649    size *= screen->mp_count;
 650
 651    size = align(size, 1 << 17);
 652
 653    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 654                         NULL, &bo);
 655    if (ret) {
 656       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 657       return false;
 658    }
 659    nouveau_bo_ref(NULL, &screen->tls);
 660    screen->tls = bo;
 661    return true;
 662 }
 663
 664 #define FAIL_SCREEN_INIT(str, err)                    \
 665    do {                                               \
 666       NOUVEAU_ERR(str, err);                          \
 667       goto fail;                                      \
 668    } while(0)
 669
 670 struct nouveau_screen *
 671 nvc0_screen_create(struct nouveau_device *dev)
 672 {
 673    struct nvc0_screen *screen;
 674    struct pipe_screen *pscreen;
 675    struct nouveau_object *chan;
 676    struct nouveau_pushbuf *push;
 677    uint64_t value;
 678    uint32_t obj_class;
 679    uint32_t flags;
 680    int ret;
 681    unsigned i;
 682
 683    switch (dev->chipset & ~0xf) {
 684    case 0xc0:
 685    case 0xd0:
 686    case 0xe0:
 687    case 0xf0:
 688    case 0x100:
 689    case 0x110:
 690    case 0x120:
 691       break;
 692    default:
 693       return NULL;
 694    }
 695
 696    screen = CALLOC_STRUCT(nvc0_screen);
 697    if (!screen)
 698       return NULL;
 699    pscreen = &screen->base.base;
 700    pscreen->destroy = nvc0_screen_destroy;
 701
 702    ret = nouveau_screen_init(&screen->base, dev);
 703    if (ret) {
 704       nvc0_screen_destroy(pscreen);
 705       return NULL;
 706    }
 707    chan = screen->base.channel;
 708    push = screen->base.pushbuf;
 709    push->user_priv = screen;
 710    push->rsvd_kick = 5;
 711
 712    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 713       PIPE_BIND_SHADER_BUFFER |
 714       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 715       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 716    screen->base.sysmem_bindings |=
 717       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 718
 719    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 720       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 721       screen->base.vidmem_bindings = 0;
 722    }
 723
 724    pscreen->context_create = nvc0_create;
 725    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 726    pscreen->get_param = nvc0_screen_get_param;
 727    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 728    pscreen->get_paramf = nvc0_screen_get_paramf;
 729    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 730    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 731
 732    nvc0_screen_init_resource_functions(pscreen);
 733
 734    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 735    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 736
 737    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 738    if (screen->base.drm->version >= 0x01000202)
 739       flags |= NOUVEAU_BO_COHERENT;
 740
 741    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 742    if (ret)
 743       goto fail;
 744    nouveau_bo_map(screen->fence.bo, 0, NULL);
 745    screen->fence.map = screen->fence.bo->map;
 746    screen->base.fence.emit = nvc0_screen_fence_emit;
 747    screen->base.fence.update = nvc0_screen_fence_update;
 748
 749
 750    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 751                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 752    if (ret)
 753       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 754
 755    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 756    PUSH_DATA (push, screen->nvsw->handle);
 757
 758    switch (dev->chipset & ~0xf) {
 759    case 0x120:
 760    case 0x110:
 761    case 0x100:
 762    case 0xf0:
 763       obj_class = NVF0_P2MF_CLASS;
 764       break;
 765    case 0xe0:
 766       obj_class = NVE4_P2MF_CLASS;
 767       break;
 768    default:
 769       obj_class = NVC0_M2MF_CLASS;
 770       break;
 771    }
 772    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 773                             &screen->m2mf);
 774    if (ret)
 775       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 776
 777    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 778    PUSH_DATA (push, screen->m2mf->oclass);
 779    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 780       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 781       PUSH_DATA (push, 0xa0b5);
 782    }
 783
 784    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 785                             &screen->eng2d);
 786    if (ret)
 787       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 788
 789    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 790    PUSH_DATA (push, screen->eng2d->oclass);
 791    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 792    PUSH_DATA (push, 0);
 793    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 794    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 795    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 796    PUSH_DATA (push, 0);
 797    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 798    PUSH_DATA (push, 0);
 799    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 800    PUSH_DATA (push, 0x3f);
 801    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 802    PUSH_DATA (push, 1);
 803    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 804    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 805
 806    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 807    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 808    PUSH_DATA (push, screen->fence.bo->offset + 16);
 809
 810    switch (dev->chipset & ~0xf) {
 811    case 0x120:
 812       obj_class = GM200_3D_CLASS;
 813       break;
 814    case 0x110:
 815       obj_class = GM107_3D_CLASS;
 816       break;
 817    case 0x100:
 818    case 0xf0:
 819       obj_class = NVF0_3D_CLASS;
 820       break;
 821    case 0xe0:
 822       switch (dev->chipset) {
 823       case 0xea:
 824          obj_class = NVEA_3D_CLASS;
 825          break;
 826       default:
 827          obj_class = NVE4_3D_CLASS;
 828          break;
 829       }
 830       break;
 831    case 0xd0:
 832       obj_class = NVC8_3D_CLASS;
 833       break;
 834    case 0xc0:
 835    default:
 836       switch (dev->chipset) {
 837       case 0xc8:
 838          obj_class = NVC8_3D_CLASS;
 839          break;
 840       case 0xc1:
 841          obj_class = NVC1_3D_CLASS;
 842          break;
 843       default:
 844          obj_class = NVC0_3D_CLASS;
 845          break;
 846       }
 847       break;
 848    }
 849    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 850                             &screen->eng3d);
 851    if (ret)
 852       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 853    screen->base.class_3d = obj_class;
 854
 855    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 856    PUSH_DATA (push, screen->eng3d->oclass);
 857
 858    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 859    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 860
 861    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 862       /* kill shaders after about 1 second (at 100 MHz) */
 863       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 864       PUSH_DATA (push, 0x17);
 865    }
 866
 867    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 868                     screen->base.drm->version >= 0x01000101);
 869    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 870    for (i = 0; i < 8; ++i)
 871            PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 872
 873    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 874    PUSH_DATA (push, 1);
 875
 876    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 877    PUSH_DATA (push, 0);
 878    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 879    PUSH_DATA (push, 0);
 880    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 881    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 882    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 883    PUSH_DATA (push, 0);
 884    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 885    PUSH_DATA (push, 1);
 886    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 887    PUSH_DATA (push, 1);
 888    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 889    PUSH_DATA (push, 1);
 890    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 891    PUSH_DATA (push, 0);
 892    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 893    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 894    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 895       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 896    } else {
 897       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 898       PUSH_DATA (push, 15);
 899    }
 900    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 901    PUSH_DATA (push, 8); /* 128 */
 902    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 903    PUSH_DATA (push, 1);
 904    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 905       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 906       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 907    }
 908
 909    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 910
 911    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
 912                         &screen->text);
 913    if (ret)
 914       goto fail;
 915
 916    /* XXX: getting a page fault at the end of the code buffer every few
 917     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 918     */
 919    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 920
 921    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
 922                         &screen->uniform_bo);
 923    if (ret)
 924       goto fail;
 925
 926    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
 927
 928    for (i = 0; i < 5; ++i) {
 929       /* TIC and TSC entries for each unit (nve4+ only) */
 930       /* auxiliary constants (6 user clip planes, base instance id) */
 931       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 932       PUSH_DATA (push, 1024);
 933       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 934       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 935       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 936       PUSH_DATA (push, (15 << 4) | 1);
 937       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 938          unsigned j;
 939          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 940          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
 941          for (j = 0; j < 8; ++j)
 942             PUSH_DATA(push, j);
 943       } else {
 944          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 945          PUSH_DATA (push, 0x54);
 946       }
 947    }
 948    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 949    PUSH_DATA (push, 0);
 950
 951    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 952    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 953    PUSH_DATA (push, 256);
 954    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 955    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 956    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 957    PUSH_DATA (push, 0);
 958    PUSH_DATAf(push, 0.0f);
 959    PUSH_DATAf(push, 0.0f);
 960    PUSH_DATAf(push, 0.0f);
 961    PUSH_DATAf(push, 0.0f);
 962    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 963    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 964    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 965
 966    if (screen->base.drm->version >= 0x01000101) {
 967       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 968       if (ret) {
 969          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 970          goto fail;
 971       }
 972    } else {
 973       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 974          value = (8 << 8) | 4;
 975       else
 976          value = (16 << 8) | 4;
 977    }
 978    screen->gpc_count = value & 0x000000ff;
 979    screen->mp_count = value >> 8;
 980    screen->mp_count_compute = screen->mp_count;
 981
 982    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 983
 984    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 985    PUSH_DATAh(push, screen->text->offset);
 986    PUSH_DATA (push, screen->text->offset);
 987    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 988    PUSH_DATAh(push, screen->tls->offset);
 989    PUSH_DATA (push, screen->tls->offset);
 990    PUSH_DATA (push, screen->tls->size >> 32);
 991    PUSH_DATA (push, screen->tls->size);
 992    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 993    PUSH_DATA (push, 0);
 994    /* Reduce likelihood of collision with real buffers by placing the hole at
 995     * the top of the 4G area. This will have to be dealt with for real
 996     * eventually by blocking off that area from the VM.
 997     */
 998    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 999    PUSH_DATA (push, 0xff << 24);
1000
1001    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1002       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1003                            &screen->poly_cache);
1004       if (ret)
1005          goto fail;
1006
1007       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1008       PUSH_DATAh(push, screen->poly_cache->offset);
1009       PUSH_DATA (push, screen->poly_cache->offset);
1010       PUSH_DATA (push, 3);
1011    }
1012
1013    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1014                         &screen->txc);
1015    if (ret)
1016       goto fail;
1017
1018    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1019    PUSH_DATAh(push, screen->txc->offset);
1020    PUSH_DATA (push, screen->txc->offset);
1021    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1022    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1023       screen->tic.maxwell = true;
1024       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1025          screen->tic.maxwell =
1026             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1027          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1028       }
1029    }
1030
1031    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1032    PUSH_DATAh(push, screen->txc->offset + 65536);
1033    PUSH_DATA (push, screen->txc->offset + 65536);
1034    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1035
1036    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1037    PUSH_DATA (push, 0);
1038    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1039    PUSH_DATA (push, 0);
1040    PUSH_DATA (push, 0);
1041    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1042    PUSH_DATA (push, 0x3f);
1043
1044    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1045    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1046    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1047    for (i = 0; i < 8 * 2; ++i)
1048       PUSH_DATA(push, 0);
1049    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1050    PUSH_DATA (push, 0);
1051    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1052    PUSH_DATA (push, 0);
1053
1054    /* neither scissors, viewport nor stencil mask should affect clears */
1055    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1056    PUSH_DATA (push, 0);
1057
1058    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1059    PUSH_DATA (push, 1);
1060    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1061       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1062       PUSH_DATAf(push, 0.0f);
1063       PUSH_DATAf(push, 1.0f);
1064    }
1065    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1066    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1067
1068    /* We use scissors instead of exact view volume clipping,
1069     * so they're always enabled.
1070     */
1071    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1072       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1073       PUSH_DATA (push, 1);
1074       PUSH_DATA (push, 8192 << 16);
1075       PUSH_DATA (push, 8192 << 16);
1076    }
1077
1078 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1079
1080    i = 0;
1081    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1082    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1083    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1084    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1085    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1086    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1087    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1088    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1089    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1090    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1091    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1092    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1093    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1094
1095    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1096    PUSH_DATA (push, 1);
1097    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1098    PUSH_DATA (push, 1);
1099    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1100    PUSH_DATA (push, 0x40);
1101    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1102    PUSH_DATA (push, 0);
1103    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1104    PUSH_DATA (push, 0x30);
1105    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1106    PUSH_DATA (push, 3);
1107    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1108    PUSH_DATA (push, 0x20);
1109    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1110    PUSH_DATA (push, 0x00);
1111    screen->save_state.patch_vertices = 3;
1112
1113    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1114    PUSH_DATA (push, 0);
1115    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1116    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1117
1118    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1119
1120    if (nvc0_screen_init_compute(screen))
1121       goto fail;
1122
1123    PUSH_KICK (push);
1124
1125    screen->tic.entries = CALLOC(4096, sizeof(void *));
1126    screen->tsc.entries = screen->tic.entries + 2048;
1127
1128    if (!nvc0_blitter_create(screen))
1129       goto fail;
1130
1131    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1132
1133    return &screen->base;
1134
1135 fail:
1136    screen->base.base.context_create = NULL;
1137    return &screen->base;
1138 }
1139
1140 int
1141 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1142 {
1143    int i = screen->tic.next;
1144
1145    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1146       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1147
1148    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1149
1150    if (screen->tic.entries[i])
1151       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1152
1153    screen->tic.entries[i] = entry;
1154    return i;
1155 }
1156
1157 int
1158 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1159 {
1160    int i = screen->tsc.next;
1161
1162    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1163       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1164
1165    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1166
1167    if (screen->tsc.entries[i])
1168       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1169
1170    screen->tsc.entries[i] = entry;
1171    return i;
1172 }