src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/mme/com9097.mme.h"
  36 #include "nvc0/mme/com90c0.mme.h"
  37
  38 #include "nv50/g80_texture.xml.h"
  39
  40 static boolean
  41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  42                                 enum pipe_format format,
  43                                 enum pipe_texture_target target,
  44                                 unsigned sample_count,
  45                                 unsigned storage_sample_count,
  46                                 unsigned bindings)
  47 {
  48    const struct util_format_description *desc = util_format_description(format);
  49
  50    if (sample_count > 8)
  51       return false;
  52    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  53       return false;
  54
  55    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  56       return false;
  57
  58    /* Short-circuit the rest of the logic -- this is used by the state tracker
  59     * to determine valid MS levels in a no-attachments scenario.
  60     */
  61    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  62       return true;
  63
  64    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  65       if (util_format_get_blocksizebits(format) == 3 * 32)
  66          return false;
  67
  68    if (bindings & PIPE_BIND_LINEAR)
  69       if (util_format_is_depth_or_stencil(format) ||
  70           (target != PIPE_TEXTURE_1D &&
  71            target != PIPE_TEXTURE_2D &&
  72            target != PIPE_TEXTURE_RECT) ||
  73           sample_count > 1)
  74          return false;
  75
  76    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  77     */
  78    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  79         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  80        /* The claim is that this should work on GM107 but it doesn't. Need to
  81         * test further and figure out if it's a nouveau issue or a HW one.
  82        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  83         */
  84        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  85       return false;
  86
  87    /* shared is always supported */
  88    bindings &= ~(PIPE_BIND_LINEAR |
  89                  PIPE_BIND_SHARED);
  90
  91    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  92       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  93           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
  94          /* This should work on Fermi, but for currently unknown reasons it
  95           * does not and results in breaking reads from pbos. */
  96          return false;
  97       }
  98    }
  99
 100    return (( nvc0_format_table[format].usage |
 101             nvc0_vertex_format[format].usage) & bindings) == bindings;
 102 }
 103
 104 static int
 105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 106 {
 107    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 108    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 109
 110    switch (param) {
 111    /* non-boolean caps */
 112    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 113    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 114       return 15;
 115    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 116       return 12;
 117    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 118       return 2048;
 119    case PIPE_CAP_MIN_TEXEL_OFFSET:
 120       return -8;
 121    case PIPE_CAP_MAX_TEXEL_OFFSET:
 122       return 7;
 123    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 124       return -32;
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126       return 31;
 127    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 128       return 128 * 1024 * 1024;
 129    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 130       return 430;
 131    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 132       return 140;
 133    case PIPE_CAP_MAX_RENDER_TARGETS:
 134       return 8;
 135    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 136       return 1;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 138       return 4;
 139    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 140    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 141       return 128;
 142    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 143    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 144       return 1024;
 145    case PIPE_CAP_MAX_VERTEX_STREAMS:
 146       return 4;
 147    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 148       return 2048;
 149    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 150       return 256;
 151    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 152       if (class_3d < GM107_3D_CLASS)
 153          return 256; /* IMAGE bindings require alignment to 256 */
 154       return 16;
 155    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 156       return 16;
 157    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 158       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 159    case PIPE_CAP_MAX_VIEWPORTS:
 160       return NVC0_MAX_VIEWPORTS;
 161    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 162       return 4;
 163    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 164       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 165    case PIPE_CAP_ENDIANNESS:
 166       return PIPE_ENDIAN_LITTLE;
 167    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 168       return 30;
 169    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 170       return NVC0_MAX_WINDOW_RECTANGLES;
 171    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 172       return class_3d >= GM200_3D_CLASS ? 8 : 0;
 173
 174    /* supported caps */
 175    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 176    case PIPE_CAP_TEXTURE_SWIZZLE:
 177    case PIPE_CAP_NPOT_TEXTURES:
 178    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 179    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 180    case PIPE_CAP_ANISOTROPIC_FILTER:
 181    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 182    case PIPE_CAP_CUBE_MAP_ARRAY:
 183    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 184    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 185    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 186    case PIPE_CAP_POINT_SPRITE:
 187    case PIPE_CAP_TGSI_TEXCOORD:
 188    case PIPE_CAP_SM3:
 189    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 190    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 191    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 192    case PIPE_CAP_QUERY_TIMESTAMP:
 193    case PIPE_CAP_QUERY_TIME_ELAPSED:
 194    case PIPE_CAP_OCCLUSION_QUERY:
 195    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 196    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 197    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 198    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 199    case PIPE_CAP_INDEP_BLEND_ENABLE:
 200    case PIPE_CAP_INDEP_BLEND_FUNC:
 201    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 202    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 203    case PIPE_CAP_PRIMITIVE_RESTART:
 204    case PIPE_CAP_TGSI_INSTANCEID:
 205    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 206    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 207    case PIPE_CAP_CONDITIONAL_RENDER:
 208    case PIPE_CAP_TEXTURE_BARRIER:
 209    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 210    case PIPE_CAP_START_INSTANCE:
 211    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 212    case PIPE_CAP_DRAW_INDIRECT:
 213    case PIPE_CAP_USER_VERTEX_BUFFERS:
 214    case PIPE_CAP_TEXTURE_QUERY_LOD:
 215    case PIPE_CAP_SAMPLE_SHADING:
 216    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 217    case PIPE_CAP_TEXTURE_GATHER_SM5:
 218    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 219    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 220    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 221    case PIPE_CAP_CLIP_HALFZ:
 222    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 223    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 224    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 225    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 226    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 227    case PIPE_CAP_TGSI_TXQS:
 228    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 229    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 230    case PIPE_CAP_SHAREABLE_SHADERS:
 231    case PIPE_CAP_CLEAR_TEXTURE:
 232    case PIPE_CAP_DRAW_PARAMETERS:
 233    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 234    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 235    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 236    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 237    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 238    case PIPE_CAP_INVALIDATE_BUFFER:
 239    case PIPE_CAP_STRING_MARKER:
 240    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 241    case PIPE_CAP_CULL_DISTANCE:
 242    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 243    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 244    case PIPE_CAP_TGSI_VOTE:
 245    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 246    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 247    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 248    case PIPE_CAP_DOUBLES:
 249    case PIPE_CAP_INT64:
 250    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 251    case PIPE_CAP_TGSI_CLOCK:
 252    case PIPE_CAP_COMPUTE:
 253    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 254    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 255    case PIPE_CAP_QUERY_SO_OVERFLOW:
 256       return 1;
 257    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 258       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 259    case PIPE_CAP_TGSI_FS_FBFETCH:
 260       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 261    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 262    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 263    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 264    case PIPE_CAP_POST_DEPTH_COVERAGE:
 265    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 266    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 267    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 268    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 269       return class_3d >= GM200_3D_CLASS;
 270    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 271       return class_3d >= GP100_3D_CLASS;
 272    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 273    case PIPE_CAP_TGSI_BALLOT:
 274    case PIPE_CAP_BINDLESS_TEXTURE:
 275       return class_3d >= NVE4_3D_CLASS;
 276
 277    /* unsupported caps */
 278    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 279    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 280    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 281    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 282    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 283    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 284    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 285    case PIPE_CAP_FAKE_SW_MSAA:
 286    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 287    case PIPE_CAP_VERTEXID_NOBASE:
 288    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 289    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 290    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 291    case PIPE_CAP_GENERATE_MIPMAP:
 292    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 293    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 294    case PIPE_CAP_QUERY_MEMORY_INFO:
 295    case PIPE_CAP_PCI_GROUP:
 296    case PIPE_CAP_PCI_BUS:
 297    case PIPE_CAP_PCI_DEVICE:
 298    case PIPE_CAP_PCI_FUNCTION:
 299    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 300    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 301    case PIPE_CAP_NATIVE_FENCE_FD:
 302    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 303    case PIPE_CAP_INT64_DIVMOD:
 304    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 305    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 306    case PIPE_CAP_MEMOBJ:
 307    case PIPE_CAP_LOAD_CONSTBUF:
 308    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 309    case PIPE_CAP_TILE_RASTER_ORDER:
 310    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 311    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 312    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 313    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 314    case PIPE_CAP_FENCE_SIGNAL:
 315    case PIPE_CAP_CONSTBUF0_FLAGS:
 316    case PIPE_CAP_PACKED_UNIFORMS:
 317    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 318       return 0;
 319
 320    case PIPE_CAP_VENDOR_ID:
 321       return 0x10de;
 322    case PIPE_CAP_DEVICE_ID: {
 323       uint64_t device_id;
 324       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 325          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 326          return -1;
 327       }
 328       return device_id;
 329    }
 330    case PIPE_CAP_ACCELERATED:
 331       return 1;
 332    case PIPE_CAP_VIDEO_MEMORY:
 333       return dev->vram_size >> 20;
 334    case PIPE_CAP_UMA:
 335       return 0;
 336    }
 337
 338    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 339    return 0;
 340 }
 341
 342 static int
 343 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 344                              enum pipe_shader_type shader,
 345                              enum pipe_shader_cap param)
 346 {
 347    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 348
 349    switch (shader) {
 350    case PIPE_SHADER_VERTEX:
 351    case PIPE_SHADER_GEOMETRY:
 352    case PIPE_SHADER_FRAGMENT:
 353    case PIPE_SHADER_COMPUTE:
 354    case PIPE_SHADER_TESS_CTRL:
 355    case PIPE_SHADER_TESS_EVAL:
 356       break;
 357    default:
 358       return 0;
 359    }
 360
 361    switch (param) {
 362    case PIPE_SHADER_CAP_PREFERRED_IR:
 363       return PIPE_SHADER_IR_TGSI;
 364    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 365       return 1 << PIPE_SHADER_IR_TGSI;
 366    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 367    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 368    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 369    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 370       return 16384;
 371    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 372       return 16;
 373    case PIPE_SHADER_CAP_MAX_INPUTS:
 374       if (shader == PIPE_SHADER_VERTEX)
 375          return 32;
 376       /* NOTE: These only count our slots for GENERIC varyings.
 377        * The address space may be larger, but the actual hard limit seems to be
 378        * less than what the address space layout permits, so don't add TEXCOORD,
 379        * COLOR, etc. here.
 380        */
 381       if (shader == PIPE_SHADER_FRAGMENT)
 382          return 0x1f0 / 16;
 383       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 384        * and excludes 0x60 per-patch inputs.
 385        */
 386       return 0x200 / 16;
 387    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 388       return 32;
 389    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 390       return NVC0_MAX_CONSTBUF_SIZE;
 391    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 392       return NVC0_MAX_PIPE_CONSTBUFS;
 393    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 394       return shader != PIPE_SHADER_FRAGMENT;
 395    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 396    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 397    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 398       return 1;
 399    case PIPE_SHADER_CAP_MAX_TEMPS:
 400       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 401    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 402       return 1;
 403    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 404       return 1;
 405    case PIPE_SHADER_CAP_SUBROUTINES:
 406       return 1;
 407    case PIPE_SHADER_CAP_INTEGERS:
 408       return 1;
 409    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 410       return 1;
 411    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 412       return 1;
 413    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 414       return 1;
 415    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 416    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 417    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 418    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 419    case PIPE_SHADER_CAP_INT64_ATOMICS:
 420    case PIPE_SHADER_CAP_FP16:
 421    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 422    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 423       return 0;
 424    case PIPE_SHADER_CAP_SCALAR_ISA:
 425       return 1;
 426    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 427       return NVC0_MAX_BUFFERS;
 428    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 429       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 430    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 431       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 432    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 433       return 32;
 434    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 435       if (class_3d >= NVE4_3D_CLASS)
 436          return NVC0_MAX_IMAGES;
 437       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 438          return NVC0_MAX_IMAGES;
 439       return 0;
 440    default:
 441       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 442       return 0;
 443    }
 444 }
 445
 446 static float
 447 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 448 {
 449    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 450
 451    switch (param) {
 452    case PIPE_CAPF_MAX_LINE_WIDTH:
 453    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 454       return 10.0f;
 455    case PIPE_CAPF_MAX_POINT_WIDTH:
 456       return 63.0f;
 457    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 458       return 63.375f;
 459    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 460       return 16.0f;
 461    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 462       return 15.0f;
 463    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 464       return 0.0f;
 465    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 466       return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
 467    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 468       return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
 469    }
 470
 471    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 472    return 0.0f;
 473 }
 474
 475 static int
 476 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 477                               enum pipe_shader_ir ir_type,
 478                               enum pipe_compute_cap param, void *data)
 479 {
 480    struct nvc0_screen *screen = nvc0_screen(pscreen);
 481    const uint16_t obj_class = screen->compute->oclass;
 482
 483 #define RET(x) do {                  \
 484    if (data)                         \
 485       memcpy(data, x, sizeof(x));    \
 486    return sizeof(x);                 \
 487 } while (0)
 488
 489    switch (param) {
 490    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 491       RET((uint64_t []) { 3 });
 492    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 493       if (obj_class >= NVE4_COMPUTE_CLASS) {
 494          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 495       } else {
 496          RET(((uint64_t []) { 65535, 65535, 65535 }));
 497       }
 498    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 499       RET(((uint64_t []) { 1024, 1024, 64 }));
 500    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 501       RET((uint64_t []) { 1024 });
 502    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 503       if (obj_class >= NVE4_COMPUTE_CLASS) {
 504          RET((uint64_t []) { 1024 });
 505       } else {
 506          RET((uint64_t []) { 512 });
 507       }
 508    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 509       RET((uint64_t []) { 1ULL << 40 });
 510    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 511       switch (obj_class) {
 512       case GM200_COMPUTE_CLASS:
 513          RET((uint64_t []) { 96 << 10 });
 514          break;
 515       case GM107_COMPUTE_CLASS:
 516          RET((uint64_t []) { 64 << 10 });
 517          break;
 518       default:
 519          RET((uint64_t []) { 48 << 10 });
 520          break;
 521       }
 522    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 523       RET((uint64_t []) { 512 << 10 });
 524    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 525       RET((uint64_t []) { 4096 });
 526    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 527       RET((uint32_t []) { 32 });
 528    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 529       RET((uint64_t []) { 1ULL << 40 });
 530    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 531       RET((uint32_t []) { 0 });
 532    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 533       RET((uint32_t []) { screen->mp_count_compute });
 534    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 535       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 536    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 537       RET((uint32_t []) { 64 });
 538    default:
 539       return 0;
 540    }
 541
 542 #undef RET
 543 }
 544
 545 static void
 546 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
 547                                   unsigned sample_count,
 548                                   unsigned *width, unsigned *height)
 549 {
 550    switch (sample_count) {
 551    case 0:
 552    case 1:
 553       /* this could be 4x4, but the GL state tracker makes it difficult to
 554        * create a 1x MSAA texture and smaller grids save CB space */
 555       *width = 2;
 556       *height = 4;
 557       break;
 558    case 2:
 559       *width = 2;
 560       *height = 4;
 561       break;
 562    case 4:
 563       *width = 2;
 564       *height = 2;
 565       break;
 566    case 8:
 567       *width = 1;
 568       *height = 2;
 569       break;
 570    default:
 571       assert(0);
 572    }
 573 }
 574
 575 static void
 576 nvc0_screen_destroy(struct pipe_screen *pscreen)
 577 {
 578    struct nvc0_screen *screen = nvc0_screen(pscreen);
 579
 580    if (!nouveau_drm_screen_unref(&screen->base))
 581       return;
 582
 583    if (screen->base.fence.current) {
 584       struct nouveau_fence *current = NULL;
 585
 586       /* nouveau_fence_wait will create a new current fence, so wait on the
 587        * _current_ one, and remove both.
 588        */
 589       nouveau_fence_ref(screen->base.fence.current, &current);
 590       nouveau_fence_wait(current, NULL);
 591       nouveau_fence_ref(NULL, &current);
 592       nouveau_fence_ref(NULL, &screen->base.fence.current);
 593    }
 594    if (screen->base.pushbuf)
 595       screen->base.pushbuf->user_priv = NULL;
 596
 597    if (screen->blitter)
 598       nvc0_blitter_destroy(screen);
 599    if (screen->pm.prog) {
 600       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 601       nvc0_program_destroy(NULL, screen->pm.prog);
 602       FREE(screen->pm.prog);
 603    }
 604
 605    nouveau_bo_ref(NULL, &screen->text);
 606    nouveau_bo_ref(NULL, &screen->uniform_bo);
 607    nouveau_bo_ref(NULL, &screen->tls);
 608    nouveau_bo_ref(NULL, &screen->txc);
 609    nouveau_bo_ref(NULL, &screen->fence.bo);
 610    nouveau_bo_ref(NULL, &screen->poly_cache);
 611
 612    nouveau_heap_destroy(&screen->lib_code);
 613    nouveau_heap_destroy(&screen->text_heap);
 614
 615    FREE(screen->default_tsc);
 616    FREE(screen->tic.entries);
 617
 618    nouveau_object_del(&screen->eng3d);
 619    nouveau_object_del(&screen->eng2d);
 620    nouveau_object_del(&screen->m2mf);
 621    nouveau_object_del(&screen->compute);
 622    nouveau_object_del(&screen->nvsw);
 623
 624    nouveau_screen_fini(&screen->base);
 625
 626    FREE(screen);
 627 }
 628
 629 static int
 630 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 631                      unsigned size, const uint32_t *data)
 632 {
 633    struct nouveau_pushbuf *push = screen->base.pushbuf;
 634
 635    size /= 4;
 636
 637    assert((pos + size) <= 0x800);
 638
 639    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 640    PUSH_DATA (push, (m - 0x3800) / 8);
 641    PUSH_DATA (push, pos);
 642    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 643    PUSH_DATA (push, pos);
 644    PUSH_DATAp(push, data, size);
 645
 646    return pos + size;
 647 }
 648
 649 static void
 650 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 651 {
 652    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 653    PUSH_DATA (push, 0xff);
 654    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 655    PUSH_DATA (push, 0xff);
 656    PUSH_DATA (push, 0xff);
 657    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 658    PUSH_DATA (push, 0xff);
 659    PUSH_DATA (push, 0xff);
 660    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 661    PUSH_DATA (push, 0x3f);
 662
 663    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 664    PUSH_DATA (push, (3 << 16) | 3);
 665    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 666    PUSH_DATA (push, (2 << 16) | 2);
 667
 668    if (obj_class < GM107_3D_CLASS) {
 669       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 670       PUSH_DATA (push, 0);
 671    }
 672    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 673    PUSH_DATA (push, 0x10);
 674    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 675    PUSH_DATA (push, 0x10);
 676    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 677    PUSH_DATA (push, 0x10);
 678    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 679    PUSH_DATA (push, 0x10);
 680    PUSH_DATA (push, 0x10);
 681    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 682    PUSH_DATA (push, 0x10);
 683    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 684    PUSH_DATA (push, 0xe);
 685
 686    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 687    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 688    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 689    PUSH_DATA (push, 0);
 690    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 691    PUSH_DATA (push, 3);
 692
 693    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 694    PUSH_DATA (push, 0x3fffff);
 695    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 696    PUSH_DATA (push, 1);
 697    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 698    PUSH_DATA (push, 1);
 699
 700    if (obj_class < GM107_3D_CLASS) {
 701       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 702       PUSH_DATA (push, 3);
 703
 704       if (obj_class >= NVE4_3D_CLASS) {
 705          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 706          PUSH_DATA (push, 1);
 707       }
 708    }
 709
 710    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 711     * are supposed to do */
 712 }
 713
 714 static void
 715 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 716 {
 717    struct nvc0_screen *screen = nvc0_screen(pscreen);
 718    struct nouveau_pushbuf *push = screen->base.pushbuf;
 719
 720    /* we need to do it after possible flush in MARK_RING */
 721    *sequence = ++screen->base.fence.sequence;
 722
 723    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 724    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 725    PUSH_DATAh(push, screen->fence.bo->offset);
 726    PUSH_DATA (push, screen->fence.bo->offset);
 727    PUSH_DATA (push, *sequence);
 728    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 729               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 730 }
 731
 732 static u32
 733 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 734 {
 735    struct nvc0_screen *screen = nvc0_screen(pscreen);
 736    return screen->fence.map[0];
 737 }
 738
 739 static int
 740 nvc0_screen_init_compute(struct nvc0_screen *screen)
 741 {
 742    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 743
 744    switch (screen->base.device->chipset & ~0xf) {
 745    case 0xc0:
 746    case 0xd0:
 747       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 748    case 0xe0:
 749    case 0xf0:
 750    case 0x100:
 751    case 0x110:
 752    case 0x120:
 753    case 0x130:
 754       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 755    default:
 756       return -1;
 757    }
 758 }
 759
 760 static int
 761 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 762                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 763 {
 764    struct nouveau_bo *bo = NULL;
 765    int ret;
 766    uint64_t size = (lpos + lneg) * 32 + cstack;
 767
 768    if (size >= (1 << 20)) {
 769       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 770       return -1;
 771    }
 772
 773    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 774    size  = align(size, 0x8000);
 775    size *= screen->mp_count;
 776
 777    size = align(size, 1 << 17);
 778
 779    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 780                         NULL, &bo);
 781    if (ret)
 782       return ret;
 783
 784    /* Make sure that the pushbuf has acquired a reference to the old tls
 785     * segment, as it may have commands that will reference it.
 786     */
 787    if (screen->tls)
 788       PUSH_REFN(screen->base.pushbuf, screen->tls,
 789                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
 790    nouveau_bo_ref(NULL, &screen->tls);
 791    screen->tls = bo;
 792    return 0;
 793 }
 794
 795 int
 796 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 797 {
 798    struct nouveau_pushbuf *push = screen->base.pushbuf;
 799    struct nouveau_bo *bo;
 800    int ret;
 801
 802    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 803                         1 << 17, size, NULL, &bo);
 804    if (ret)
 805       return ret;
 806
 807    /* Make sure that the pushbuf has acquired a reference to the old text
 808     * segment, as it may have commands that will reference it.
 809     */
 810    if (screen->text)
 811       PUSH_REFN(push, screen->text,
 812                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
 813    nouveau_bo_ref(NULL, &screen->text);
 814    screen->text = bo;
 815
 816    nouveau_heap_destroy(&screen->lib_code);
 817    nouveau_heap_destroy(&screen->text_heap);
 818
 819    /* XXX: getting a page fault at the end of the code buffer every few
 820     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 821     */
 822    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 823
 824    /* update the code segment setup */
 825    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 826    PUSH_DATAh(push, screen->text->offset);
 827    PUSH_DATA (push, screen->text->offset);
 828    if (screen->compute) {
 829       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 830       PUSH_DATAh(push, screen->text->offset);
 831       PUSH_DATA (push, screen->text->offset);
 832    }
 833
 834    return 0;
 835 }
 836
 837 void
 838 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
 839                        int stage, int index, int size, uint64_t addr)
 840 {
 841    assert(stage != 5);
 842
 843    struct nouveau_pushbuf *push = screen->base.pushbuf;
 844
 845    if (screen->base.class_3d >= GM107_3D_CLASS) {
 846       struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
 847
 848       // TODO: Better figure out the conditions in which this is needed
 849       bool serialize = binding->addr == addr && binding->size != size;
 850       if (can_serialize)
 851          serialize = serialize && *can_serialize;
 852       if (serialize) {
 853          IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 854          if (can_serialize)
 855             *can_serialize = false;
 856       }
 857
 858       binding->addr = addr;
 859       binding->size = size;
 860    }
 861
 862    if (size >= 0) {
 863       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 864       PUSH_DATA (push, size);
 865       PUSH_DATAh(push, addr);
 866       PUSH_DATA (push, addr);
 867    }
 868    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
 869 }
 870
 871 #define FAIL_SCREEN_INIT(str, err)                    \
 872    do {                                               \
 873       NOUVEAU_ERR(str, err);                          \
 874       goto fail;                                      \
 875    } while(0)
 876
 877 struct nouveau_screen *
 878 nvc0_screen_create(struct nouveau_device *dev)
 879 {
 880    struct nvc0_screen *screen;
 881    struct pipe_screen *pscreen;
 882    struct nouveau_object *chan;
 883    struct nouveau_pushbuf *push;
 884    uint64_t value;
 885    uint32_t obj_class;
 886    uint32_t flags;
 887    int ret;
 888    unsigned i;
 889
 890    switch (dev->chipset & ~0xf) {
 891    case 0xc0:
 892    case 0xd0:
 893    case 0xe0:
 894    case 0xf0:
 895    case 0x100:
 896    case 0x110:
 897    case 0x120:
 898    case 0x130:
 899       break;
 900    default:
 901       return NULL;
 902    }
 903
 904    screen = CALLOC_STRUCT(nvc0_screen);
 905    if (!screen)
 906       return NULL;
 907    pscreen = &screen->base.base;
 908    pscreen->destroy = nvc0_screen_destroy;
 909
 910    ret = nouveau_screen_init(&screen->base, dev);
 911    if (ret)
 912       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 913    chan = screen->base.channel;
 914    push = screen->base.pushbuf;
 915    push->user_priv = screen;
 916    push->rsvd_kick = 5;
 917
 918    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 919       PIPE_BIND_SHADER_BUFFER |
 920       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 921       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 922    screen->base.sysmem_bindings |=
 923       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 924
 925    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 926       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 927       screen->base.vidmem_bindings = 0;
 928    }
 929
 930    pscreen->context_create = nvc0_create;
 931    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 932    pscreen->get_param = nvc0_screen_get_param;
 933    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 934    pscreen->get_paramf = nvc0_screen_get_paramf;
 935    pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
 936    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 937    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 938
 939    nvc0_screen_init_resource_functions(pscreen);
 940
 941    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 942    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 943
 944    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 945    if (screen->base.drm->version >= 0x01000202)
 946       flags |= NOUVEAU_BO_COHERENT;
 947
 948    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 949    if (ret)
 950       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 951    nouveau_bo_map(screen->fence.bo, 0, NULL);
 952    screen->fence.map = screen->fence.bo->map;
 953    screen->base.fence.emit = nvc0_screen_fence_emit;
 954    screen->base.fence.update = nvc0_screen_fence_update;
 955
 956
 957    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 958                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 959    if (ret)
 960       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 961
 962    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 963    PUSH_DATA (push, screen->nvsw->handle);
 964
 965    switch (dev->chipset & ~0xf) {
 966    case 0x130:
 967    case 0x120:
 968    case 0x110:
 969    case 0x100:
 970    case 0xf0:
 971       obj_class = NVF0_P2MF_CLASS;
 972       break;
 973    case 0xe0:
 974       obj_class = NVE4_P2MF_CLASS;
 975       break;
 976    default:
 977       obj_class = NVC0_M2MF_CLASS;
 978       break;
 979    }
 980    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 981                             &screen->m2mf);
 982    if (ret)
 983       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 984
 985    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 986    PUSH_DATA (push, screen->m2mf->oclass);
 987    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 988       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 989       PUSH_DATA (push, 0xa0b5);
 990    }
 991
 992    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 993                             &screen->eng2d);
 994    if (ret)
 995       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 996
 997    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 998    PUSH_DATA (push, screen->eng2d->oclass);
 999    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1000    PUSH_DATA (push, 0);
1001    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1002    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1003    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1004    PUSH_DATA (push, 0);
1005    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1006    PUSH_DATA (push, 0);
1007    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1008    PUSH_DATA (push, 0x3f);
1009    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1010    PUSH_DATA (push, 1);
1011    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1012    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1013
1014    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1015    PUSH_DATAh(push, screen->fence.bo->offset + 16);
1016    PUSH_DATA (push, screen->fence.bo->offset + 16);
1017
1018    switch (dev->chipset & ~0xf) {
1019    case 0x130:
1020       switch (dev->chipset) {
1021       case 0x130:
1022       case 0x13b:
1023          obj_class = GP100_3D_CLASS;
1024          break;
1025       default:
1026          obj_class = GP102_3D_CLASS;
1027          break;
1028       }
1029       break;
1030    case 0x120:
1031       obj_class = GM200_3D_CLASS;
1032       break;
1033    case 0x110:
1034       obj_class = GM107_3D_CLASS;
1035       break;
1036    case 0x100:
1037    case 0xf0:
1038       obj_class = NVF0_3D_CLASS;
1039       break;
1040    case 0xe0:
1041       switch (dev->chipset) {
1042       case 0xea:
1043          obj_class = NVEA_3D_CLASS;
1044          break;
1045       default:
1046          obj_class = NVE4_3D_CLASS;
1047          break;
1048       }
1049       break;
1050    case 0xd0:
1051       obj_class = NVC8_3D_CLASS;
1052       break;
1053    case 0xc0:
1054    default:
1055       switch (dev->chipset) {
1056       case 0xc8:
1057          obj_class = NVC8_3D_CLASS;
1058          break;
1059       case 0xc1:
1060          obj_class = NVC1_3D_CLASS;
1061          break;
1062       default:
1063          obj_class = NVC0_3D_CLASS;
1064          break;
1065       }
1066       break;
1067    }
1068    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1069                             &screen->eng3d);
1070    if (ret)
1071       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1072    screen->base.class_3d = obj_class;
1073
1074    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1075    PUSH_DATA (push, screen->eng3d->oclass);
1076
1077    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1078    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1079
1080    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1081       /* kill shaders after about 1 second (at 100 MHz) */
1082       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1083       PUSH_DATA (push, 0x17);
1084    }
1085
1086    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1087                     screen->base.drm->version >= 0x01000101);
1088    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1089    for (i = 0; i < 8; ++i)
1090       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1091
1092    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1093    PUSH_DATA (push, 1);
1094
1095    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1096    PUSH_DATA (push, 0);
1097    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1098    PUSH_DATA (push, 0);
1099    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1100    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1101    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1102    PUSH_DATA (push, 0);
1103    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1104    PUSH_DATA (push, 1);
1105    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1106    PUSH_DATA (push, 1);
1107    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1108    PUSH_DATA (push, 1);
1109    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1110    PUSH_DATA (push, 0);
1111    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1112    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1113    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1114       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1115    } else {
1116       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1117       PUSH_DATA (push, 15);
1118    }
1119    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1120    PUSH_DATA (push, 8); /* 128 */
1121    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1122    PUSH_DATA (push, 1);
1123    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1124       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1125       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1126    }
1127
1128    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1129
1130    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1131    if (ret)
1132       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1133
1134    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1135    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1136                         &screen->uniform_bo);
1137    if (ret)
1138       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1139
1140    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1141
1142    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1143    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1144    PUSH_DATA (push, 256);
1145    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1146    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1147    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1148    PUSH_DATA (push, 0);
1149    PUSH_DATAf(push, 0.0f);
1150    PUSH_DATAf(push, 0.0f);
1151    PUSH_DATAf(push, 0.0f);
1152    PUSH_DATAf(push, 0.0f);
1153    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1154    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1155    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1156
1157    if (screen->base.drm->version >= 0x01000101) {
1158       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1159       if (ret)
1160          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1161    } else {
1162       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1163          value = (8 << 8) | 4;
1164       else
1165          value = (16 << 8) | 4;
1166    }
1167    screen->gpc_count = value & 0x000000ff;
1168    screen->mp_count = value >> 8;
1169    screen->mp_count_compute = screen->mp_count;
1170
1171    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1172    if (ret)
1173       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1174
1175    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1176    PUSH_DATAh(push, screen->tls->offset);
1177    PUSH_DATA (push, screen->tls->offset);
1178    PUSH_DATA (push, screen->tls->size >> 32);
1179    PUSH_DATA (push, screen->tls->size);
1180    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1181    PUSH_DATA (push, 0);
1182    /* Reduce likelihood of collision with real buffers by placing the hole at
1183     * the top of the 4G area. This will have to be dealt with for real
1184     * eventually by blocking off that area from the VM.
1185     */
1186    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1187    PUSH_DATA (push, 0xff << 24);
1188
1189    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1190       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1191                            &screen->poly_cache);
1192       if (ret)
1193          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1194
1195       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1196       PUSH_DATAh(push, screen->poly_cache->offset);
1197       PUSH_DATA (push, screen->poly_cache->offset);
1198       PUSH_DATA (push, 3);
1199    }
1200
1201    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1202                         &screen->txc);
1203    if (ret)
1204       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1205
1206    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1207    PUSH_DATAh(push, screen->txc->offset);
1208    PUSH_DATA (push, screen->txc->offset);
1209    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1210    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1211       screen->tic.maxwell = true;
1212       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1213          screen->tic.maxwell =
1214             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1215          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1216       }
1217    }
1218
1219    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1220    PUSH_DATAh(push, screen->txc->offset + 65536);
1221    PUSH_DATA (push, screen->txc->offset + 65536);
1222    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1223
1224    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1225    PUSH_DATA (push, 0);
1226    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1227    PUSH_DATA (push, 0);
1228    PUSH_DATA (push, 0);
1229    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1230    PUSH_DATA (push, 0x3f);
1231
1232    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1233    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1234    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1235    for (i = 0; i < 8 * 2; ++i)
1236       PUSH_DATA(push, 0);
1237    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1238    PUSH_DATA (push, 0);
1239    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1240    PUSH_DATA (push, 0);
1241
1242    /* neither scissors, viewport nor stencil mask should affect clears */
1243    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1244    PUSH_DATA (push, 0);
1245
1246    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1247    PUSH_DATA (push, 1);
1248    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1249       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1250       PUSH_DATAf(push, 0.0f);
1251       PUSH_DATAf(push, 1.0f);
1252    }
1253    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1254    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1255
1256    /* We use scissors instead of exact view volume clipping,
1257     * so they're always enabled.
1258     */
1259    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1260       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1261       PUSH_DATA (push, 1);
1262       PUSH_DATA (push, 8192 << 16);
1263       PUSH_DATA (push, 8192 << 16);
1264    }
1265
1266 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1267
1268    i = 0;
1269    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1270    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1271    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1272    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1273    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1274    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1275    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1276    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1277    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1278    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1279    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1280    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1281    MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1282    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1283
1284    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1285    PUSH_DATA (push, 1);
1286    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1287    PUSH_DATA (push, 1);
1288    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1289    PUSH_DATA (push, 0x40);
1290    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1291    PUSH_DATA (push, 0);
1292    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1293    PUSH_DATA (push, 0x30);
1294    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1295    PUSH_DATA (push, 3);
1296    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1297    PUSH_DATA (push, 0x20);
1298    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1299    PUSH_DATA (push, 0x00);
1300    screen->save_state.patch_vertices = 3;
1301
1302    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1303    PUSH_DATA (push, 0);
1304    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1305    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1306
1307    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1308
1309    if (nvc0_screen_init_compute(screen))
1310       goto fail;
1311
1312    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1313    for (i = 0; i < 5; ++i) {
1314       unsigned j = 0;
1315       for (j = 0; j < 16; j++)
1316          screen->cb_bindings[i][j].size = -1;
1317
1318       /* TIC and TSC entries for each unit (nve4+ only) */
1319       /* auxiliary constants (6 user clip planes, base instance id) */
1320       nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1321                              screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1322       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1323          unsigned j;
1324          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1325          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1326          for (j = 0; j < 8; ++j)
1327             PUSH_DATA(push, j);
1328       } else {
1329          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1330          PUSH_DATA (push, 0x54);
1331       }
1332
1333       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1334       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1335       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1336       PUSH_DATA (push, 0); /* 0 */
1337       PUSH_DATA (push, 0);
1338       PUSH_DATA (push, 1); /* 1 */
1339       PUSH_DATA (push, 0);
1340       PUSH_DATA (push, 0); /* 2 */
1341       PUSH_DATA (push, 1);
1342       PUSH_DATA (push, 1); /* 3 */
1343       PUSH_DATA (push, 1);
1344       PUSH_DATA (push, 2); /* 4 */
1345       PUSH_DATA (push, 0);
1346       PUSH_DATA (push, 3); /* 5 */
1347       PUSH_DATA (push, 0);
1348       PUSH_DATA (push, 2); /* 6 */
1349       PUSH_DATA (push, 1);
1350       PUSH_DATA (push, 3); /* 7 */
1351       PUSH_DATA (push, 1);
1352    }
1353    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1354    PUSH_DATA (push, 0);
1355
1356    PUSH_KICK (push);
1357
1358    screen->tic.entries = CALLOC(
1359          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1360          sizeof(void *));
1361    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1362    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1363
1364    if (!nvc0_blitter_create(screen))
1365       goto fail;
1366
1367    screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1368    screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1369
1370    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1371
1372    return &screen->base;
1373
1374 fail:
1375    screen->base.base.context_create = NULL;
1376    return &screen->base;
1377 }
1378
1379 int
1380 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1381 {
1382    int i = screen->tic.next;
1383
1384    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1385       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1386
1387    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1388
1389    if (screen->tic.entries[i])
1390       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1391
1392    screen->tic.entries[i] = entry;
1393    return i;
1394 }
1395
1396 int
1397 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1398 {
1399    int i = screen->tsc.next;
1400
1401    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1402       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1403
1404    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1405
1406    if (screen->tsc.entries[i])
1407       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1408
1409    screen->tsc.entries[i] = entry;
1410    return i;
1411 }