src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/mme/com9097.mme.h"
  36
  37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  39 #endif
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    if (sample_count > 8)
  49       return FALSE;
  50    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  51       return FALSE;
  52
  53    if (!util_format_is_supported(format, bindings))
  54       return FALSE;
  55
  56    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  57       if (util_format_get_blocksizebits(format) == 3 * 32)
  58          return FALSE;
  59
  60    /* transfers & shared are always supported */
  61    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  62                  PIPE_BIND_TRANSFER_WRITE |
  63                  PIPE_BIND_SHARED);
  64
  65    return (nvc0_format_table[format].usage & bindings) == bindings;
  66 }
  67
  68 static int
  69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  70 {
  71    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  72
  73    switch (param) {
  74    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  75    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  76       return 15;
  77    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  78       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  79    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  80       return 2048;
  81    case PIPE_CAP_MIN_TEXEL_OFFSET:
  82       return -8;
  83    case PIPE_CAP_MAX_TEXEL_OFFSET:
  84       return 7;
  85    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  86       return -32;
  87    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
  88       return 31;
  89    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  90    case PIPE_CAP_TEXTURE_SWIZZLE:
  91    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  92    case PIPE_CAP_NPOT_TEXTURES:
  93    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  94    case PIPE_CAP_ANISOTROPIC_FILTER:
  95    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  96    case PIPE_CAP_CUBE_MAP_ARRAY:
  97    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  98    case PIPE_CAP_TEXTURE_MULTISAMPLE:
  99       return 1;
 100    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 101       return 65536;
 102    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 103       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 104    case PIPE_CAP_TWO_SIDED_STENCIL:
 105    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 106    case PIPE_CAP_POINT_SPRITE:
 107    case PIPE_CAP_TGSI_TEXCOORD:
 108       return 1;
 109    case PIPE_CAP_SM3:
 110       return 1;
 111    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 112       return 330;
 113    case PIPE_CAP_MAX_RENDER_TARGETS:
 114       return 8;
 115    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 116       return 1;
 117    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 118    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 119    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 120       return 1;
 121    case PIPE_CAP_QUERY_TIMESTAMP:
 122    case PIPE_CAP_QUERY_TIME_ELAPSED:
 123    case PIPE_CAP_OCCLUSION_QUERY:
 124    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 125    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 126       return 1;
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 128       return 4;
 129    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 130    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 131       return 128;
 132    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 133    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 134       return 1024;
 135    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 136    case PIPE_CAP_INDEP_BLEND_ENABLE:
 137    case PIPE_CAP_INDEP_BLEND_FUNC:
 138       return 1;
 139    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 140    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 141       return 1;
 142    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 143    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 144       return 0;
 145    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 146       return 0;
 147    case PIPE_CAP_PRIMITIVE_RESTART:
 148    case PIPE_CAP_TGSI_INSTANCEID:
 149    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 150    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 151    case PIPE_CAP_CONDITIONAL_RENDER:
 152    case PIPE_CAP_TEXTURE_BARRIER:
 153    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 154    case PIPE_CAP_START_INSTANCE:
 155    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 156       return 1;
 157    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 158       return 0; /* state trackers will know better */
 159    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 160    case PIPE_CAP_USER_INDEX_BUFFERS:
 161    case PIPE_CAP_USER_VERTEX_BUFFERS:
 162       return 1;
 163    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 164       return 256;
 165    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 166       return 1; /* 256 for binding as RT, but that's not possible in GL */
 167    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 168       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 169    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 170    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 171    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 172       return 0;
 173    case PIPE_CAP_COMPUTE:
 174       return (class_3d == NVE4_3D_CLASS) ? 1 : 0;
 175    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 176       return 1;
 177    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 178       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 179    case PIPE_CAP_ENDIANNESS:
 180       return PIPE_ENDIAN_LITTLE;
 181    case PIPE_CAP_TGSI_VS_LAYER:
 182    case PIPE_CAP_TEXTURE_GATHER_SM5:
 183    case PIPE_CAP_FAKE_SW_MSAA:
 184       return 0;
 185    case PIPE_CAP_MAX_VIEWPORTS:
 186       return NVC0_MAX_VIEWPORTS;
 187    case PIPE_CAP_TEXTURE_QUERY_LOD:
 188    case PIPE_CAP_SAMPLE_SHADING:
 189    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 190       return 1;
 191    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 192       return 4;
 193    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 194       return 0;
 195    default:
 196       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 197       return 0;
 198    }
 199 }
 200
 201 static int
 202 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 203                              enum pipe_shader_cap param)
 204 {
 205    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 206
 207    switch (shader) {
 208    case PIPE_SHADER_VERTEX:
 209       /*
 210    case PIPE_SHADER_TESSELLATION_CONTROL:
 211    case PIPE_SHADER_TESSELLATION_EVALUATION:
 212       */
 213    case PIPE_SHADER_GEOMETRY:
 214    case PIPE_SHADER_FRAGMENT:
 215       break;
 216    case PIPE_SHADER_COMPUTE:
 217       if (class_3d != NVE4_3D_CLASS)
 218          return 0;
 219       break;
 220    default:
 221       return 0;
 222    }
 223
 224    switch (param) {
 225    case PIPE_SHADER_CAP_PREFERRED_IR:
 226       return PIPE_SHADER_IR_TGSI;
 227    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 228    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 229    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 230    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 231       return 16384;
 232    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 233       return 16;
 234    case PIPE_SHADER_CAP_MAX_INPUTS:
 235       if (shader == PIPE_SHADER_VERTEX)
 236          return 32;
 237       /* NOTE: These only count our slots for GENERIC varyings.
 238        * The address space may be larger, but the actual hard limit seems to be
 239        * less than what the address space layout permits, so don't add TEXCOORD,
 240        * COLOR, etc. here.
 241        */
 242       if (shader == PIPE_SHADER_FRAGMENT)
 243          return 0x1f0 / 16;
 244       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 245        * and excludes 0x60 per-patch inputs.
 246        */
 247       return 0x200 / 16;
 248    case PIPE_SHADER_CAP_MAX_CONSTS:
 249       return 65536 / 16;
 250    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 251       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 252          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 253       return NVC0_MAX_PIPE_CONSTBUFS;
 254    case PIPE_SHADER_CAP_MAX_ADDRS:
 255       return 1;
 256    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 257    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 258       return shader != PIPE_SHADER_FRAGMENT;
 259    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 260    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 261       return 1;
 262    case PIPE_SHADER_CAP_MAX_PREDS:
 263       return 0;
 264    case PIPE_SHADER_CAP_MAX_TEMPS:
 265       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 266    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 267       return 1;
 268    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 269       return 0;
 270    case PIPE_SHADER_CAP_SUBROUTINES:
 271       return 1;
 272    case PIPE_SHADER_CAP_INTEGERS:
 273       return 1;
 274    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 275       return 16; /* would be 32 in linked (OpenGL-style) mode */
 276    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 277       return 16; /* XXX not sure if more are really safe */
 278    default:
 279       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 280       return 0;
 281    }
 282 }
 283
 284 static float
 285 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 286 {
 287    switch (param) {
 288    case PIPE_CAPF_MAX_LINE_WIDTH:
 289    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 290       return 10.0f;
 291    case PIPE_CAPF_MAX_POINT_WIDTH:
 292       return 63.0f;
 293    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 294       return 63.375f;
 295    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 296       return 16.0f;
 297    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 298       return 15.0f;
 299    case PIPE_CAPF_GUARD_BAND_LEFT:
 300    case PIPE_CAPF_GUARD_BAND_TOP:
 301       return 0.0f;
 302    case PIPE_CAPF_GUARD_BAND_RIGHT:
 303    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 304       return 0.0f; /* that or infinity */
 305    }
 306
 307    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 308    return 0.0f;
 309 }
 310
 311 static int
 312 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 313                               enum pipe_compute_cap param, void *data)
 314 {
 315    uint64_t *data64 = (uint64_t *)data;
 316    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
 317
 318    switch (param) {
 319    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 320       data64[0] = 3;
 321       return 8;
 322    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 323       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
 324       data64[1] = 65535;
 325       data64[2] = 65535;
 326       return 24;
 327    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 328       data64[0] = 1024;
 329       data64[1] = 1024;
 330       data64[2] = 64;
 331       return 24;
 332    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 333       data64[0] = 1024;
 334       return 8;
 335    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 336       data64[0] = (uint64_t)1 << 40;
 337       return 8;
 338    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 339       data64[0] = 48 << 10;
 340       return 8;
 341    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 342       data64[0] = 512 << 10;
 343       return 8;
 344    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 345       data64[0] = 4096;
 346       return 8;
 347    default:
 348       return 0;
 349    }
 350 }
 351
 352 static void
 353 nvc0_screen_destroy(struct pipe_screen *pscreen)
 354 {
 355    struct nvc0_screen *screen = nvc0_screen(pscreen);
 356
 357    if (!nouveau_drm_screen_unref(&screen->base))
 358       return;
 359
 360    if (screen->base.fence.current) {
 361       struct nouveau_fence *current = NULL;
 362
 363       /* nouveau_fence_wait will create a new current fence, so wait on the
 364        * _current_ one, and remove both.
 365        */
 366       nouveau_fence_ref(screen->base.fence.current, &current);
 367       nouveau_fence_wait(current);
 368       nouveau_fence_ref(NULL, &current);
 369       nouveau_fence_ref(NULL, &screen->base.fence.current);
 370    }
 371    if (screen->base.pushbuf)
 372       screen->base.pushbuf->user_priv = NULL;
 373
 374    if (screen->blitter)
 375       nvc0_blitter_destroy(screen);
 376    if (screen->pm.prog) {
 377       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 378       nvc0_program_destroy(NULL, screen->pm.prog);
 379    }
 380
 381    nouveau_bo_ref(NULL, &screen->text);
 382    nouveau_bo_ref(NULL, &screen->uniform_bo);
 383    nouveau_bo_ref(NULL, &screen->tls);
 384    nouveau_bo_ref(NULL, &screen->txc);
 385    nouveau_bo_ref(NULL, &screen->fence.bo);
 386    nouveau_bo_ref(NULL, &screen->poly_cache);
 387    nouveau_bo_ref(NULL, &screen->parm);
 388
 389    nouveau_heap_destroy(&screen->lib_code);
 390    nouveau_heap_destroy(&screen->text_heap);
 391
 392    FREE(screen->tic.entries);
 393
 394    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 395
 396    nouveau_object_del(&screen->eng3d);
 397    nouveau_object_del(&screen->eng2d);
 398    nouveau_object_del(&screen->m2mf);
 399    nouveau_object_del(&screen->compute);
 400    nouveau_object_del(&screen->nvsw);
 401
 402    nouveau_screen_fini(&screen->base);
 403
 404    FREE(screen);
 405 }
 406
 407 static int
 408 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 409                      unsigned size, const uint32_t *data)
 410 {
 411    struct nouveau_pushbuf *push = screen->base.pushbuf;
 412
 413    size /= 4;
 414
 415    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 416    PUSH_DATA (push, (m - 0x3800) / 8);
 417    PUSH_DATA (push, pos);
 418    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 419    PUSH_DATA (push, pos);
 420    PUSH_DATAp(push, data, size);
 421
 422    return pos + size;
 423 }
 424
 425 static void
 426 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 427 {
 428    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 429    PUSH_DATA (push, 0xff);
 430    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 431    PUSH_DATA (push, 0xff);
 432    PUSH_DATA (push, 0xff);
 433    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 434    PUSH_DATA (push, 0xff);
 435    PUSH_DATA (push, 0xff);
 436    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 437    PUSH_DATA (push, 0x3f);
 438
 439    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 440    PUSH_DATA (push, (3 << 16) | 3);
 441    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 442    PUSH_DATA (push, (2 << 16) | 2);
 443    BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
 444    PUSH_DATA (push, 1);
 445
 446    if (obj_class < GM107_3D_CLASS) {
 447       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 448       PUSH_DATA (push, 0);
 449    }
 450    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 451    PUSH_DATA (push, 0x10);
 452    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 453    PUSH_DATA (push, 0x10);
 454    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 455    PUSH_DATA (push, 0x10);
 456    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 457    PUSH_DATA (push, 0x10);
 458    PUSH_DATA (push, 0x10);
 459    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 460    PUSH_DATA (push, 0x10);
 461    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 462    PUSH_DATA (push, 0xe);
 463
 464    BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
 465    PUSH_DATA (push, 1 << 12);
 466    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 467    PUSH_DATA (push, 0);
 468    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 469    PUSH_DATA (push, 3);
 470
 471    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 472    PUSH_DATA (push, 0x3fffff);
 473    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 474    PUSH_DATA (push, 1);
 475    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 476    PUSH_DATA (push, 1);
 477
 478    if (obj_class < GM107_3D_CLASS) {
 479       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 480       PUSH_DATA (push, 3);
 481
 482       if (obj_class >= NVE4_3D_CLASS) {
 483          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 484          PUSH_DATA (push, 1);
 485       }
 486    }
 487
 488    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 489     * are supposed to do */
 490 }
 491
 492 static void
 493 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 494 {
 495    struct nvc0_screen *screen = nvc0_screen(pscreen);
 496    struct nouveau_pushbuf *push = screen->base.pushbuf;
 497
 498    /* we need to do it after possible flush in MARK_RING */
 499    *sequence = ++screen->base.fence.sequence;
 500
 501    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
 502    PUSH_DATAh(push, screen->fence.bo->offset);
 503    PUSH_DATA (push, screen->fence.bo->offset);
 504    PUSH_DATA (push, *sequence);
 505    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 506               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 507 }
 508
 509 static u32
 510 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 511 {
 512    struct nvc0_screen *screen = nvc0_screen(pscreen);
 513    return screen->fence.map[0];
 514 }
 515
 516 static int
 517 nvc0_screen_init_compute(struct nvc0_screen *screen)
 518 {
 519    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 520
 521    switch (screen->base.device->chipset & ~0xf) {
 522    case 0xc0:
 523    case 0xd0:
 524       /* Using COMPUTE has weird effects on 3D state, we need to
 525        * investigate this further before enabling it by default.
 526        */
 527       if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
 528          return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 529       return 0;
 530    case 0xe0:
 531       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 532    case 0xf0:
 533    case 0x100:
 534    case 0x110:
 535       return 0;
 536    default:
 537       return -1;
 538    }
 539 }
 540
 541 boolean
 542 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 543                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 544 {
 545    struct nouveau_bo *bo = NULL;
 546    int ret;
 547    uint64_t size = (lpos + lneg) * 32 + cstack;
 548
 549    if (size >= (1 << 20)) {
 550       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 551       return FALSE;
 552    }
 553
 554    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 555    size  = align(size, 0x8000);
 556    size *= screen->mp_count;
 557
 558    size = align(size, 1 << 17);
 559
 560    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
 561                         NULL, &bo);
 562    if (ret) {
 563       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 564       return FALSE;
 565    }
 566    nouveau_bo_ref(NULL, &screen->tls);
 567    screen->tls = bo;
 568    return TRUE;
 569 }
 570
 571 #define FAIL_SCREEN_INIT(str, err)                    \
 572    do {                                               \
 573       NOUVEAU_ERR(str, err);                          \
 574       nvc0_screen_destroy(pscreen);                   \
 575       return NULL;                                    \
 576    } while(0)
 577
 578 struct pipe_screen *
 579 nvc0_screen_create(struct nouveau_device *dev)
 580 {
 581    struct nvc0_screen *screen;
 582    struct pipe_screen *pscreen;
 583    struct nouveau_object *chan;
 584    struct nouveau_pushbuf *push;
 585    uint64_t value;
 586    uint32_t obj_class;
 587    int ret;
 588    unsigned i;
 589    union nouveau_bo_config mm_config;
 590
 591    switch (dev->chipset & ~0xf) {
 592    case 0xc0:
 593    case 0xd0:
 594    case 0xe0:
 595    case 0xf0:
 596    case 0x100:
 597    case 0x110:
 598       break;
 599    default:
 600       return NULL;
 601    }
 602
 603    screen = CALLOC_STRUCT(nvc0_screen);
 604    if (!screen)
 605       return NULL;
 606    pscreen = &screen->base.base;
 607
 608    ret = nouveau_screen_init(&screen->base, dev);
 609    if (ret) {
 610       nvc0_screen_destroy(pscreen);
 611       return NULL;
 612    }
 613    chan = screen->base.channel;
 614    push = screen->base.pushbuf;
 615    push->user_priv = screen;
 616    push->rsvd_kick = 5;
 617
 618    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 619       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 620    screen->base.sysmem_bindings |=
 621       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 622
 623    pscreen->destroy = nvc0_screen_destroy;
 624    pscreen->context_create = nvc0_create;
 625    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 626    pscreen->get_param = nvc0_screen_get_param;
 627    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 628    pscreen->get_paramf = nvc0_screen_get_paramf;
 629    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 630
 631    nvc0_screen_init_resource_functions(pscreen);
 632
 633    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 634    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 635
 636    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
 637                         &screen->fence.bo);
 638    if (ret)
 639       goto fail;
 640    nouveau_bo_map(screen->fence.bo, 0, NULL);
 641    screen->fence.map = screen->fence.bo->map;
 642    screen->base.fence.emit = nvc0_screen_fence_emit;
 643    screen->base.fence.update = nvc0_screen_fence_update;
 644
 645
 646    ret = nouveau_object_new(chan,
 647                             (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
 648                             NULL, 0, &screen->nvsw);
 649    if (ret)
 650       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 651
 652
 653    switch (dev->chipset & ~0xf) {
 654    case 0x110:
 655    case 0x100:
 656    case 0xf0:
 657       obj_class = NVF0_P2MF_CLASS;
 658       break;
 659    case 0xe0:
 660       obj_class = NVE4_P2MF_CLASS;
 661       break;
 662    default:
 663       obj_class = NVC0_M2MF_CLASS;
 664       break;
 665    }
 666    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 667                             &screen->m2mf);
 668    if (ret)
 669       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 670
 671    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 672    PUSH_DATA (push, screen->m2mf->oclass);
 673    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 674       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 675       PUSH_DATA (push, 0xa0b5);
 676    }
 677
 678    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 679                             &screen->eng2d);
 680    if (ret)
 681       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 682
 683    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 684    PUSH_DATA (push, screen->eng2d->oclass);
 685    BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
 686    PUSH_DATA (push, 0);
 687    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 688    PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
 689    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 690    PUSH_DATA (push, 0);
 691    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 692    PUSH_DATA (push, 0);
 693    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 694    PUSH_DATA (push, 0x3f);
 695    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 696    PUSH_DATA (push, 1);
 697    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 698    PUSH_DATA (push, NVC0_2D_COND_MODE_ALWAYS);
 699
 700    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 701    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 702    PUSH_DATA (push, screen->fence.bo->offset + 16);
 703
 704    switch (dev->chipset & ~0xf) {
 705    case 0x110:
 706       obj_class = GM107_3D_CLASS;
 707       break;
 708    case 0x100:
 709    case 0xf0:
 710       obj_class = NVF0_3D_CLASS;
 711       break;
 712    case 0xe0:
 713       switch (dev->chipset) {
 714       case 0xea:
 715          obj_class = NVEA_3D_CLASS;
 716          break;
 717       default:
 718          obj_class = NVE4_3D_CLASS;
 719          break;
 720       }
 721       break;
 722    case 0xd0:
 723       obj_class = NVC8_3D_CLASS;
 724       break;
 725    case 0xc0:
 726    default:
 727       switch (dev->chipset) {
 728       case 0xc8:
 729          obj_class = NVC8_3D_CLASS;
 730          break;
 731       case 0xc1:
 732          obj_class = NVC1_3D_CLASS;
 733          break;
 734       default:
 735          obj_class = NVC0_3D_CLASS;
 736          break;
 737       }
 738       break;
 739    }
 740    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 741                             &screen->eng3d);
 742    if (ret)
 743       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 744    screen->base.class_3d = obj_class;
 745
 746    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 747    PUSH_DATA (push, screen->eng3d->oclass);
 748
 749    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 750    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 751
 752    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 753       /* kill shaders after about 1 second (at 100 MHz) */
 754       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 755       PUSH_DATA (push, 0x17);
 756    }
 757
 758    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
 759    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 760    for (i = 0; i < 8; ++i)
 761            PUSH_DATA(push, dev->drm_version >= 0x01000101);
 762
 763    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 764    PUSH_DATA (push, 1);
 765
 766    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 767    PUSH_DATA (push, 0);
 768    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 769    PUSH_DATA (push, 0);
 770    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 771    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 772    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 773    PUSH_DATA (push, 0);
 774    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 775    PUSH_DATA (push, 1);
 776    BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
 777    PUSH_DATA (push, 0);
 778    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 779    PUSH_DATA (push, 1);
 780    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 781    PUSH_DATA (push, 0);
 782    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 783       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 784       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 785    } else {
 786       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 787       PUSH_DATA (push, 15);
 788    }
 789    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 790    PUSH_DATA (push, 8); /* 128 */
 791    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 792    PUSH_DATA (push, 1);
 793    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 794       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 795       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 796    }
 797
 798    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 799
 800    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 801                         &screen->text);
 802    if (ret)
 803       goto fail;
 804
 805    /* XXX: getting a page fault at the end of the code buffer every few
 806     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 807     */
 808    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 809
 810    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
 811                         &screen->uniform_bo);
 812    if (ret)
 813       goto fail;
 814
 815    PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 816
 817    for (i = 0; i < 5; ++i) {
 818       /* TIC and TSC entries for each unit (nve4+ only) */
 819       /* auxiliary constants (6 user clip planes, base instance id) */
 820       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 821       PUSH_DATA (push, 512);
 822       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 823       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 824       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 825       PUSH_DATA (push, (15 << 4) | 1);
 826       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 827          unsigned j;
 828          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 829          PUSH_DATA (push, 0);
 830          for (j = 0; j < 8; ++j)
 831             PUSH_DATA(push, j);
 832       } else {
 833          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 834          PUSH_DATA (push, 0x54);
 835       }
 836    }
 837    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 838    PUSH_DATA (push, 0);
 839
 840    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 841    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 842    PUSH_DATA (push, 256);
 843    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 844    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 845    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 846    PUSH_DATA (push, 0);
 847    PUSH_DATAf(push, 0.0f);
 848    PUSH_DATAf(push, 0.0f);
 849    PUSH_DATAf(push, 0.0f);
 850    PUSH_DATAf(push, 0.0f);
 851    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 852    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 853    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 854
 855    if (dev->drm_version >= 0x01000101) {
 856       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 857       if (ret) {
 858          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 859          goto fail;
 860       }
 861    } else {
 862       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 863          value = (8 << 8) | 4;
 864       else
 865          value = (16 << 8) | 4;
 866    }
 867    screen->mp_count = value >> 8;
 868    screen->mp_count_compute = screen->mp_count;
 869
 870    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 871
 872    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 873    PUSH_DATAh(push, screen->text->offset);
 874    PUSH_DATA (push, screen->text->offset);
 875    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 876    PUSH_DATAh(push, screen->tls->offset);
 877    PUSH_DATA (push, screen->tls->offset);
 878    PUSH_DATA (push, screen->tls->size >> 32);
 879    PUSH_DATA (push, screen->tls->size);
 880    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 881    PUSH_DATA (push, 0);
 882    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 883    PUSH_DATA (push, 0);
 884
 885    if (screen->eng3d->oclass < GM107_3D_CLASS) {
 886       ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 887                            &screen->poly_cache);
 888       if (ret)
 889          goto fail;
 890
 891       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 892       PUSH_DATAh(push, screen->poly_cache->offset);
 893       PUSH_DATA (push, screen->poly_cache->offset);
 894       PUSH_DATA (push, 3);
 895    }
 896
 897    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
 898                         &screen->txc);
 899    if (ret)
 900       goto fail;
 901
 902    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 903    PUSH_DATAh(push, screen->txc->offset);
 904    PUSH_DATA (push, screen->txc->offset);
 905    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 906
 907    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 908    PUSH_DATAh(push, screen->txc->offset + 65536);
 909    PUSH_DATA (push, screen->txc->offset + 65536);
 910    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 911
 912    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 913    PUSH_DATA (push, 0);
 914    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 915    PUSH_DATA (push, 0);
 916    PUSH_DATA (push, 0);
 917    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 918    PUSH_DATA (push, 0x3f);
 919
 920    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 921    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 922    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 923    for (i = 0; i < 8 * 2; ++i)
 924       PUSH_DATA(push, 0);
 925    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 926    PUSH_DATA (push, 0);
 927    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 928    PUSH_DATA (push, 0);
 929
 930    /* neither scissors, viewport nor stencil mask should affect clears */
 931    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 932    PUSH_DATA (push, 0);
 933
 934    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 935    PUSH_DATA (push, 1);
 936    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
 937       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
 938       PUSH_DATAf(push, 0.0f);
 939       PUSH_DATAf(push, 1.0f);
 940    }
 941    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 942    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 943
 944    /* We use scissors instead of exact view volume clipping,
 945     * so they're always enabled.
 946     */
 947    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
 948       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
 949       PUSH_DATA (push, 1);
 950       PUSH_DATA (push, 8192 << 16);
 951       PUSH_DATA (push, 8192 << 16);
 952    }
 953
 954 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 955
 956    i = 0;
 957    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
 958    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
 959    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
 960    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
 961    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
 962    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
 963    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
 964
 965    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
 966    PUSH_DATA (push, 1);
 967    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
 968    PUSH_DATA (push, 1);
 969    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 970    PUSH_DATA (push, 0x40);
 971    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
 972    PUSH_DATA (push, 0);
 973    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 974    PUSH_DATA (push, 0x30);
 975    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
 976    PUSH_DATA (push, 3);
 977    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
 978    PUSH_DATA (push, 0x20);
 979    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
 980    PUSH_DATA (push, 0x00);
 981
 982    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
 983    PUSH_DATA (push, 0);
 984    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
 985    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
 986
 987    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
 988
 989    if (nvc0_screen_init_compute(screen))
 990       goto fail;
 991
 992    PUSH_KICK (push);
 993
 994    screen->tic.entries = CALLOC(4096, sizeof(void *));
 995    screen->tsc.entries = screen->tic.entries + 2048;
 996
 997    mm_config.nvc0.tile_mode = 0;
 998    mm_config.nvc0.memtype = 0xfe0;
 999    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
1000
1001    if (!nvc0_blitter_create(screen))
1002       goto fail;
1003
1004    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
1005
1006    return pscreen;
1007
1008 fail:
1009    nvc0_screen_destroy(pscreen);
1010    return NULL;
1011 }
1012
1013 int
1014 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1015 {
1016    int i = screen->tic.next;
1017
1018    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1019       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1020
1021    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1022
1023    if (screen->tic.entries[i])
1024       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1025
1026    screen->tic.entries[i] = entry;
1027    return i;
1028 }
1029
1030 int
1031 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1032 {
1033    int i = screen->tsc.next;
1034
1035    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1036       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1037
1038    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1039
1040    if (screen->tsc.entries[i])
1041       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1042
1043    screen->tsc.entries[i] = entry;
1044    return i;
1045 }