src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/mme/com9097.mme.h"
  36 #include "nvc0/mme/com90c0.mme.h"
  37
  38 #include "nv50/g80_texture.xml.h"
  39
  40 static boolean
  41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  42                                 enum pipe_format format,
  43                                 enum pipe_texture_target target,
  44                                 unsigned sample_count,
  45                                 unsigned bindings)
  46 {
  47    const struct util_format_description *desc = util_format_description(format);
  48
  49    if (sample_count > 8)
  50       return false;
  51    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  52       return false;
  53
  54    /* Short-circuit the rest of the logic -- this is used by the state tracker
  55     * to determine valid MS levels in a no-attachments scenario.
  56     */
  57    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  58       return true;
  59
  60    if (!util_format_is_supported(format, bindings))
  61       return false;
  62
  63    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  64       if (util_format_get_blocksizebits(format) == 3 * 32)
  65          return false;
  66
  67    if (bindings & PIPE_BIND_LINEAR)
  68       if (util_format_is_depth_or_stencil(format) ||
  69           (target != PIPE_TEXTURE_1D &&
  70            target != PIPE_TEXTURE_2D &&
  71            target != PIPE_TEXTURE_RECT) ||
  72           sample_count > 1)
  73          return false;
  74
  75    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  76     */
  77    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  78         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  79        /* The claim is that this should work on GM107 but it doesn't. Need to
  80         * test further and figure out if it's a nouveau issue or a HW one.
  81        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  82         */
  83        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  84       return false;
  85
  86    /* shared is always supported */
  87    bindings &= ~(PIPE_BIND_LINEAR |
  88                  PIPE_BIND_SHARED);
  89
  90    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  91       if (sample_count > 1 &&
  92           nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
  93          /* MS images are currently unsupported on Maxwell because they have to
  94           * be handled explicitly. */
  95          return false;
  96       }
  97
  98       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  99           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
 100          /* This should work on Fermi, but for currently unknown reasons it
 101           * does not and results in breaking reads from pbos. */
 102          return false;
 103       }
 104    }
 105
 106    return (( nvc0_format_table[format].usage |
 107             nvc0_vertex_format[format].usage) & bindings) == bindings;
 108 }
 109
 110 static int
 111 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 112 {
 113    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 114    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 115
 116    switch (param) {
 117    /* non-boolean caps */
 118    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 119    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 120       return 15;
 121    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 122       return 12;
 123    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 124       return 2048;
 125    case PIPE_CAP_MIN_TEXEL_OFFSET:
 126       return -8;
 127    case PIPE_CAP_MAX_TEXEL_OFFSET:
 128       return 7;
 129    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 130       return -32;
 131    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 132       return 31;
 133    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 134       return 128 * 1024 * 1024;
 135    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 136       return 430;
 137    case PIPE_CAP_MAX_RENDER_TARGETS:
 138       return 8;
 139    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 140       return 1;
 141    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 142       return 4;
 143    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 145       return 128;
 146    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 147    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 148       return 1024;
 149    case PIPE_CAP_MAX_VERTEX_STREAMS:
 150       return 4;
 151    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 152       return 2048;
 153    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 154       return 256;
 155    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 156       if (class_3d < GM107_3D_CLASS)
 157          return 256; /* IMAGE bindings require alignment to 256 */
 158       return 16;
 159    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 160       return 16;
 161    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 162       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 163    case PIPE_CAP_MAX_VIEWPORTS:
 164       return NVC0_MAX_VIEWPORTS;
 165    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 166       return 4;
 167    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 168       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 169    case PIPE_CAP_ENDIANNESS:
 170       return PIPE_ENDIAN_LITTLE;
 171    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 172       return 30;
 173    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 174       return NVC0_MAX_WINDOW_RECTANGLES;
 175
 176    /* supported caps */
 177    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 178    case PIPE_CAP_TEXTURE_SWIZZLE:
 179    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 180    case PIPE_CAP_NPOT_TEXTURES:
 181    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 182    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 183    case PIPE_CAP_ANISOTROPIC_FILTER:
 184    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 185    case PIPE_CAP_CUBE_MAP_ARRAY:
 186    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 187    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 188    case PIPE_CAP_TWO_SIDED_STENCIL:
 189    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 190    case PIPE_CAP_POINT_SPRITE:
 191    case PIPE_CAP_TGSI_TEXCOORD:
 192    case PIPE_CAP_SM3:
 193    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 194    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 195    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 196    case PIPE_CAP_QUERY_TIMESTAMP:
 197    case PIPE_CAP_QUERY_TIME_ELAPSED:
 198    case PIPE_CAP_OCCLUSION_QUERY:
 199    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 200    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 201    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 202    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 203    case PIPE_CAP_INDEP_BLEND_ENABLE:
 204    case PIPE_CAP_INDEP_BLEND_FUNC:
 205    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 206    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 207    case PIPE_CAP_PRIMITIVE_RESTART:
 208    case PIPE_CAP_TGSI_INSTANCEID:
 209    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 210    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 211    case PIPE_CAP_CONDITIONAL_RENDER:
 212    case PIPE_CAP_TEXTURE_BARRIER:
 213    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 214    case PIPE_CAP_START_INSTANCE:
 215    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 216    case PIPE_CAP_DRAW_INDIRECT:
 217    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 218    case PIPE_CAP_USER_VERTEX_BUFFERS:
 219    case PIPE_CAP_TEXTURE_QUERY_LOD:
 220    case PIPE_CAP_SAMPLE_SHADING:
 221    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 222    case PIPE_CAP_TEXTURE_GATHER_SM5:
 223    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 224    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 225    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 226    case PIPE_CAP_CLIP_HALFZ:
 227    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 228    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 229    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 230    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 231    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 232    case PIPE_CAP_TGSI_TXQS:
 233    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 234    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 235    case PIPE_CAP_SHAREABLE_SHADERS:
 236    case PIPE_CAP_CLEAR_TEXTURE:
 237    case PIPE_CAP_DRAW_PARAMETERS:
 238    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 239    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 240    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 241    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 242    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 243    case PIPE_CAP_INVALIDATE_BUFFER:
 244    case PIPE_CAP_STRING_MARKER:
 245    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 246    case PIPE_CAP_CULL_DISTANCE:
 247    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 248    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 249    case PIPE_CAP_TGSI_VOTE:
 250    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 251    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 252    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 253    case PIPE_CAP_DOUBLES:
 254    case PIPE_CAP_INT64:
 255    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 256    case PIPE_CAP_TGSI_CLOCK:
 257    case PIPE_CAP_COMPUTE:
 258    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 259    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 260       return 1;
 261    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 262       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 263    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 264       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 265    case PIPE_CAP_TGSI_FS_FBFETCH:
 266       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 267    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 268    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 269    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 270    case PIPE_CAP_POST_DEPTH_COVERAGE:
 271       return class_3d >= GM200_3D_CLASS;
 272    case PIPE_CAP_TGSI_BALLOT:
 273       return class_3d >= NVE4_3D_CLASS;
 274
 275    /* unsupported caps */
 276    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 277    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 278    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 279    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 280    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 281    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 282    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 283    case PIPE_CAP_FAKE_SW_MSAA:
 284    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 285    case PIPE_CAP_VERTEXID_NOBASE:
 286    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 287    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 288    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 289    case PIPE_CAP_GENERATE_MIPMAP:
 290    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 291    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 292    case PIPE_CAP_QUERY_MEMORY_INFO:
 293    case PIPE_CAP_PCI_GROUP:
 294    case PIPE_CAP_PCI_BUS:
 295    case PIPE_CAP_PCI_DEVICE:
 296    case PIPE_CAP_PCI_FUNCTION:
 297    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 298    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 299    case PIPE_CAP_NATIVE_FENCE_FD:
 300    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 301    case PIPE_CAP_INT64_DIVMOD:
 302    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 303    case PIPE_CAP_BINDLESS_TEXTURE:
 304    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 305    case PIPE_CAP_QUERY_SO_OVERFLOW:
 306       return 0;
 307
 308    case PIPE_CAP_VENDOR_ID:
 309       return 0x10de;
 310    case PIPE_CAP_DEVICE_ID: {
 311       uint64_t device_id;
 312       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 313          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 314          return -1;
 315       }
 316       return device_id;
 317    }
 318    case PIPE_CAP_ACCELERATED:
 319       return 1;
 320    case PIPE_CAP_VIDEO_MEMORY:
 321       return dev->vram_size >> 20;
 322    case PIPE_CAP_UMA:
 323       return 0;
 324    }
 325
 326    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 327    return 0;
 328 }
 329
 330 static int
 331 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 332                              enum pipe_shader_type shader,
 333                              enum pipe_shader_cap param)
 334 {
 335    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 336
 337    switch (shader) {
 338    case PIPE_SHADER_VERTEX:
 339    case PIPE_SHADER_GEOMETRY:
 340    case PIPE_SHADER_FRAGMENT:
 341    case PIPE_SHADER_COMPUTE:
 342    case PIPE_SHADER_TESS_CTRL:
 343    case PIPE_SHADER_TESS_EVAL:
 344       break;
 345    default:
 346       return 0;
 347    }
 348
 349    switch (param) {
 350    case PIPE_SHADER_CAP_PREFERRED_IR:
 351       return PIPE_SHADER_IR_TGSI;
 352    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 353       return 1 << PIPE_SHADER_IR_TGSI;
 354    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 355    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 356    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 357    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 358       return 16384;
 359    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 360       return 16;
 361    case PIPE_SHADER_CAP_MAX_INPUTS:
 362       if (shader == PIPE_SHADER_VERTEX)
 363          return 32;
 364       /* NOTE: These only count our slots for GENERIC varyings.
 365        * The address space may be larger, but the actual hard limit seems to be
 366        * less than what the address space layout permits, so don't add TEXCOORD,
 367        * COLOR, etc. here.
 368        */
 369       if (shader == PIPE_SHADER_FRAGMENT)
 370          return 0x1f0 / 16;
 371       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 372        * and excludes 0x60 per-patch inputs.
 373        */
 374       return 0x200 / 16;
 375    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 376       return 32;
 377    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 378       return 65536;
 379    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 380       return NVC0_MAX_PIPE_CONSTBUFS;
 381    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 382       return shader != PIPE_SHADER_FRAGMENT;
 383    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 384    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 385    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 386       return 1;
 387    case PIPE_SHADER_CAP_MAX_TEMPS:
 388       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 389    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 390       return 1;
 391    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 392       return 1;
 393    case PIPE_SHADER_CAP_SUBROUTINES:
 394       return 1;
 395    case PIPE_SHADER_CAP_INTEGERS:
 396       return 1;
 397    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 398       return 1;
 399    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 400       return 1;
 401    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 402       return 1;
 403    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 404    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 405    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 406       return 0;
 407    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 408       return NVC0_MAX_BUFFERS;
 409    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 410       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 411    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 412       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 413    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 414       return 32;
 415    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 416       if (class_3d >= NVE4_3D_CLASS)
 417          return NVC0_MAX_IMAGES;
 418       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 419          return NVC0_MAX_IMAGES;
 420       return 0;
 421    default:
 422       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 423       return 0;
 424    }
 425 }
 426
 427 static float
 428 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 429 {
 430    switch (param) {
 431    case PIPE_CAPF_MAX_LINE_WIDTH:
 432    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 433       return 10.0f;
 434    case PIPE_CAPF_MAX_POINT_WIDTH:
 435       return 63.0f;
 436    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 437       return 63.375f;
 438    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 439       return 16.0f;
 440    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 441       return 15.0f;
 442    case PIPE_CAPF_GUARD_BAND_LEFT:
 443    case PIPE_CAPF_GUARD_BAND_TOP:
 444       return 0.0f;
 445    case PIPE_CAPF_GUARD_BAND_RIGHT:
 446    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 447       return 0.0f; /* that or infinity */
 448    }
 449
 450    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 451    return 0.0f;
 452 }
 453
 454 static int
 455 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 456                               enum pipe_shader_ir ir_type,
 457                               enum pipe_compute_cap param, void *data)
 458 {
 459    struct nvc0_screen *screen = nvc0_screen(pscreen);
 460    const uint16_t obj_class = screen->compute->oclass;
 461
 462 #define RET(x) do {                  \
 463    if (data)                         \
 464       memcpy(data, x, sizeof(x));    \
 465    return sizeof(x);                 \
 466 } while (0)
 467
 468    switch (param) {
 469    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 470       RET((uint64_t []) { 3 });
 471    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 472       if (obj_class >= NVE4_COMPUTE_CLASS) {
 473          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 474       } else {
 475          RET(((uint64_t []) { 65535, 65535, 65535 }));
 476       }
 477    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 478       RET(((uint64_t []) { 1024, 1024, 64 }));
 479    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 480       RET((uint64_t []) { 1024 });
 481    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 482       if (obj_class >= NVE4_COMPUTE_CLASS) {
 483          RET((uint64_t []) { 1024 });
 484       } else {
 485          RET((uint64_t []) { 512 });
 486       }
 487    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 488       RET((uint64_t []) { 1ULL << 40 });
 489    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 490       switch (obj_class) {
 491       case GM200_COMPUTE_CLASS:
 492          RET((uint64_t []) { 96 << 10 });
 493          break;
 494       case GM107_COMPUTE_CLASS:
 495          RET((uint64_t []) { 64 << 10 });
 496          break;
 497       default:
 498          RET((uint64_t []) { 48 << 10 });
 499          break;
 500       }
 501    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 502       RET((uint64_t []) { 512 << 10 });
 503    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 504       RET((uint64_t []) { 4096 });
 505    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 506       RET((uint32_t []) { 32 });
 507    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 508       RET((uint64_t []) { 1ULL << 40 });
 509    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 510       RET((uint32_t []) { 0 });
 511    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 512       RET((uint32_t []) { screen->mp_count_compute });
 513    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 514       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 515    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 516       RET((uint32_t []) { 64 });
 517    default:
 518       return 0;
 519    }
 520
 521 #undef RET
 522 }
 523
 524 static void
 525 nvc0_screen_destroy(struct pipe_screen *pscreen)
 526 {
 527    struct nvc0_screen *screen = nvc0_screen(pscreen);
 528
 529    if (!nouveau_drm_screen_unref(&screen->base))
 530       return;
 531
 532    if (screen->base.fence.current) {
 533       struct nouveau_fence *current = NULL;
 534
 535       /* nouveau_fence_wait will create a new current fence, so wait on the
 536        * _current_ one, and remove both.
 537        */
 538       nouveau_fence_ref(screen->base.fence.current, &current);
 539       nouveau_fence_wait(current, NULL);
 540       nouveau_fence_ref(NULL, &current);
 541       nouveau_fence_ref(NULL, &screen->base.fence.current);
 542    }
 543    if (screen->base.pushbuf)
 544       screen->base.pushbuf->user_priv = NULL;
 545
 546    if (screen->blitter)
 547       nvc0_blitter_destroy(screen);
 548    if (screen->pm.prog) {
 549       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 550       nvc0_program_destroy(NULL, screen->pm.prog);
 551       FREE(screen->pm.prog);
 552    }
 553
 554    nouveau_bo_ref(NULL, &screen->text);
 555    nouveau_bo_ref(NULL, &screen->uniform_bo);
 556    nouveau_bo_ref(NULL, &screen->tls);
 557    nouveau_bo_ref(NULL, &screen->txc);
 558    nouveau_bo_ref(NULL, &screen->fence.bo);
 559    nouveau_bo_ref(NULL, &screen->poly_cache);
 560
 561    nouveau_heap_destroy(&screen->lib_code);
 562    nouveau_heap_destroy(&screen->text_heap);
 563
 564    FREE(screen->default_tsc);
 565    FREE(screen->tic.entries);
 566
 567    nouveau_object_del(&screen->eng3d);
 568    nouveau_object_del(&screen->eng2d);
 569    nouveau_object_del(&screen->m2mf);
 570    nouveau_object_del(&screen->compute);
 571    nouveau_object_del(&screen->nvsw);
 572
 573    nouveau_screen_fini(&screen->base);
 574
 575    FREE(screen);
 576 }
 577
 578 static int
 579 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 580                      unsigned size, const uint32_t *data)
 581 {
 582    struct nouveau_pushbuf *push = screen->base.pushbuf;
 583
 584    size /= 4;
 585
 586    assert((pos + size) <= 0x800);
 587
 588    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 589    PUSH_DATA (push, (m - 0x3800) / 8);
 590    PUSH_DATA (push, pos);
 591    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 592    PUSH_DATA (push, pos);
 593    PUSH_DATAp(push, data, size);
 594
 595    return pos + size;
 596 }
 597
 598 static void
 599 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 600 {
 601    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 602    PUSH_DATA (push, 0xff);
 603    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 604    PUSH_DATA (push, 0xff);
 605    PUSH_DATA (push, 0xff);
 606    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 607    PUSH_DATA (push, 0xff);
 608    PUSH_DATA (push, 0xff);
 609    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 610    PUSH_DATA (push, 0x3f);
 611
 612    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 613    PUSH_DATA (push, (3 << 16) | 3);
 614    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 615    PUSH_DATA (push, (2 << 16) | 2);
 616
 617    if (obj_class < GM107_3D_CLASS) {
 618       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 619       PUSH_DATA (push, 0);
 620    }
 621    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 622    PUSH_DATA (push, 0x10);
 623    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 624    PUSH_DATA (push, 0x10);
 625    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 626    PUSH_DATA (push, 0x10);
 627    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 628    PUSH_DATA (push, 0x10);
 629    PUSH_DATA (push, 0x10);
 630    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 631    PUSH_DATA (push, 0x10);
 632    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 633    PUSH_DATA (push, 0xe);
 634
 635    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 636    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 637    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 638    PUSH_DATA (push, 0);
 639    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 640    PUSH_DATA (push, 3);
 641
 642    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 643    PUSH_DATA (push, 0x3fffff);
 644    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 645    PUSH_DATA (push, 1);
 646    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 647    PUSH_DATA (push, 1);
 648
 649    if (obj_class < GM107_3D_CLASS) {
 650       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 651       PUSH_DATA (push, 3);
 652
 653       if (obj_class >= NVE4_3D_CLASS) {
 654          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 655          PUSH_DATA (push, 1);
 656       }
 657    }
 658
 659    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 660     * are supposed to do */
 661 }
 662
 663 static void
 664 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 665 {
 666    struct nvc0_screen *screen = nvc0_screen(pscreen);
 667    struct nouveau_pushbuf *push = screen->base.pushbuf;
 668
 669    /* we need to do it after possible flush in MARK_RING */
 670    *sequence = ++screen->base.fence.sequence;
 671
 672    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 673    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 674    PUSH_DATAh(push, screen->fence.bo->offset);
 675    PUSH_DATA (push, screen->fence.bo->offset);
 676    PUSH_DATA (push, *sequence);
 677    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 678               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 679 }
 680
 681 static u32
 682 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 683 {
 684    struct nvc0_screen *screen = nvc0_screen(pscreen);
 685    return screen->fence.map[0];
 686 }
 687
 688 static int
 689 nvc0_screen_init_compute(struct nvc0_screen *screen)
 690 {
 691    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 692
 693    switch (screen->base.device->chipset & ~0xf) {
 694    case 0xc0:
 695    case 0xd0:
 696       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 697    case 0xe0:
 698    case 0xf0:
 699    case 0x100:
 700    case 0x110:
 701    case 0x120:
 702    case 0x130:
 703       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 704    default:
 705       return -1;
 706    }
 707 }
 708
 709 static int
 710 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 711                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 712 {
 713    struct nouveau_bo *bo = NULL;
 714    int ret;
 715    uint64_t size = (lpos + lneg) * 32 + cstack;
 716
 717    if (size >= (1 << 20)) {
 718       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 719       return -1;
 720    }
 721
 722    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 723    size  = align(size, 0x8000);
 724    size *= screen->mp_count;
 725
 726    size = align(size, 1 << 17);
 727
 728    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 729                         NULL, &bo);
 730    if (ret)
 731       return ret;
 732    nouveau_bo_ref(NULL, &screen->tls);
 733    screen->tls = bo;
 734    return 0;
 735 }
 736
 737 int
 738 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 739 {
 740    struct nouveau_pushbuf *push = screen->base.pushbuf;
 741    struct nouveau_bo *bo;
 742    int ret;
 743
 744    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 745                         1 << 17, size, NULL, &bo);
 746    if (ret)
 747       return ret;
 748
 749    nouveau_bo_ref(NULL, &screen->text);
 750    screen->text = bo;
 751
 752    nouveau_heap_destroy(&screen->lib_code);
 753    nouveau_heap_destroy(&screen->text_heap);
 754
 755    /* XXX: getting a page fault at the end of the code buffer every few
 756     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 757     */
 758    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 759
 760    /* update the code segment setup */
 761    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 762    PUSH_DATAh(push, screen->text->offset);
 763    PUSH_DATA (push, screen->text->offset);
 764    if (screen->compute) {
 765       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 766       PUSH_DATAh(push, screen->text->offset);
 767       PUSH_DATA (push, screen->text->offset);
 768    }
 769
 770    return 0;
 771 }
 772
 773 #define FAIL_SCREEN_INIT(str, err)                    \
 774    do {                                               \
 775       NOUVEAU_ERR(str, err);                          \
 776       goto fail;                                      \
 777    } while(0)
 778
 779 struct nouveau_screen *
 780 nvc0_screen_create(struct nouveau_device *dev)
 781 {
 782    struct nvc0_screen *screen;
 783    struct pipe_screen *pscreen;
 784    struct nouveau_object *chan;
 785    struct nouveau_pushbuf *push;
 786    uint64_t value;
 787    uint32_t obj_class;
 788    uint32_t flags;
 789    int ret;
 790    unsigned i;
 791
 792    switch (dev->chipset & ~0xf) {
 793    case 0xc0:
 794    case 0xd0:
 795    case 0xe0:
 796    case 0xf0:
 797    case 0x100:
 798    case 0x110:
 799    case 0x120:
 800    case 0x130:
 801       break;
 802    default:
 803       return NULL;
 804    }
 805
 806    screen = CALLOC_STRUCT(nvc0_screen);
 807    if (!screen)
 808       return NULL;
 809    pscreen = &screen->base.base;
 810    pscreen->destroy = nvc0_screen_destroy;
 811
 812    ret = nouveau_screen_init(&screen->base, dev);
 813    if (ret)
 814       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 815    chan = screen->base.channel;
 816    push = screen->base.pushbuf;
 817    push->user_priv = screen;
 818    push->rsvd_kick = 5;
 819
 820    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 821       PIPE_BIND_SHADER_BUFFER |
 822       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 823       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 824    screen->base.sysmem_bindings |=
 825       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 826
 827    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 828       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 829       screen->base.vidmem_bindings = 0;
 830    }
 831
 832    pscreen->context_create = nvc0_create;
 833    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 834    pscreen->get_param = nvc0_screen_get_param;
 835    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 836    pscreen->get_paramf = nvc0_screen_get_paramf;
 837    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 838    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 839
 840    nvc0_screen_init_resource_functions(pscreen);
 841
 842    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 843    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 844
 845    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 846    if (screen->base.drm->version >= 0x01000202)
 847       flags |= NOUVEAU_BO_COHERENT;
 848
 849    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 850    if (ret)
 851       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 852    nouveau_bo_map(screen->fence.bo, 0, NULL);
 853    screen->fence.map = screen->fence.bo->map;
 854    screen->base.fence.emit = nvc0_screen_fence_emit;
 855    screen->base.fence.update = nvc0_screen_fence_update;
 856
 857
 858    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 859                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 860    if (ret)
 861       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 862
 863    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 864    PUSH_DATA (push, screen->nvsw->handle);
 865
 866    switch (dev->chipset & ~0xf) {
 867    case 0x130:
 868    case 0x120:
 869    case 0x110:
 870    case 0x100:
 871    case 0xf0:
 872       obj_class = NVF0_P2MF_CLASS;
 873       break;
 874    case 0xe0:
 875       obj_class = NVE4_P2MF_CLASS;
 876       break;
 877    default:
 878       obj_class = NVC0_M2MF_CLASS;
 879       break;
 880    }
 881    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 882                             &screen->m2mf);
 883    if (ret)
 884       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 885
 886    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 887    PUSH_DATA (push, screen->m2mf->oclass);
 888    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 889       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 890       PUSH_DATA (push, 0xa0b5);
 891    }
 892
 893    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 894                             &screen->eng2d);
 895    if (ret)
 896       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 897
 898    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 899    PUSH_DATA (push, screen->eng2d->oclass);
 900    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 901    PUSH_DATA (push, 0);
 902    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 903    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 904    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 905    PUSH_DATA (push, 0);
 906    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 907    PUSH_DATA (push, 0);
 908    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 909    PUSH_DATA (push, 0x3f);
 910    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 911    PUSH_DATA (push, 1);
 912    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 913    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 914
 915    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 916    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 917    PUSH_DATA (push, screen->fence.bo->offset + 16);
 918
 919    switch (dev->chipset & ~0xf) {
 920    case 0x130:
 921       switch (dev->chipset) {
 922       case 0x130:
 923       case 0x13b:
 924          obj_class = GP100_3D_CLASS;
 925          break;
 926       default:
 927          obj_class = GP102_3D_CLASS;
 928          break;
 929       }
 930       break;
 931    case 0x120:
 932       obj_class = GM200_3D_CLASS;
 933       break;
 934    case 0x110:
 935       obj_class = GM107_3D_CLASS;
 936       break;
 937    case 0x100:
 938    case 0xf0:
 939       obj_class = NVF0_3D_CLASS;
 940       break;
 941    case 0xe0:
 942       switch (dev->chipset) {
 943       case 0xea:
 944          obj_class = NVEA_3D_CLASS;
 945          break;
 946       default:
 947          obj_class = NVE4_3D_CLASS;
 948          break;
 949       }
 950       break;
 951    case 0xd0:
 952       obj_class = NVC8_3D_CLASS;
 953       break;
 954    case 0xc0:
 955    default:
 956       switch (dev->chipset) {
 957       case 0xc8:
 958          obj_class = NVC8_3D_CLASS;
 959          break;
 960       case 0xc1:
 961          obj_class = NVC1_3D_CLASS;
 962          break;
 963       default:
 964          obj_class = NVC0_3D_CLASS;
 965          break;
 966       }
 967       break;
 968    }
 969    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 970                             &screen->eng3d);
 971    if (ret)
 972       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 973    screen->base.class_3d = obj_class;
 974
 975    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 976    PUSH_DATA (push, screen->eng3d->oclass);
 977
 978    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 979    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 980
 981    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 982       /* kill shaders after about 1 second (at 100 MHz) */
 983       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 984       PUSH_DATA (push, 0x17);
 985    }
 986
 987    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 988                     screen->base.drm->version >= 0x01000101);
 989    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 990    for (i = 0; i < 8; ++i)
 991       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 992
 993    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 994    PUSH_DATA (push, 1);
 995
 996    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 997    PUSH_DATA (push, 0);
 998    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 999    PUSH_DATA (push, 0);
1000    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1001    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1002    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1003    PUSH_DATA (push, 0);
1004    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1005    PUSH_DATA (push, 1);
1006    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1007    PUSH_DATA (push, 1);
1008    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1009    PUSH_DATA (push, 1);
1010    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1011    PUSH_DATA (push, 0);
1012    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1013    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1014    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1015       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1016    } else {
1017       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1018       PUSH_DATA (push, 15);
1019    }
1020    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1021    PUSH_DATA (push, 8); /* 128 */
1022    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1023    PUSH_DATA (push, 1);
1024    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1025       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1026       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1027    }
1028
1029    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1030
1031    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1032    if (ret)
1033       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1034
1035    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1036                         &screen->uniform_bo);
1037    if (ret)
1038       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1039
1040    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1041
1042    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1043    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1044    PUSH_DATA (push, 256);
1045    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1046    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1047    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1048    PUSH_DATA (push, 0);
1049    PUSH_DATAf(push, 0.0f);
1050    PUSH_DATAf(push, 0.0f);
1051    PUSH_DATAf(push, 0.0f);
1052    PUSH_DATAf(push, 0.0f);
1053    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1054    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1055    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1056
1057    if (screen->base.drm->version >= 0x01000101) {
1058       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1059       if (ret)
1060          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1061    } else {
1062       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1063          value = (8 << 8) | 4;
1064       else
1065          value = (16 << 8) | 4;
1066    }
1067    screen->gpc_count = value & 0x000000ff;
1068    screen->mp_count = value >> 8;
1069    screen->mp_count_compute = screen->mp_count;
1070
1071    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1072    if (ret)
1073       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1074
1075    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1076    PUSH_DATAh(push, screen->tls->offset);
1077    PUSH_DATA (push, screen->tls->offset);
1078    PUSH_DATA (push, screen->tls->size >> 32);
1079    PUSH_DATA (push, screen->tls->size);
1080    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1081    PUSH_DATA (push, 0);
1082    /* Reduce likelihood of collision with real buffers by placing the hole at
1083     * the top of the 4G area. This will have to be dealt with for real
1084     * eventually by blocking off that area from the VM.
1085     */
1086    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1087    PUSH_DATA (push, 0xff << 24);
1088
1089    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1090       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1091                            &screen->poly_cache);
1092       if (ret)
1093          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1094
1095       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1096       PUSH_DATAh(push, screen->poly_cache->offset);
1097       PUSH_DATA (push, screen->poly_cache->offset);
1098       PUSH_DATA (push, 3);
1099    }
1100
1101    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1102                         &screen->txc);
1103    if (ret)
1104       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1105
1106    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1107    PUSH_DATAh(push, screen->txc->offset);
1108    PUSH_DATA (push, screen->txc->offset);
1109    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1110    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1111       screen->tic.maxwell = true;
1112       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1113          screen->tic.maxwell =
1114             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1115          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1116       }
1117    }
1118
1119    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1120    PUSH_DATAh(push, screen->txc->offset + 65536);
1121    PUSH_DATA (push, screen->txc->offset + 65536);
1122    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1123
1124    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1125    PUSH_DATA (push, 0);
1126    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1127    PUSH_DATA (push, 0);
1128    PUSH_DATA (push, 0);
1129    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1130    PUSH_DATA (push, 0x3f);
1131
1132    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1133    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1134    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1135    for (i = 0; i < 8 * 2; ++i)
1136       PUSH_DATA(push, 0);
1137    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1138    PUSH_DATA (push, 0);
1139    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1140    PUSH_DATA (push, 0);
1141
1142    /* neither scissors, viewport nor stencil mask should affect clears */
1143    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1144    PUSH_DATA (push, 0);
1145
1146    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1147    PUSH_DATA (push, 1);
1148    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1149       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1150       PUSH_DATAf(push, 0.0f);
1151       PUSH_DATAf(push, 1.0f);
1152    }
1153    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1154    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1155
1156    /* We use scissors instead of exact view volume clipping,
1157     * so they're always enabled.
1158     */
1159    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1160       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1161       PUSH_DATA (push, 1);
1162       PUSH_DATA (push, 8192 << 16);
1163       PUSH_DATA (push, 8192 << 16);
1164    }
1165
1166 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1167
1168    i = 0;
1169    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1170    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1171    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1172    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1173    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1174    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1175    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1176    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1177    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1178    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1179    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1180    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1181    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1182
1183    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1184    PUSH_DATA (push, 1);
1185    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1186    PUSH_DATA (push, 1);
1187    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1188    PUSH_DATA (push, 0x40);
1189    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1190    PUSH_DATA (push, 0);
1191    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1192    PUSH_DATA (push, 0x30);
1193    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1194    PUSH_DATA (push, 3);
1195    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1196    PUSH_DATA (push, 0x20);
1197    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1198    PUSH_DATA (push, 0x00);
1199    screen->save_state.patch_vertices = 3;
1200
1201    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1202    PUSH_DATA (push, 0);
1203    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1204    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1205
1206    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1207
1208    if (nvc0_screen_init_compute(screen))
1209       goto fail;
1210
1211    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1212    for (i = 0; i < 5; ++i) {
1213       /* TIC and TSC entries for each unit (nve4+ only) */
1214       /* auxiliary constants (6 user clip planes, base instance id) */
1215       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1216       PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1217       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1218       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1219       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1220       PUSH_DATA (push, (15 << 4) | 1);
1221       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1222          unsigned j;
1223          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1224          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1225          for (j = 0; j < 8; ++j)
1226             PUSH_DATA(push, j);
1227       } else {
1228          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1229          PUSH_DATA (push, 0x54);
1230       }
1231
1232       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1233       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1234       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1235       PUSH_DATA (push, 0); /* 0 */
1236       PUSH_DATA (push, 0);
1237       PUSH_DATA (push, 1); /* 1 */
1238       PUSH_DATA (push, 0);
1239       PUSH_DATA (push, 0); /* 2 */
1240       PUSH_DATA (push, 1);
1241       PUSH_DATA (push, 1); /* 3 */
1242       PUSH_DATA (push, 1);
1243       PUSH_DATA (push, 2); /* 4 */
1244       PUSH_DATA (push, 0);
1245       PUSH_DATA (push, 3); /* 5 */
1246       PUSH_DATA (push, 0);
1247       PUSH_DATA (push, 2); /* 6 */
1248       PUSH_DATA (push, 1);
1249       PUSH_DATA (push, 3); /* 7 */
1250       PUSH_DATA (push, 1);
1251    }
1252    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1253    PUSH_DATA (push, 0);
1254
1255    PUSH_KICK (push);
1256
1257    screen->tic.entries = CALLOC(4096, sizeof(void *));
1258    screen->tsc.entries = screen->tic.entries + 2048;
1259
1260    if (!nvc0_blitter_create(screen))
1261       goto fail;
1262
1263    screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1264    screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1265
1266    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1267
1268    return &screen->base;
1269
1270 fail:
1271    screen->base.base.context_create = NULL;
1272    return &screen->base;
1273 }
1274
1275 int
1276 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1277 {
1278    int i = screen->tic.next;
1279
1280    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1281       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1282
1283    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1284
1285    if (screen->tic.entries[i])
1286       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1287
1288    screen->tic.entries[i] = entry;
1289    return i;
1290 }
1291
1292 int
1293 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1294 {
1295    int i = screen->tsc.next;
1296
1297    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1298       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1299
1300    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1301
1302    if (screen->tsc.entries[i])
1303       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1304
1305    screen->tsc.entries[i] = entry;
1306    return i;
1307 }