src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    if (sample_count > 8)
  49       return false;
  50    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  51       return false;
  52
  53    if (!util_format_is_supported(format, bindings))
  54       return false;
  55
  56    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  57       if (util_format_get_blocksizebits(format) == 3 * 32)
  58          return false;
  59
  60    /* transfers & shared are always supported */
  61    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  62                  PIPE_BIND_TRANSFER_WRITE |
  63                  PIPE_BIND_SHARED);
  64
  65    return (( nvc0_format_table[format].usage |
  66             nvc0_vertex_format[format].usage) & bindings) == bindings;
  67 }
  68
  69 static int
  70 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  71 {
  72    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  73    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  74
  75    switch (param) {
  76    /* non-boolean caps */
  77    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  78    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  79       return 15;
  80    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  81       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  82    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  83       return 2048;
  84    case PIPE_CAP_MIN_TEXEL_OFFSET:
  85       return -8;
  86    case PIPE_CAP_MAX_TEXEL_OFFSET:
  87       return 7;
  88    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  89       return -32;
  90    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
  91       return 31;
  92    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  93       return 128 * 1024 * 1024;
  94    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  95       return 410;
  96    case PIPE_CAP_MAX_RENDER_TARGETS:
  97       return 8;
  98    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  99       return 1;
 100    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 101       return 4;
 102    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 103    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 104       return 128;
 105    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 106    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 107       return 1024;
 108    case PIPE_CAP_MAX_VERTEX_STREAMS:
 109       return 4;
 110    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 111       return 2048;
 112    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 113       return 256;
 114    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 115       return 16; /* 256 for binding as RT, but that's not possible in GL */
 116    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 117       return 16;
 118    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 119       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 120    case PIPE_CAP_MAX_VIEWPORTS:
 121       return NVC0_MAX_VIEWPORTS;
 122    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 123       return 4;
 124    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 125       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 126    case PIPE_CAP_ENDIANNESS:
 127       return PIPE_ENDIAN_LITTLE;
 128    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 129       return 30;
 130
 131    /* supported caps */
 132    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 133    case PIPE_CAP_TEXTURE_SWIZZLE:
 134    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 135    case PIPE_CAP_NPOT_TEXTURES:
 136    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 137    case PIPE_CAP_ANISOTROPIC_FILTER:
 138    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 139    case PIPE_CAP_CUBE_MAP_ARRAY:
 140    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 141    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 142    case PIPE_CAP_TWO_SIDED_STENCIL:
 143    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 144    case PIPE_CAP_POINT_SPRITE:
 145    case PIPE_CAP_TGSI_TEXCOORD:
 146    case PIPE_CAP_SM3:
 147    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 148    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 149    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 150    case PIPE_CAP_QUERY_TIMESTAMP:
 151    case PIPE_CAP_QUERY_TIME_ELAPSED:
 152    case PIPE_CAP_OCCLUSION_QUERY:
 153    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 154    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 155    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 156    case PIPE_CAP_INDEP_BLEND_ENABLE:
 157    case PIPE_CAP_INDEP_BLEND_FUNC:
 158    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 159    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 160    case PIPE_CAP_PRIMITIVE_RESTART:
 161    case PIPE_CAP_TGSI_INSTANCEID:
 162    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 163    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 164    case PIPE_CAP_CONDITIONAL_RENDER:
 165    case PIPE_CAP_TEXTURE_BARRIER:
 166    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 167    case PIPE_CAP_START_INSTANCE:
 168    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 169    case PIPE_CAP_DRAW_INDIRECT:
 170    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 171    case PIPE_CAP_USER_INDEX_BUFFERS:
 172    case PIPE_CAP_USER_VERTEX_BUFFERS:
 173    case PIPE_CAP_TEXTURE_QUERY_LOD:
 174    case PIPE_CAP_SAMPLE_SHADING:
 175    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 176    case PIPE_CAP_TEXTURE_GATHER_SM5:
 177    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 178    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 179    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 180    case PIPE_CAP_CLIP_HALFZ:
 181    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 182    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 183    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 184    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 185    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 186    case PIPE_CAP_TGSI_TXQS:
 187    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 188    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 189    case PIPE_CAP_SHAREABLE_SHADERS:
 190    case PIPE_CAP_CLEAR_TEXTURE:
 191    case PIPE_CAP_DRAW_PARAMETERS:
 192    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 193    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 194    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 195    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 196    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 197       return 1;
 198    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 199       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 200    case PIPE_CAP_COMPUTE:
 201       if (debug_get_bool_option("NVF0_COMPUTE", false))
 202          return 1;
 203       return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
 204    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 205       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 206
 207    /* unsupported caps */
 208    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 209    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 210    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 211    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 212    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 213    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 214    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 215    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 216    case PIPE_CAP_FAKE_SW_MSAA:
 217    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 218    case PIPE_CAP_VERTEXID_NOBASE:
 219    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 220    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 221    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 222    case PIPE_CAP_INVALIDATE_BUFFER:
 223    case PIPE_CAP_GENERATE_MIPMAP:
 224    case PIPE_CAP_STRING_MARKER:
 225    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 226    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 227    case PIPE_CAP_QUERY_MEMORY_INFO:
 228    case PIPE_CAP_PCI_GROUP:
 229    case PIPE_CAP_PCI_BUS:
 230    case PIPE_CAP_PCI_DEVICE:
 231    case PIPE_CAP_PCI_FUNCTION:
 232       return 0;
 233
 234    case PIPE_CAP_VENDOR_ID:
 235       return 0x10de;
 236    case PIPE_CAP_DEVICE_ID: {
 237       uint64_t device_id;
 238       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 239          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 240          return -1;
 241       }
 242       return device_id;
 243    }
 244    case PIPE_CAP_ACCELERATED:
 245       return 1;
 246    case PIPE_CAP_VIDEO_MEMORY:
 247       return dev->vram_size >> 20;
 248    case PIPE_CAP_UMA:
 249       return 0;
 250    }
 251
 252    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 253    return 0;
 254 }
 255
 256 static int
 257 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 258                              enum pipe_shader_cap param)
 259 {
 260    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 261
 262    switch (shader) {
 263    case PIPE_SHADER_VERTEX:
 264    case PIPE_SHADER_GEOMETRY:
 265    case PIPE_SHADER_FRAGMENT:
 266       break;
 267    case PIPE_SHADER_TESS_CTRL:
 268    case PIPE_SHADER_TESS_EVAL:
 269       if (class_3d >= GM107_3D_CLASS)
 270          return 0;
 271       break;
 272    case PIPE_SHADER_COMPUTE:
 273       if (!debug_get_bool_option("NVF0_COMPUTE", false))
 274          if (class_3d > NVE4_3D_CLASS)
 275             return 0;
 276       break;
 277    default:
 278       return 0;
 279    }
 280
 281    switch (param) {
 282    case PIPE_SHADER_CAP_PREFERRED_IR:
 283       return PIPE_SHADER_IR_TGSI;
 284    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 285       if (class_3d >= NVE4_3D_CLASS)
 286          return 0;
 287       return 1 << PIPE_SHADER_IR_TGSI;
 288    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 289    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 290    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 291    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 292       return 16384;
 293    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 294       return 16;
 295    case PIPE_SHADER_CAP_MAX_INPUTS:
 296       if (shader == PIPE_SHADER_VERTEX)
 297          return 32;
 298       /* NOTE: These only count our slots for GENERIC varyings.
 299        * The address space may be larger, but the actual hard limit seems to be
 300        * less than what the address space layout permits, so don't add TEXCOORD,
 301        * COLOR, etc. here.
 302        */
 303       if (shader == PIPE_SHADER_FRAGMENT)
 304          return 0x1f0 / 16;
 305       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 306        * and excludes 0x60 per-patch inputs.
 307        */
 308       return 0x200 / 16;
 309    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 310       return 32;
 311    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 312       return 65536;
 313    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 314       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 315          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 316       return NVC0_MAX_PIPE_CONSTBUFS;
 317    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 318       return shader != PIPE_SHADER_FRAGMENT;
 319    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 320       return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
 321    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 322    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 323       return 1;
 324    case PIPE_SHADER_CAP_MAX_PREDS:
 325       return 0;
 326    case PIPE_SHADER_CAP_MAX_TEMPS:
 327       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 328    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 329       return 1;
 330    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 331       return 0;
 332    case PIPE_SHADER_CAP_SUBROUTINES:
 333       return 1;
 334    case PIPE_SHADER_CAP_INTEGERS:
 335       return 1;
 336    case PIPE_SHADER_CAP_DOUBLES:
 337       return 1;
 338    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 339       return 1;
 340    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 341       return 1;
 342    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 343    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 344       return 0;
 345    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 346       return NVC0_MAX_BUFFERS;
 347    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 348       return 16; /* would be 32 in linked (OpenGL-style) mode */
 349    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 350       return 16; /* XXX not sure if more are really safe */
 351    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 352       return 32;
 353    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 354       return 0;
 355    default:
 356       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 357       return 0;
 358    }
 359 }
 360
 361 static float
 362 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 363 {
 364    switch (param) {
 365    case PIPE_CAPF_MAX_LINE_WIDTH:
 366    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 367       return 10.0f;
 368    case PIPE_CAPF_MAX_POINT_WIDTH:
 369       return 63.0f;
 370    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 371       return 63.375f;
 372    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 373       return 16.0f;
 374    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 375       return 15.0f;
 376    case PIPE_CAPF_GUARD_BAND_LEFT:
 377    case PIPE_CAPF_GUARD_BAND_TOP:
 378       return 0.0f;
 379    case PIPE_CAPF_GUARD_BAND_RIGHT:
 380    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 381       return 0.0f; /* that or infinity */
 382    }
 383
 384    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 385    return 0.0f;
 386 }
 387
 388 static int
 389 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 390                               enum pipe_compute_cap param, void *data)
 391 {
 392    struct nvc0_screen *screen = nvc0_screen(pscreen);
 393    const uint16_t obj_class = screen->compute->oclass;
 394
 395 #define RET(x) do {                  \
 396    if (data)                         \
 397       memcpy(data, x, sizeof(x));    \
 398    return sizeof(x);                 \
 399 } while (0)
 400
 401    switch (param) {
 402    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 403       RET((uint64_t []) { 3 });
 404    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 405       if (obj_class >= NVE4_COMPUTE_CLASS) {
 406          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 407       } else {
 408          RET(((uint64_t []) { 65535, 65535, 65535 }));
 409       }
 410    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 411       RET(((uint64_t []) { 1024, 1024, 64 }));
 412    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 413       RET((uint64_t []) { 1024 });
 414    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 415       RET((uint64_t []) { 1ULL << 40 });
 416    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 417       RET((uint64_t []) { 48 << 10 });
 418    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 419       RET((uint64_t []) { 512 << 10 });
 420    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 421       RET((uint64_t []) { 4096 });
 422    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 423       RET((uint32_t []) { 32 });
 424    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 425       RET((uint64_t []) { 1ULL << 40 });
 426    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 427       RET((uint32_t []) { 0 });
 428    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 429       RET((uint32_t []) { screen->mp_count_compute });
 430    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 431       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 432    default:
 433       return 0;
 434    }
 435
 436 #undef RET
 437 }
 438
 439 static void
 440 nvc0_screen_destroy(struct pipe_screen *pscreen)
 441 {
 442    struct nvc0_screen *screen = nvc0_screen(pscreen);
 443
 444    if (!nouveau_drm_screen_unref(&screen->base))
 445       return;
 446
 447    if (screen->base.fence.current) {
 448       struct nouveau_fence *current = NULL;
 449
 450       /* nouveau_fence_wait will create a new current fence, so wait on the
 451        * _current_ one, and remove both.
 452        */
 453       nouveau_fence_ref(screen->base.fence.current, &current);
 454       nouveau_fence_wait(current, NULL);
 455       nouveau_fence_ref(NULL, &current);
 456       nouveau_fence_ref(NULL, &screen->base.fence.current);
 457    }
 458    if (screen->base.pushbuf)
 459       screen->base.pushbuf->user_priv = NULL;
 460
 461    if (screen->blitter)
 462       nvc0_blitter_destroy(screen);
 463    if (screen->pm.prog) {
 464       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 465       nvc0_program_destroy(NULL, screen->pm.prog);
 466       FREE(screen->pm.prog);
 467    }
 468
 469    nouveau_bo_ref(NULL, &screen->text);
 470    nouveau_bo_ref(NULL, &screen->uniform_bo);
 471    nouveau_bo_ref(NULL, &screen->tls);
 472    nouveau_bo_ref(NULL, &screen->txc);
 473    nouveau_bo_ref(NULL, &screen->fence.bo);
 474    nouveau_bo_ref(NULL, &screen->poly_cache);
 475    nouveau_bo_ref(NULL, &screen->parm);
 476
 477    nouveau_heap_destroy(&screen->lib_code);
 478    nouveau_heap_destroy(&screen->text_heap);
 479
 480    FREE(screen->tic.entries);
 481
 482    nouveau_object_del(&screen->eng3d);
 483    nouveau_object_del(&screen->eng2d);
 484    nouveau_object_del(&screen->m2mf);
 485    nouveau_object_del(&screen->compute);
 486    nouveau_object_del(&screen->nvsw);
 487
 488    nouveau_screen_fini(&screen->base);
 489
 490    FREE(screen);
 491 }
 492
 493 static int
 494 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 495                      unsigned size, const uint32_t *data)
 496 {
 497    struct nouveau_pushbuf *push = screen->base.pushbuf;
 498
 499    size /= 4;
 500
 501    assert((pos + size) <= 0x800);
 502
 503    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 504    PUSH_DATA (push, (m - 0x3800) / 8);
 505    PUSH_DATA (push, pos);
 506    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 507    PUSH_DATA (push, pos);
 508    PUSH_DATAp(push, data, size);
 509
 510    return pos + size;
 511 }
 512
 513 static void
 514 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 515 {
 516    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 517    PUSH_DATA (push, 0xff);
 518    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 519    PUSH_DATA (push, 0xff);
 520    PUSH_DATA (push, 0xff);
 521    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 522    PUSH_DATA (push, 0xff);
 523    PUSH_DATA (push, 0xff);
 524    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 525    PUSH_DATA (push, 0x3f);
 526
 527    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 528    PUSH_DATA (push, (3 << 16) | 3);
 529    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 530    PUSH_DATA (push, (2 << 16) | 2);
 531
 532    if (obj_class < GM107_3D_CLASS) {
 533       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 534       PUSH_DATA (push, 0);
 535    }
 536    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 537    PUSH_DATA (push, 0x10);
 538    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 539    PUSH_DATA (push, 0x10);
 540    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 541    PUSH_DATA (push, 0x10);
 542    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 543    PUSH_DATA (push, 0x10);
 544    PUSH_DATA (push, 0x10);
 545    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 546    PUSH_DATA (push, 0x10);
 547    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 548    PUSH_DATA (push, 0xe);
 549
 550    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 551    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 552    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 553    PUSH_DATA (push, 0);
 554    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 555    PUSH_DATA (push, 3);
 556
 557    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 558    PUSH_DATA (push, 0x3fffff);
 559    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 560    PUSH_DATA (push, 1);
 561    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 562    PUSH_DATA (push, 1);
 563
 564    if (obj_class < GM107_3D_CLASS) {
 565       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 566       PUSH_DATA (push, 3);
 567
 568       if (obj_class >= NVE4_3D_CLASS) {
 569          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 570          PUSH_DATA (push, 1);
 571       }
 572    }
 573
 574    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 575     * are supposed to do */
 576 }
 577
 578 static void
 579 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 580 {
 581    struct nvc0_screen *screen = nvc0_screen(pscreen);
 582    struct nouveau_pushbuf *push = screen->base.pushbuf;
 583
 584    /* we need to do it after possible flush in MARK_RING */
 585    *sequence = ++screen->base.fence.sequence;
 586
 587    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 588    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 589    PUSH_DATAh(push, screen->fence.bo->offset);
 590    PUSH_DATA (push, screen->fence.bo->offset);
 591    PUSH_DATA (push, *sequence);
 592    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 593               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 594 }
 595
 596 static u32
 597 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 598 {
 599    struct nvc0_screen *screen = nvc0_screen(pscreen);
 600    return screen->fence.map[0];
 601 }
 602
 603 static int
 604 nvc0_screen_init_compute(struct nvc0_screen *screen)
 605 {
 606    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 607
 608    switch (screen->base.device->chipset & ~0xf) {
 609    case 0xc0:
 610    case 0xd0:
 611       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 612    case 0xe0:
 613       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 614    case 0xf0:
 615    case 0x100:
 616    case 0x110:
 617       if (debug_get_bool_option("NVF0_COMPUTE", false))
 618          return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 619    case 0x120:
 620       return 0;
 621    default:
 622       return -1;
 623    }
 624 }
 625
 626 bool
 627 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 628                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 629 {
 630    struct nouveau_bo *bo = NULL;
 631    int ret;
 632    uint64_t size = (lpos + lneg) * 32 + cstack;
 633
 634    if (size >= (1 << 20)) {
 635       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 636       return false;
 637    }
 638
 639    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 640    size  = align(size, 0x8000);
 641    size *= screen->mp_count;
 642
 643    size = align(size, 1 << 17);
 644
 645    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 646                         NULL, &bo);
 647    if (ret) {
 648       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 649       return false;
 650    }
 651    nouveau_bo_ref(NULL, &screen->tls);
 652    screen->tls = bo;
 653    return true;
 654 }
 655
 656 #define FAIL_SCREEN_INIT(str, err)                    \
 657    do {                                               \
 658       NOUVEAU_ERR(str, err);                          \
 659       goto fail;                                      \
 660    } while(0)
 661
 662 struct nouveau_screen *
 663 nvc0_screen_create(struct nouveau_device *dev)
 664 {
 665    struct nvc0_screen *screen;
 666    struct pipe_screen *pscreen;
 667    struct nouveau_object *chan;
 668    struct nouveau_pushbuf *push;
 669    uint64_t value;
 670    uint32_t obj_class;
 671    uint32_t flags;
 672    int ret;
 673    unsigned i;
 674
 675    switch (dev->chipset & ~0xf) {
 676    case 0xc0:
 677    case 0xd0:
 678    case 0xe0:
 679    case 0xf0:
 680    case 0x100:
 681    case 0x110:
 682    case 0x120:
 683       break;
 684    default:
 685       return NULL;
 686    }
 687
 688    screen = CALLOC_STRUCT(nvc0_screen);
 689    if (!screen)
 690       return NULL;
 691    pscreen = &screen->base.base;
 692    pscreen->destroy = nvc0_screen_destroy;
 693
 694    ret = nouveau_screen_init(&screen->base, dev);
 695    if (ret) {
 696       nvc0_screen_destroy(pscreen);
 697       return NULL;
 698    }
 699    chan = screen->base.channel;
 700    push = screen->base.pushbuf;
 701    push->user_priv = screen;
 702    push->rsvd_kick = 5;
 703
 704    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 705       PIPE_BIND_SHADER_BUFFER |
 706       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 707       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 708    screen->base.sysmem_bindings |=
 709       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 710
 711    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 712       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 713       screen->base.vidmem_bindings = 0;
 714    }
 715
 716    pscreen->context_create = nvc0_create;
 717    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 718    pscreen->get_param = nvc0_screen_get_param;
 719    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 720    pscreen->get_paramf = nvc0_screen_get_paramf;
 721    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 722    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 723
 724    nvc0_screen_init_resource_functions(pscreen);
 725
 726    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 727    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 728
 729    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 730    if (screen->base.drm->version >= 0x01000202)
 731       flags |= NOUVEAU_BO_COHERENT;
 732
 733    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 734    if (ret)
 735       goto fail;
 736    nouveau_bo_map(screen->fence.bo, 0, NULL);
 737    screen->fence.map = screen->fence.bo->map;
 738    screen->base.fence.emit = nvc0_screen_fence_emit;
 739    screen->base.fence.update = nvc0_screen_fence_update;
 740
 741
 742    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 743                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 744    if (ret)
 745       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 746
 747    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 748    PUSH_DATA (push, screen->nvsw->handle);
 749
 750    switch (dev->chipset & ~0xf) {
 751    case 0x120:
 752    case 0x110:
 753    case 0x100:
 754    case 0xf0:
 755       obj_class = NVF0_P2MF_CLASS;
 756       break;
 757    case 0xe0:
 758       obj_class = NVE4_P2MF_CLASS;
 759       break;
 760    default:
 761       obj_class = NVC0_M2MF_CLASS;
 762       break;
 763    }
 764    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 765                             &screen->m2mf);
 766    if (ret)
 767       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 768
 769    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 770    PUSH_DATA (push, screen->m2mf->oclass);
 771    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 772       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 773       PUSH_DATA (push, 0xa0b5);
 774    }
 775
 776    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 777                             &screen->eng2d);
 778    if (ret)
 779       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 780
 781    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 782    PUSH_DATA (push, screen->eng2d->oclass);
 783    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 784    PUSH_DATA (push, 0);
 785    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 786    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 787    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 788    PUSH_DATA (push, 0);
 789    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 790    PUSH_DATA (push, 0);
 791    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 792    PUSH_DATA (push, 0x3f);
 793    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 794    PUSH_DATA (push, 1);
 795    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 796    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 797
 798    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 799    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 800    PUSH_DATA (push, screen->fence.bo->offset + 16);
 801
 802    switch (dev->chipset & ~0xf) {
 803    case 0x120:
 804       obj_class = GM200_3D_CLASS;
 805       break;
 806    case 0x110:
 807       obj_class = GM107_3D_CLASS;
 808       break;
 809    case 0x100:
 810    case 0xf0:
 811       obj_class = NVF0_3D_CLASS;
 812       break;
 813    case 0xe0:
 814       switch (dev->chipset) {
 815       case 0xea:
 816          obj_class = NVEA_3D_CLASS;
 817          break;
 818       default:
 819          obj_class = NVE4_3D_CLASS;
 820          break;
 821       }
 822       break;
 823    case 0xd0:
 824       obj_class = NVC8_3D_CLASS;
 825       break;
 826    case 0xc0:
 827    default:
 828       switch (dev->chipset) {
 829       case 0xc8:
 830          obj_class = NVC8_3D_CLASS;
 831          break;
 832       case 0xc1:
 833          obj_class = NVC1_3D_CLASS;
 834          break;
 835       default:
 836          obj_class = NVC0_3D_CLASS;
 837          break;
 838       }
 839       break;
 840    }
 841    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 842                             &screen->eng3d);
 843    if (ret)
 844       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 845    screen->base.class_3d = obj_class;
 846
 847    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 848    PUSH_DATA (push, screen->eng3d->oclass);
 849
 850    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 851    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 852
 853    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 854       /* kill shaders after about 1 second (at 100 MHz) */
 855       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 856       PUSH_DATA (push, 0x17);
 857    }
 858
 859    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 860                     screen->base.drm->version >= 0x01000101);
 861    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 862    for (i = 0; i < 8; ++i)
 863            PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 864
 865    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 866    PUSH_DATA (push, 1);
 867
 868    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 869    PUSH_DATA (push, 0);
 870    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 871    PUSH_DATA (push, 0);
 872    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 873    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 874    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 875    PUSH_DATA (push, 0);
 876    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 877    PUSH_DATA (push, 1);
 878    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 879    PUSH_DATA (push, 1);
 880    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 881    PUSH_DATA (push, 1);
 882    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 883    PUSH_DATA (push, 0);
 884    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 885    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 886    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 887       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 888    } else {
 889       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 890       PUSH_DATA (push, 15);
 891    }
 892    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 893    PUSH_DATA (push, 8); /* 128 */
 894    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 895    PUSH_DATA (push, 1);
 896    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 897       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 898       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 899    }
 900
 901    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 902
 903    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
 904                         &screen->text);
 905    if (ret)
 906       goto fail;
 907
 908    /* XXX: getting a page fault at the end of the code buffer every few
 909     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 910     */
 911    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 912
 913    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
 914                         &screen->uniform_bo);
 915    if (ret)
 916       goto fail;
 917
 918    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
 919
 920    for (i = 0; i < 5; ++i) {
 921       /* TIC and TSC entries for each unit (nve4+ only) */
 922       /* auxiliary constants (6 user clip planes, base instance id) */
 923       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 924       PUSH_DATA (push, 1024);
 925       PUSH_DATAh(push, screen->uniform_bo->offset + (6 << 16) + (i << 10));
 926       PUSH_DATA (push, screen->uniform_bo->offset + (6 << 16) + (i << 10));
 927       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 928       PUSH_DATA (push, (15 << 4) | 1);
 929       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 930          unsigned j;
 931          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 932          PUSH_DATA (push, 0);
 933          for (j = 0; j < 8; ++j)
 934             PUSH_DATA(push, j);
 935       } else {
 936          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 937          PUSH_DATA (push, 0x54);
 938       }
 939    }
 940    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 941    PUSH_DATA (push, 0);
 942
 943    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 944    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 945    PUSH_DATA (push, 256);
 946    PUSH_DATAh(push, screen->uniform_bo->offset + (6 << 16) + (6 << 10));
 947    PUSH_DATA (push, screen->uniform_bo->offset + (6 << 16) + (6 << 10));
 948    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 949    PUSH_DATA (push, 0);
 950    PUSH_DATAf(push, 0.0f);
 951    PUSH_DATAf(push, 0.0f);
 952    PUSH_DATAf(push, 0.0f);
 953    PUSH_DATAf(push, 0.0f);
 954    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 955    PUSH_DATAh(push, screen->uniform_bo->offset + (6 << 16) + (6 << 10));
 956    PUSH_DATA (push, screen->uniform_bo->offset + (6 << 16) + (6 << 10));
 957
 958    if (screen->base.drm->version >= 0x01000101) {
 959       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 960       if (ret) {
 961          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 962          goto fail;
 963       }
 964    } else {
 965       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 966          value = (8 << 8) | 4;
 967       else
 968          value = (16 << 8) | 4;
 969    }
 970    screen->gpc_count = value & 0x000000ff;
 971    screen->mp_count = value >> 8;
 972    screen->mp_count_compute = screen->mp_count;
 973
 974    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 975
 976    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 977    PUSH_DATAh(push, screen->text->offset);
 978    PUSH_DATA (push, screen->text->offset);
 979    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 980    PUSH_DATAh(push, screen->tls->offset);
 981    PUSH_DATA (push, screen->tls->offset);
 982    PUSH_DATA (push, screen->tls->size >> 32);
 983    PUSH_DATA (push, screen->tls->size);
 984    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 985    PUSH_DATA (push, 0);
 986    /* Reduce likelihood of collision with real buffers by placing the hole at
 987     * the top of the 4G area. This will have to be dealt with for real
 988     * eventually by blocking off that area from the VM.
 989     */
 990    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 991    PUSH_DATA (push, 0xff << 24);
 992
 993    if (screen->eng3d->oclass < GM107_3D_CLASS) {
 994       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
 995                            &screen->poly_cache);
 996       if (ret)
 997          goto fail;
 998
 999       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1000       PUSH_DATAh(push, screen->poly_cache->offset);
1001       PUSH_DATA (push, screen->poly_cache->offset);
1002       PUSH_DATA (push, 3);
1003    }
1004
1005    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1006                         &screen->txc);
1007    if (ret)
1008       goto fail;
1009
1010    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1011    PUSH_DATAh(push, screen->txc->offset);
1012    PUSH_DATA (push, screen->txc->offset);
1013    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1014    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1015       screen->tic.maxwell = true;
1016       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1017          screen->tic.maxwell =
1018             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1019          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1020       }
1021    }
1022
1023    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1024    PUSH_DATAh(push, screen->txc->offset + 65536);
1025    PUSH_DATA (push, screen->txc->offset + 65536);
1026    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1027
1028    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1029    PUSH_DATA (push, 0);
1030    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1031    PUSH_DATA (push, 0);
1032    PUSH_DATA (push, 0);
1033    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1034    PUSH_DATA (push, 0x3f);
1035
1036    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1037    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1038    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1039    for (i = 0; i < 8 * 2; ++i)
1040       PUSH_DATA(push, 0);
1041    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1042    PUSH_DATA (push, 0);
1043    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1044    PUSH_DATA (push, 0);
1045
1046    /* neither scissors, viewport nor stencil mask should affect clears */
1047    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1048    PUSH_DATA (push, 0);
1049
1050    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1051    PUSH_DATA (push, 1);
1052    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1053       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1054       PUSH_DATAf(push, 0.0f);
1055       PUSH_DATAf(push, 1.0f);
1056    }
1057    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1058    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1059
1060    /* We use scissors instead of exact view volume clipping,
1061     * so they're always enabled.
1062     */
1063    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1064       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1065       PUSH_DATA (push, 1);
1066       PUSH_DATA (push, 8192 << 16);
1067       PUSH_DATA (push, 8192 << 16);
1068    }
1069
1070 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1071
1072    i = 0;
1073    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1074    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1075    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1076    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1077    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1078    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1079    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1080    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1081    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1082    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1083    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1084    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1085    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1086
1087    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1088    PUSH_DATA (push, 1);
1089    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1090    PUSH_DATA (push, 1);
1091    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1092    PUSH_DATA (push, 0x40);
1093    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1094    PUSH_DATA (push, 0);
1095    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1096    PUSH_DATA (push, 0x30);
1097    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1098    PUSH_DATA (push, 3);
1099    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1100    PUSH_DATA (push, 0x20);
1101    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1102    PUSH_DATA (push, 0x00);
1103    screen->save_state.patch_vertices = 3;
1104
1105    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1106    PUSH_DATA (push, 0);
1107    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1108    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1109
1110    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1111
1112    if (nvc0_screen_init_compute(screen))
1113       goto fail;
1114
1115    PUSH_KICK (push);
1116
1117    screen->tic.entries = CALLOC(4096, sizeof(void *));
1118    screen->tsc.entries = screen->tic.entries + 2048;
1119
1120    if (!nvc0_blitter_create(screen))
1121       goto fail;
1122
1123    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1124
1125    return &screen->base;
1126
1127 fail:
1128    screen->base.base.context_create = NULL;
1129    return &screen->base;
1130 }
1131
1132 int
1133 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1134 {
1135    int i = screen->tic.next;
1136
1137    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1138       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1139
1140    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1141
1142    if (screen->tic.entries[i])
1143       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1144
1145    screen->tic.entries[i] = entry;
1146    return i;
1147 }
1148
1149 int
1150 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1151 {
1152    int i = screen->tsc.next;
1153
1154    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1155       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1156
1157    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1158
1159    if (screen->tsc.entries[i])
1160       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1161
1162    screen->tsc.entries[i] = entry;
1163    return i;
1164 }