src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    const struct util_format_description *desc = util_format_description(format);
  49
  50    if (sample_count > 8)
  51       return false;
  52    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  53       return false;
  54
  55    /* Short-circuit the rest of the logic -- this is used by the state tracker
  56     * to determine valid MS levels in a no-attachments scenario.
  57     */
  58    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  59       return true;
  60
  61    if (!util_format_is_supported(format, bindings))
  62       return false;
  63
  64    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  65       if (util_format_get_blocksizebits(format) == 3 * 32)
  66          return false;
  67
  68    if (bindings & PIPE_BIND_LINEAR)
  69       if (util_format_is_depth_or_stencil(format) ||
  70           (target != PIPE_TEXTURE_1D &&
  71            target != PIPE_TEXTURE_2D &&
  72            target != PIPE_TEXTURE_RECT) ||
  73           sample_count > 1)
  74          return false;
  75
  76    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  77     */
  78    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  79         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  80        /* The claim is that this should work on GM107 but it doesn't. Need to
  81         * test further and figure out if it's a nouveau issue or a HW one.
  82        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  83         */
  84        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  85       return false;
  86
  87    /* shared is always supported */
  88    bindings &= ~(PIPE_BIND_LINEAR |
  89                  PIPE_BIND_SHARED);
  90
  91    if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
  92        nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
  93       /* MS images are currently unsupported on Maxwell because they have to
  94        * be handled explicitly. */
  95       return false;
  96    }
  97
  98    return (( nvc0_format_table[format].usage |
  99             nvc0_vertex_format[format].usage) & bindings) == bindings;
 100 }
 101
 102 static int
 103 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 104 {
 105    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 106    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 107
 108    switch (param) {
 109    /* non-boolean caps */
 110    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 111    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 112       return 15;
 113    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 114       return 12;
 115    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 116       return 2048;
 117    case PIPE_CAP_MIN_TEXEL_OFFSET:
 118       return -8;
 119    case PIPE_CAP_MAX_TEXEL_OFFSET:
 120       return 7;
 121    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 122       return -32;
 123    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 124       return 31;
 125    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 126       return 128 * 1024 * 1024;
 127    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 128       if (class_3d <= NVF0_3D_CLASS)
 129          return 430;
 130       return 410;
 131    case PIPE_CAP_MAX_RENDER_TARGETS:
 132       return 8;
 133    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 134       return 1;
 135    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 136       return 4;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 138    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 139       return 128;
 140    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 141    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 142       return 1024;
 143    case PIPE_CAP_MAX_VERTEX_STREAMS:
 144       return 4;
 145    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 146       return 2048;
 147    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 148       return 256;
 149    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 150       return 16; /* 256 for binding as RT, but that's not possible in GL */
 151    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 152       return 16;
 153    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 154       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 155    case PIPE_CAP_MAX_VIEWPORTS:
 156       return NVC0_MAX_VIEWPORTS;
 157    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 158       return 4;
 159    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 160       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 161    case PIPE_CAP_ENDIANNESS:
 162       return PIPE_ENDIAN_LITTLE;
 163    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 164       return 30;
 165    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 166       return NVC0_MAX_WINDOW_RECTANGLES;
 167
 168    /* supported caps */
 169    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 170    case PIPE_CAP_TEXTURE_SWIZZLE:
 171    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 172    case PIPE_CAP_NPOT_TEXTURES:
 173    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 174    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 175    case PIPE_CAP_ANISOTROPIC_FILTER:
 176    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 177    case PIPE_CAP_CUBE_MAP_ARRAY:
 178    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 179    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180    case PIPE_CAP_TWO_SIDED_STENCIL:
 181    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 182    case PIPE_CAP_POINT_SPRITE:
 183    case PIPE_CAP_TGSI_TEXCOORD:
 184    case PIPE_CAP_SM3:
 185    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 186    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 187    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 188    case PIPE_CAP_QUERY_TIMESTAMP:
 189    case PIPE_CAP_QUERY_TIME_ELAPSED:
 190    case PIPE_CAP_OCCLUSION_QUERY:
 191    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 192    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 193    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 194    case PIPE_CAP_INDEP_BLEND_ENABLE:
 195    case PIPE_CAP_INDEP_BLEND_FUNC:
 196    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 197    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 198    case PIPE_CAP_PRIMITIVE_RESTART:
 199    case PIPE_CAP_TGSI_INSTANCEID:
 200    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 201    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 202    case PIPE_CAP_CONDITIONAL_RENDER:
 203    case PIPE_CAP_TEXTURE_BARRIER:
 204    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 205    case PIPE_CAP_START_INSTANCE:
 206    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 207    case PIPE_CAP_DRAW_INDIRECT:
 208    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 209    case PIPE_CAP_USER_INDEX_BUFFERS:
 210    case PIPE_CAP_USER_VERTEX_BUFFERS:
 211    case PIPE_CAP_TEXTURE_QUERY_LOD:
 212    case PIPE_CAP_SAMPLE_SHADING:
 213    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 214    case PIPE_CAP_TEXTURE_GATHER_SM5:
 215    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 216    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 217    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 218    case PIPE_CAP_CLIP_HALFZ:
 219    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 220    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 221    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 222    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 223    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 224    case PIPE_CAP_TGSI_TXQS:
 225    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 226    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 227    case PIPE_CAP_SHAREABLE_SHADERS:
 228    case PIPE_CAP_CLEAR_TEXTURE:
 229    case PIPE_CAP_DRAW_PARAMETERS:
 230    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 231    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 232    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 233    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 234    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 235    case PIPE_CAP_INVALIDATE_BUFFER:
 236    case PIPE_CAP_STRING_MARKER:
 237    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 238    case PIPE_CAP_CULL_DISTANCE:
 239    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 240    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 241    case PIPE_CAP_TGSI_VOTE:
 242    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 243       return 1;
 244    case PIPE_CAP_COMPUTE:
 245       return (class_3d < GP100_3D_CLASS);
 246    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 247       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 248    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 249       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 250
 251    /* unsupported caps */
 252    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 253    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 254    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 255    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 256    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 257    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 258    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 259    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 260    case PIPE_CAP_FAKE_SW_MSAA:
 261    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 262    case PIPE_CAP_VERTEXID_NOBASE:
 263    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 264    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 265    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 266    case PIPE_CAP_GENERATE_MIPMAP:
 267    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 268    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 269    case PIPE_CAP_QUERY_MEMORY_INFO:
 270    case PIPE_CAP_PCI_GROUP:
 271    case PIPE_CAP_PCI_BUS:
 272    case PIPE_CAP_PCI_DEVICE:
 273    case PIPE_CAP_PCI_FUNCTION:
 274    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 275       return 0;
 276
 277    case PIPE_CAP_VENDOR_ID:
 278       return 0x10de;
 279    case PIPE_CAP_DEVICE_ID: {
 280       uint64_t device_id;
 281       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 282          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 283          return -1;
 284       }
 285       return device_id;
 286    }
 287    case PIPE_CAP_ACCELERATED:
 288       return 1;
 289    case PIPE_CAP_VIDEO_MEMORY:
 290       return dev->vram_size >> 20;
 291    case PIPE_CAP_UMA:
 292       return 0;
 293    }
 294
 295    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 296    return 0;
 297 }
 298
 299 static int
 300 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 301                              enum pipe_shader_cap param)
 302 {
 303    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 304
 305    switch (shader) {
 306    case PIPE_SHADER_VERTEX:
 307    case PIPE_SHADER_GEOMETRY:
 308    case PIPE_SHADER_FRAGMENT:
 309    case PIPE_SHADER_COMPUTE:
 310    case PIPE_SHADER_TESS_CTRL:
 311    case PIPE_SHADER_TESS_EVAL:
 312       break;
 313    default:
 314       return 0;
 315    }
 316
 317    switch (param) {
 318    case PIPE_SHADER_CAP_PREFERRED_IR:
 319       return PIPE_SHADER_IR_TGSI;
 320    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 321       return 1 << PIPE_SHADER_IR_TGSI;
 322    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 323    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 324    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 325    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 326       return 16384;
 327    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 328       return 16;
 329    case PIPE_SHADER_CAP_MAX_INPUTS:
 330       if (shader == PIPE_SHADER_VERTEX)
 331          return 32;
 332       /* NOTE: These only count our slots for GENERIC varyings.
 333        * The address space may be larger, but the actual hard limit seems to be
 334        * less than what the address space layout permits, so don't add TEXCOORD,
 335        * COLOR, etc. here.
 336        */
 337       if (shader == PIPE_SHADER_FRAGMENT)
 338          return 0x1f0 / 16;
 339       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 340        * and excludes 0x60 per-patch inputs.
 341        */
 342       return 0x200 / 16;
 343    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 344       return 32;
 345    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 346       return 65536;
 347    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 348       return NVC0_MAX_PIPE_CONSTBUFS;
 349    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 350       return shader != PIPE_SHADER_FRAGMENT;
 351    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 352    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 353    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 354       return 1;
 355    case PIPE_SHADER_CAP_MAX_PREDS:
 356       return 0;
 357    case PIPE_SHADER_CAP_MAX_TEMPS:
 358       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 359    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 360       return 1;
 361    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 362       return 1;
 363    case PIPE_SHADER_CAP_SUBROUTINES:
 364       return 1;
 365    case PIPE_SHADER_CAP_INTEGERS:
 366       return 1;
 367    case PIPE_SHADER_CAP_DOUBLES:
 368       return 1;
 369    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 370       return 1;
 371    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 372       return 1;
 373    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 374    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 375       return 0;
 376    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 377       return NVC0_MAX_BUFFERS;
 378    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 379       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 380    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 381       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 382    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 383       return 32;
 384    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 385       if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
 386          return NVC0_MAX_IMAGES;
 387       if (class_3d < NVE4_3D_CLASS)
 388          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 389             return NVC0_MAX_IMAGES;
 390       return 0;
 391    default:
 392       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 393       return 0;
 394    }
 395 }
 396
 397 static float
 398 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 399 {
 400    switch (param) {
 401    case PIPE_CAPF_MAX_LINE_WIDTH:
 402    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 403       return 10.0f;
 404    case PIPE_CAPF_MAX_POINT_WIDTH:
 405       return 63.0f;
 406    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 407       return 63.375f;
 408    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 409       return 16.0f;
 410    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 411       return 15.0f;
 412    case PIPE_CAPF_GUARD_BAND_LEFT:
 413    case PIPE_CAPF_GUARD_BAND_TOP:
 414       return 0.0f;
 415    case PIPE_CAPF_GUARD_BAND_RIGHT:
 416    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 417       return 0.0f; /* that or infinity */
 418    }
 419
 420    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 421    return 0.0f;
 422 }
 423
 424 static int
 425 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 426                               enum pipe_shader_ir ir_type,
 427                               enum pipe_compute_cap param, void *data)
 428 {
 429    struct nvc0_screen *screen = nvc0_screen(pscreen);
 430    const uint16_t obj_class = screen->compute->oclass;
 431
 432 #define RET(x) do {                  \
 433    if (data)                         \
 434       memcpy(data, x, sizeof(x));    \
 435    return sizeof(x);                 \
 436 } while (0)
 437
 438    switch (param) {
 439    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 440       RET((uint64_t []) { 3 });
 441    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 442       if (obj_class >= NVE4_COMPUTE_CLASS) {
 443          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 444       } else {
 445          RET(((uint64_t []) { 65535, 65535, 65535 }));
 446       }
 447    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 448       RET(((uint64_t []) { 1024, 1024, 64 }));
 449    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 450       RET((uint64_t []) { 1024 });
 451    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 452       RET((uint64_t []) { 1ULL << 40 });
 453    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 454       switch (obj_class) {
 455       case GM200_COMPUTE_CLASS:
 456          RET((uint64_t []) { 96 << 10 });
 457          break;
 458       case GM107_COMPUTE_CLASS:
 459          RET((uint64_t []) { 64 << 10 });
 460          break;
 461       default:
 462          RET((uint64_t []) { 48 << 10 });
 463          break;
 464       }
 465    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 466       RET((uint64_t []) { 512 << 10 });
 467    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 468       RET((uint64_t []) { 4096 });
 469    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 470       RET((uint32_t []) { 32 });
 471    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 472       RET((uint64_t []) { 1ULL << 40 });
 473    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 474       RET((uint32_t []) { 0 });
 475    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 476       RET((uint32_t []) { screen->mp_count_compute });
 477    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 478       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 479    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 480       RET((uint32_t []) { 64 });
 481    default:
 482       return 0;
 483    }
 484
 485 #undef RET
 486 }
 487
 488 static void
 489 nvc0_screen_destroy(struct pipe_screen *pscreen)
 490 {
 491    struct nvc0_screen *screen = nvc0_screen(pscreen);
 492
 493    if (!nouveau_drm_screen_unref(&screen->base))
 494       return;
 495
 496    if (screen->base.fence.current) {
 497       struct nouveau_fence *current = NULL;
 498
 499       /* nouveau_fence_wait will create a new current fence, so wait on the
 500        * _current_ one, and remove both.
 501        */
 502       nouveau_fence_ref(screen->base.fence.current, &current);
 503       nouveau_fence_wait(current, NULL);
 504       nouveau_fence_ref(NULL, &current);
 505       nouveau_fence_ref(NULL, &screen->base.fence.current);
 506    }
 507    if (screen->base.pushbuf)
 508       screen->base.pushbuf->user_priv = NULL;
 509
 510    if (screen->blitter)
 511       nvc0_blitter_destroy(screen);
 512    if (screen->pm.prog) {
 513       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 514       nvc0_program_destroy(NULL, screen->pm.prog);
 515       FREE(screen->pm.prog);
 516    }
 517
 518    nouveau_bo_ref(NULL, &screen->text);
 519    nouveau_bo_ref(NULL, &screen->uniform_bo);
 520    nouveau_bo_ref(NULL, &screen->tls);
 521    nouveau_bo_ref(NULL, &screen->txc);
 522    nouveau_bo_ref(NULL, &screen->fence.bo);
 523    nouveau_bo_ref(NULL, &screen->poly_cache);
 524
 525    nouveau_heap_destroy(&screen->lib_code);
 526    nouveau_heap_destroy(&screen->text_heap);
 527
 528    FREE(screen->tic.entries);
 529
 530    nouveau_object_del(&screen->eng3d);
 531    nouveau_object_del(&screen->eng2d);
 532    nouveau_object_del(&screen->m2mf);
 533    nouveau_object_del(&screen->compute);
 534    nouveau_object_del(&screen->nvsw);
 535
 536    nouveau_screen_fini(&screen->base);
 537
 538    FREE(screen);
 539 }
 540
 541 static int
 542 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 543                      unsigned size, const uint32_t *data)
 544 {
 545    struct nouveau_pushbuf *push = screen->base.pushbuf;
 546
 547    size /= 4;
 548
 549    assert((pos + size) <= 0x800);
 550
 551    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 552    PUSH_DATA (push, (m - 0x3800) / 8);
 553    PUSH_DATA (push, pos);
 554    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 555    PUSH_DATA (push, pos);
 556    PUSH_DATAp(push, data, size);
 557
 558    return pos + size;
 559 }
 560
 561 static void
 562 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 563 {
 564    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 565    PUSH_DATA (push, 0xff);
 566    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 567    PUSH_DATA (push, 0xff);
 568    PUSH_DATA (push, 0xff);
 569    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 570    PUSH_DATA (push, 0xff);
 571    PUSH_DATA (push, 0xff);
 572    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 573    PUSH_DATA (push, 0x3f);
 574
 575    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 576    PUSH_DATA (push, (3 << 16) | 3);
 577    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 578    PUSH_DATA (push, (2 << 16) | 2);
 579
 580    if (obj_class < GM107_3D_CLASS) {
 581       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 582       PUSH_DATA (push, 0);
 583    }
 584    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 585    PUSH_DATA (push, 0x10);
 586    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 587    PUSH_DATA (push, 0x10);
 588    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 589    PUSH_DATA (push, 0x10);
 590    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 591    PUSH_DATA (push, 0x10);
 592    PUSH_DATA (push, 0x10);
 593    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 594    PUSH_DATA (push, 0x10);
 595    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 596    PUSH_DATA (push, 0xe);
 597
 598    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 599    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 600    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 601    PUSH_DATA (push, 0);
 602    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 603    PUSH_DATA (push, 3);
 604
 605    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 606    PUSH_DATA (push, 0x3fffff);
 607    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 608    PUSH_DATA (push, 1);
 609    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 610    PUSH_DATA (push, 1);
 611
 612    if (obj_class < GM107_3D_CLASS) {
 613       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 614       PUSH_DATA (push, 3);
 615
 616       if (obj_class >= NVE4_3D_CLASS) {
 617          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 618          PUSH_DATA (push, 1);
 619       }
 620    }
 621
 622    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 623     * are supposed to do */
 624 }
 625
 626 static void
 627 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 628 {
 629    struct nvc0_screen *screen = nvc0_screen(pscreen);
 630    struct nouveau_pushbuf *push = screen->base.pushbuf;
 631
 632    /* we need to do it after possible flush in MARK_RING */
 633    *sequence = ++screen->base.fence.sequence;
 634
 635    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 636    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 637    PUSH_DATAh(push, screen->fence.bo->offset);
 638    PUSH_DATA (push, screen->fence.bo->offset);
 639    PUSH_DATA (push, *sequence);
 640    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 641               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 642 }
 643
 644 static u32
 645 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 646 {
 647    struct nvc0_screen *screen = nvc0_screen(pscreen);
 648    return screen->fence.map[0];
 649 }
 650
 651 static int
 652 nvc0_screen_init_compute(struct nvc0_screen *screen)
 653 {
 654    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 655
 656    switch (screen->base.device->chipset & ~0xf) {
 657    case 0xc0:
 658    case 0xd0:
 659       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 660    case 0xe0:
 661    case 0xf0:
 662    case 0x100:
 663    case 0x110:
 664    case 0x120:
 665       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 666    case 0x130:
 667       return 0;
 668    default:
 669       return -1;
 670    }
 671 }
 672
 673 static int
 674 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 675                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 676 {
 677    struct nouveau_bo *bo = NULL;
 678    int ret;
 679    uint64_t size = (lpos + lneg) * 32 + cstack;
 680
 681    if (size >= (1 << 20)) {
 682       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 683       return -1;
 684    }
 685
 686    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 687    size  = align(size, 0x8000);
 688    size *= screen->mp_count;
 689
 690    size = align(size, 1 << 17);
 691
 692    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 693                         NULL, &bo);
 694    if (ret)
 695       return ret;
 696    nouveau_bo_ref(NULL, &screen->tls);
 697    screen->tls = bo;
 698    return 0;
 699 }
 700
 701 int
 702 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 703 {
 704    struct nouveau_pushbuf *push = screen->base.pushbuf;
 705    struct nouveau_bo *bo;
 706    int ret;
 707
 708    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 709                         1 << 17, size, NULL, &bo);
 710    if (ret)
 711       return ret;
 712
 713    nouveau_bo_ref(NULL, &screen->text);
 714    screen->text = bo;
 715
 716    nouveau_heap_destroy(&screen->lib_code);
 717    nouveau_heap_destroy(&screen->text_heap);
 718
 719    /* XXX: getting a page fault at the end of the code buffer every few
 720     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 721     */
 722    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 723
 724    /* update the code segment setup */
 725    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 726    PUSH_DATAh(push, screen->text->offset);
 727    PUSH_DATA (push, screen->text->offset);
 728    if (screen->compute) {
 729       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 730       PUSH_DATAh(push, screen->text->offset);
 731       PUSH_DATA (push, screen->text->offset);
 732    }
 733
 734    return 0;
 735 }
 736
 737 #define FAIL_SCREEN_INIT(str, err)                    \
 738    do {                                               \
 739       NOUVEAU_ERR(str, err);                          \
 740       goto fail;                                      \
 741    } while(0)
 742
 743 struct nouveau_screen *
 744 nvc0_screen_create(struct nouveau_device *dev)
 745 {
 746    struct nvc0_screen *screen;
 747    struct pipe_screen *pscreen;
 748    struct nouveau_object *chan;
 749    struct nouveau_pushbuf *push;
 750    uint64_t value;
 751    uint32_t obj_class;
 752    uint32_t flags;
 753    int ret;
 754    unsigned i;
 755
 756    switch (dev->chipset & ~0xf) {
 757    case 0xc0:
 758    case 0xd0:
 759    case 0xe0:
 760    case 0xf0:
 761    case 0x100:
 762    case 0x110:
 763    case 0x120:
 764    case 0x130:
 765       break;
 766    default:
 767       return NULL;
 768    }
 769
 770    screen = CALLOC_STRUCT(nvc0_screen);
 771    if (!screen)
 772       return NULL;
 773    pscreen = &screen->base.base;
 774    pscreen->destroy = nvc0_screen_destroy;
 775
 776    ret = nouveau_screen_init(&screen->base, dev);
 777    if (ret)
 778       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 779    chan = screen->base.channel;
 780    push = screen->base.pushbuf;
 781    push->user_priv = screen;
 782    push->rsvd_kick = 5;
 783
 784    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 785       PIPE_BIND_SHADER_BUFFER |
 786       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 787       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 788    screen->base.sysmem_bindings |=
 789       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 790
 791    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 792       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 793       screen->base.vidmem_bindings = 0;
 794    }
 795
 796    pscreen->context_create = nvc0_create;
 797    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 798    pscreen->get_param = nvc0_screen_get_param;
 799    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 800    pscreen->get_paramf = nvc0_screen_get_paramf;
 801    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 802    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 803
 804    nvc0_screen_init_resource_functions(pscreen);
 805
 806    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 807    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 808
 809    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 810    if (screen->base.drm->version >= 0x01000202)
 811       flags |= NOUVEAU_BO_COHERENT;
 812
 813    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 814    if (ret)
 815       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 816    nouveau_bo_map(screen->fence.bo, 0, NULL);
 817    screen->fence.map = screen->fence.bo->map;
 818    screen->base.fence.emit = nvc0_screen_fence_emit;
 819    screen->base.fence.update = nvc0_screen_fence_update;
 820
 821
 822    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 823                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 824    if (ret)
 825       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 826
 827    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 828    PUSH_DATA (push, screen->nvsw->handle);
 829
 830    switch (dev->chipset & ~0xf) {
 831    case 0x130:
 832    case 0x120:
 833    case 0x110:
 834    case 0x100:
 835    case 0xf0:
 836       obj_class = NVF0_P2MF_CLASS;
 837       break;
 838    case 0xe0:
 839       obj_class = NVE4_P2MF_CLASS;
 840       break;
 841    default:
 842       obj_class = NVC0_M2MF_CLASS;
 843       break;
 844    }
 845    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 846                             &screen->m2mf);
 847    if (ret)
 848       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 849
 850    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 851    PUSH_DATA (push, screen->m2mf->oclass);
 852    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 853       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 854       PUSH_DATA (push, 0xa0b5);
 855    }
 856
 857    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 858                             &screen->eng2d);
 859    if (ret)
 860       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 861
 862    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 863    PUSH_DATA (push, screen->eng2d->oclass);
 864    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 865    PUSH_DATA (push, 0);
 866    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 867    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 868    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 869    PUSH_DATA (push, 0);
 870    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 871    PUSH_DATA (push, 0);
 872    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 873    PUSH_DATA (push, 0x3f);
 874    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 875    PUSH_DATA (push, 1);
 876    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 877    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 878
 879    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 880    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 881    PUSH_DATA (push, screen->fence.bo->offset + 16);
 882
 883    switch (dev->chipset & ~0xf) {
 884    case 0x130:
 885       obj_class = GP100_3D_CLASS;
 886       break;
 887    case 0x120:
 888       obj_class = GM200_3D_CLASS;
 889       break;
 890    case 0x110:
 891       obj_class = GM107_3D_CLASS;
 892       break;
 893    case 0x100:
 894    case 0xf0:
 895       obj_class = NVF0_3D_CLASS;
 896       break;
 897    case 0xe0:
 898       switch (dev->chipset) {
 899       case 0xea:
 900          obj_class = NVEA_3D_CLASS;
 901          break;
 902       default:
 903          obj_class = NVE4_3D_CLASS;
 904          break;
 905       }
 906       break;
 907    case 0xd0:
 908       obj_class = NVC8_3D_CLASS;
 909       break;
 910    case 0xc0:
 911    default:
 912       switch (dev->chipset) {
 913       case 0xc8:
 914          obj_class = NVC8_3D_CLASS;
 915          break;
 916       case 0xc1:
 917          obj_class = NVC1_3D_CLASS;
 918          break;
 919       default:
 920          obj_class = NVC0_3D_CLASS;
 921          break;
 922       }
 923       break;
 924    }
 925    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 926                             &screen->eng3d);
 927    if (ret)
 928       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 929    screen->base.class_3d = obj_class;
 930
 931    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 932    PUSH_DATA (push, screen->eng3d->oclass);
 933
 934    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 935    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 936
 937    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 938       /* kill shaders after about 1 second (at 100 MHz) */
 939       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 940       PUSH_DATA (push, 0x17);
 941    }
 942
 943    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 944                     screen->base.drm->version >= 0x01000101);
 945    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 946    for (i = 0; i < 8; ++i)
 947       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 948
 949    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 950    PUSH_DATA (push, 1);
 951
 952    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 953    PUSH_DATA (push, 0);
 954    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 955    PUSH_DATA (push, 0);
 956    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 957    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 958    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 959    PUSH_DATA (push, 0);
 960    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 961    PUSH_DATA (push, 1);
 962    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 963    PUSH_DATA (push, 1);
 964    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 965    PUSH_DATA (push, 1);
 966    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 967    PUSH_DATA (push, 0);
 968    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 969    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 970    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 971       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 972    } else {
 973       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 974       PUSH_DATA (push, 15);
 975    }
 976    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 977    PUSH_DATA (push, 8); /* 128 */
 978    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 979    PUSH_DATA (push, 1);
 980    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 981       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 982       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 983    }
 984
 985    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 986
 987    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
 988    if (ret)
 989       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
 990
 991    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
 992                         &screen->uniform_bo);
 993    if (ret)
 994       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
 995
 996    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
 997
 998    for (i = 0; i < 5; ++i) {
 999       /* TIC and TSC entries for each unit (nve4+ only) */
1000       /* auxiliary constants (6 user clip planes, base instance id) */
1001       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1002       PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1003       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1004       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1005       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1006       PUSH_DATA (push, (15 << 4) | 1);
1007       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1008          unsigned j;
1009          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1010          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1011          for (j = 0; j < 8; ++j)
1012             PUSH_DATA(push, j);
1013       } else {
1014          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1015          PUSH_DATA (push, 0x54);
1016       }
1017
1018       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1019       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1020       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1021       PUSH_DATA (push, 0); /* 0 */
1022       PUSH_DATA (push, 0);
1023       PUSH_DATA (push, 1); /* 1 */
1024       PUSH_DATA (push, 0);
1025       PUSH_DATA (push, 0); /* 2 */
1026       PUSH_DATA (push, 1);
1027       PUSH_DATA (push, 1); /* 3 */
1028       PUSH_DATA (push, 1);
1029       PUSH_DATA (push, 2); /* 4 */
1030       PUSH_DATA (push, 0);
1031       PUSH_DATA (push, 3); /* 5 */
1032       PUSH_DATA (push, 0);
1033       PUSH_DATA (push, 2); /* 6 */
1034       PUSH_DATA (push, 1);
1035       PUSH_DATA (push, 3); /* 7 */
1036       PUSH_DATA (push, 1);
1037    }
1038    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1039    PUSH_DATA (push, 0);
1040
1041    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1042    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1043    PUSH_DATA (push, 256);
1044    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1045    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1046    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1047    PUSH_DATA (push, 0);
1048    PUSH_DATAf(push, 0.0f);
1049    PUSH_DATAf(push, 0.0f);
1050    PUSH_DATAf(push, 0.0f);
1051    PUSH_DATAf(push, 0.0f);
1052    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1053    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1054    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1055
1056    if (screen->base.drm->version >= 0x01000101) {
1057       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1058       if (ret)
1059          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1060    } else {
1061       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1062          value = (8 << 8) | 4;
1063       else
1064          value = (16 << 8) | 4;
1065    }
1066    screen->gpc_count = value & 0x000000ff;
1067    screen->mp_count = value >> 8;
1068    screen->mp_count_compute = screen->mp_count;
1069
1070    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1071    if (ret)
1072       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1073
1074    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1075    PUSH_DATAh(push, screen->tls->offset);
1076    PUSH_DATA (push, screen->tls->offset);
1077    PUSH_DATA (push, screen->tls->size >> 32);
1078    PUSH_DATA (push, screen->tls->size);
1079    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1080    PUSH_DATA (push, 0);
1081    /* Reduce likelihood of collision with real buffers by placing the hole at
1082     * the top of the 4G area. This will have to be dealt with for real
1083     * eventually by blocking off that area from the VM.
1084     */
1085    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1086    PUSH_DATA (push, 0xff << 24);
1087
1088    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1089       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1090                            &screen->poly_cache);
1091       if (ret)
1092          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1093
1094       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1095       PUSH_DATAh(push, screen->poly_cache->offset);
1096       PUSH_DATA (push, screen->poly_cache->offset);
1097       PUSH_DATA (push, 3);
1098    }
1099
1100    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1101                         &screen->txc);
1102    if (ret)
1103       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1104
1105    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1106    PUSH_DATAh(push, screen->txc->offset);
1107    PUSH_DATA (push, screen->txc->offset);
1108    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1109    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1110       screen->tic.maxwell = true;
1111       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1112          screen->tic.maxwell =
1113             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1114          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1115       }
1116    }
1117
1118    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1119    PUSH_DATAh(push, screen->txc->offset + 65536);
1120    PUSH_DATA (push, screen->txc->offset + 65536);
1121    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1122
1123    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1124    PUSH_DATA (push, 0);
1125    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1126    PUSH_DATA (push, 0);
1127    PUSH_DATA (push, 0);
1128    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1129    PUSH_DATA (push, 0x3f);
1130
1131    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1132    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1133    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1134    for (i = 0; i < 8 * 2; ++i)
1135       PUSH_DATA(push, 0);
1136    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1137    PUSH_DATA (push, 0);
1138    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1139    PUSH_DATA (push, 0);
1140
1141    /* neither scissors, viewport nor stencil mask should affect clears */
1142    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1143    PUSH_DATA (push, 0);
1144
1145    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1146    PUSH_DATA (push, 1);
1147    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1148       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1149       PUSH_DATAf(push, 0.0f);
1150       PUSH_DATAf(push, 1.0f);
1151    }
1152    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1153    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1154
1155    /* We use scissors instead of exact view volume clipping,
1156     * so they're always enabled.
1157     */
1158    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1159       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1160       PUSH_DATA (push, 1);
1161       PUSH_DATA (push, 8192 << 16);
1162       PUSH_DATA (push, 8192 << 16);
1163    }
1164
1165 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1166
1167    i = 0;
1168    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1169    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1170    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1171    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1172    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1173    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1174    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1175    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1176    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1177    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1178    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1179    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1180    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1181
1182    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1183    PUSH_DATA (push, 1);
1184    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1185    PUSH_DATA (push, 1);
1186    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1187    PUSH_DATA (push, 0x40);
1188    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1189    PUSH_DATA (push, 0);
1190    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1191    PUSH_DATA (push, 0x30);
1192    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1193    PUSH_DATA (push, 3);
1194    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1195    PUSH_DATA (push, 0x20);
1196    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1197    PUSH_DATA (push, 0x00);
1198    screen->save_state.patch_vertices = 3;
1199
1200    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1201    PUSH_DATA (push, 0);
1202    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1203    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1204
1205    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1206
1207    if (nvc0_screen_init_compute(screen))
1208       goto fail;
1209
1210    PUSH_KICK (push);
1211
1212    screen->tic.entries = CALLOC(4096, sizeof(void *));
1213    screen->tsc.entries = screen->tic.entries + 2048;
1214
1215    if (!nvc0_blitter_create(screen))
1216       goto fail;
1217
1218    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1219
1220    return &screen->base;
1221
1222 fail:
1223    screen->base.base.context_create = NULL;
1224    return &screen->base;
1225 }
1226
1227 int
1228 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1229 {
1230    int i = screen->tic.next;
1231
1232    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1233       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1234
1235    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1236
1237    if (screen->tic.entries[i])
1238       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1239
1240    screen->tic.entries[i] = entry;
1241    return i;
1242 }
1243
1244 int
1245 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1246 {
1247    int i = screen->tsc.next;
1248
1249    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1250       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1251
1252    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1253
1254    if (screen->tsc.entries[i])
1255       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1256
1257    screen->tsc.entries[i] = entry;
1258    return i;
1259 }