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nv50,nvc0: bump minimum texture buffer offset alignment
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 if (sample_count > 8)
49 return false;
50 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
51 return false;
52
53 if (!util_format_is_supported(format, bindings))
54 return false;
55
56 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
57 if (util_format_get_blocksizebits(format) == 3 * 32)
58 return false;
59
60 /* transfers & shared are always supported */
61 bindings &= ~(PIPE_BIND_TRANSFER_READ |
62 PIPE_BIND_TRANSFER_WRITE |
63 PIPE_BIND_SHARED);
64
65 return (( nvc0_format_table[format].usage |
66 nvc0_vertex_format[format].usage) & bindings) == bindings;
67 }
68
69 static int
70 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
71 {
72 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
73 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
74
75 switch (param) {
76 /* non-boolean caps */
77 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
78 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
79 return 15;
80 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
81 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
82 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
83 return 2048;
84 case PIPE_CAP_MIN_TEXEL_OFFSET:
85 return -8;
86 case PIPE_CAP_MAX_TEXEL_OFFSET:
87 return 7;
88 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
89 return -32;
90 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
91 return 31;
92 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
93 return 128 * 1024 * 1024;
94 case PIPE_CAP_GLSL_FEATURE_LEVEL:
95 return 410;
96 case PIPE_CAP_MAX_RENDER_TARGETS:
97 return 8;
98 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
99 return 1;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
101 return 4;
102 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
103 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
104 return 128;
105 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
106 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
107 return 1024;
108 case PIPE_CAP_MAX_VERTEX_STREAMS:
109 return 4;
110 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
111 return 2048;
112 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
113 return 256;
114 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
115 return 16; /* 256 for binding as RT, but that's not possible in GL */
116 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
117 return 16;
118 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
119 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
120 case PIPE_CAP_MAX_VIEWPORTS:
121 return NVC0_MAX_VIEWPORTS;
122 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
123 return 4;
124 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
125 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
126 case PIPE_CAP_ENDIANNESS:
127 return PIPE_ENDIAN_LITTLE;
128 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
129 return 30;
130
131 /* supported caps */
132 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
133 case PIPE_CAP_TEXTURE_SWIZZLE:
134 case PIPE_CAP_TEXTURE_SHADOW_MAP:
135 case PIPE_CAP_NPOT_TEXTURES:
136 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
137 case PIPE_CAP_ANISOTROPIC_FILTER:
138 case PIPE_CAP_SEAMLESS_CUBE_MAP:
139 case PIPE_CAP_CUBE_MAP_ARRAY:
140 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
141 case PIPE_CAP_TEXTURE_MULTISAMPLE:
142 case PIPE_CAP_TWO_SIDED_STENCIL:
143 case PIPE_CAP_DEPTH_CLIP_DISABLE:
144 case PIPE_CAP_POINT_SPRITE:
145 case PIPE_CAP_TGSI_TEXCOORD:
146 case PIPE_CAP_SM3:
147 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
148 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
149 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
150 case PIPE_CAP_QUERY_TIMESTAMP:
151 case PIPE_CAP_QUERY_TIME_ELAPSED:
152 case PIPE_CAP_OCCLUSION_QUERY:
153 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
154 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
155 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
156 case PIPE_CAP_INDEP_BLEND_ENABLE:
157 case PIPE_CAP_INDEP_BLEND_FUNC:
158 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
159 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
160 case PIPE_CAP_PRIMITIVE_RESTART:
161 case PIPE_CAP_TGSI_INSTANCEID:
162 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
163 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
164 case PIPE_CAP_CONDITIONAL_RENDER:
165 case PIPE_CAP_TEXTURE_BARRIER:
166 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
167 case PIPE_CAP_START_INSTANCE:
168 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
169 case PIPE_CAP_DRAW_INDIRECT:
170 case PIPE_CAP_USER_CONSTANT_BUFFERS:
171 case PIPE_CAP_USER_INDEX_BUFFERS:
172 case PIPE_CAP_USER_VERTEX_BUFFERS:
173 case PIPE_CAP_TEXTURE_QUERY_LOD:
174 case PIPE_CAP_SAMPLE_SHADING:
175 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
176 case PIPE_CAP_TEXTURE_GATHER_SM5:
177 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
178 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
179 case PIPE_CAP_SAMPLER_VIEW_TARGET:
180 case PIPE_CAP_CLIP_HALFZ:
181 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
182 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
183 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
184 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
185 case PIPE_CAP_DEPTH_BOUNDS_TEST:
186 case PIPE_CAP_TGSI_TXQS:
187 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
188 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
189 case PIPE_CAP_SHAREABLE_SHADERS:
190 case PIPE_CAP_CLEAR_TEXTURE:
191 case PIPE_CAP_DRAW_PARAMETERS:
192 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
193 case PIPE_CAP_MULTI_DRAW_INDIRECT:
194 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
195 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
196 case PIPE_CAP_QUERY_BUFFER_OBJECT:
197 return 1;
198 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
199 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
200 case PIPE_CAP_COMPUTE:
201 if (debug_get_bool_option("NVF0_COMPUTE", false))
202 return 1;
203 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
204 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
205 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
206
207 /* unsupported caps */
208 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
209 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
210 case PIPE_CAP_SHADER_STENCIL_EXPORT:
211 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
212 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
213 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
214 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
215 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
216 case PIPE_CAP_FAKE_SW_MSAA:
217 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
218 case PIPE_CAP_VERTEXID_NOBASE:
219 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
220 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
221 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
222 case PIPE_CAP_INVALIDATE_BUFFER:
223 case PIPE_CAP_GENERATE_MIPMAP:
224 case PIPE_CAP_STRING_MARKER:
225 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
226 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
227 case PIPE_CAP_QUERY_MEMORY_INFO:
228 return 0;
229
230 case PIPE_CAP_VENDOR_ID:
231 return 0x10de;
232 case PIPE_CAP_DEVICE_ID: {
233 uint64_t device_id;
234 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
235 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
236 return -1;
237 }
238 return device_id;
239 }
240 case PIPE_CAP_ACCELERATED:
241 return 1;
242 case PIPE_CAP_VIDEO_MEMORY:
243 return dev->vram_size >> 20;
244 case PIPE_CAP_UMA:
245 return 0;
246 }
247
248 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
249 return 0;
250 }
251
252 static int
253 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
254 enum pipe_shader_cap param)
255 {
256 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
257
258 switch (shader) {
259 case PIPE_SHADER_VERTEX:
260 case PIPE_SHADER_GEOMETRY:
261 case PIPE_SHADER_FRAGMENT:
262 break;
263 case PIPE_SHADER_TESS_CTRL:
264 case PIPE_SHADER_TESS_EVAL:
265 if (class_3d >= GM107_3D_CLASS)
266 return 0;
267 break;
268 case PIPE_SHADER_COMPUTE:
269 if (!debug_get_bool_option("NVF0_COMPUTE", false))
270 if (class_3d > NVE4_3D_CLASS)
271 return 0;
272 break;
273 default:
274 return 0;
275 }
276
277 switch (param) {
278 case PIPE_SHADER_CAP_PREFERRED_IR:
279 return PIPE_SHADER_IR_TGSI;
280 case PIPE_SHADER_CAP_SUPPORTED_IRS:
281 if (class_3d >= NVE4_3D_CLASS)
282 return 0;
283 return 1 << PIPE_SHADER_IR_TGSI;
284 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
285 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
286 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
287 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
288 return 16384;
289 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
290 return 16;
291 case PIPE_SHADER_CAP_MAX_INPUTS:
292 if (shader == PIPE_SHADER_VERTEX)
293 return 32;
294 /* NOTE: These only count our slots for GENERIC varyings.
295 * The address space may be larger, but the actual hard limit seems to be
296 * less than what the address space layout permits, so don't add TEXCOORD,
297 * COLOR, etc. here.
298 */
299 if (shader == PIPE_SHADER_FRAGMENT)
300 return 0x1f0 / 16;
301 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
302 * and excludes 0x60 per-patch inputs.
303 */
304 return 0x200 / 16;
305 case PIPE_SHADER_CAP_MAX_OUTPUTS:
306 return 32;
307 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
308 return 65536;
309 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
310 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
311 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
312 return NVC0_MAX_PIPE_CONSTBUFS;
313 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
314 return shader != PIPE_SHADER_FRAGMENT;
315 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
316 return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
317 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
318 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
319 return 1;
320 case PIPE_SHADER_CAP_MAX_PREDS:
321 return 0;
322 case PIPE_SHADER_CAP_MAX_TEMPS:
323 return NVC0_CAP_MAX_PROGRAM_TEMPS;
324 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
325 return 1;
326 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
327 return 0;
328 case PIPE_SHADER_CAP_SUBROUTINES:
329 return 1;
330 case PIPE_SHADER_CAP_INTEGERS:
331 return 1;
332 case PIPE_SHADER_CAP_DOUBLES:
333 return 1;
334 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
335 return 1;
336 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
337 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
338 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
339 return 0;
340 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
341 return NVC0_MAX_BUFFERS;
342 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
343 return 16; /* would be 32 in linked (OpenGL-style) mode */
344 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
345 return 16; /* XXX not sure if more are really safe */
346 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
347 return 32;
348 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
349 return 0;
350 default:
351 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
352 return 0;
353 }
354 }
355
356 static float
357 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
358 {
359 switch (param) {
360 case PIPE_CAPF_MAX_LINE_WIDTH:
361 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
362 return 10.0f;
363 case PIPE_CAPF_MAX_POINT_WIDTH:
364 return 63.0f;
365 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
366 return 63.375f;
367 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
368 return 16.0f;
369 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
370 return 15.0f;
371 case PIPE_CAPF_GUARD_BAND_LEFT:
372 case PIPE_CAPF_GUARD_BAND_TOP:
373 return 0.0f;
374 case PIPE_CAPF_GUARD_BAND_RIGHT:
375 case PIPE_CAPF_GUARD_BAND_BOTTOM:
376 return 0.0f; /* that or infinity */
377 }
378
379 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
380 return 0.0f;
381 }
382
383 static int
384 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
385 enum pipe_compute_cap param, void *data)
386 {
387 struct nvc0_screen *screen = nvc0_screen(pscreen);
388 const uint16_t obj_class = screen->compute->oclass;
389
390 #define RET(x) do { \
391 if (data) \
392 memcpy(data, x, sizeof(x)); \
393 return sizeof(x); \
394 } while (0)
395
396 switch (param) {
397 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
398 RET((uint64_t []) { 3 });
399 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
400 if (obj_class >= NVE4_COMPUTE_CLASS) {
401 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
402 } else {
403 RET(((uint64_t []) { 65535, 65535, 65535 }));
404 }
405 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
406 RET(((uint64_t []) { 1024, 1024, 64 }));
407 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
408 RET((uint64_t []) { 1024 });
409 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
410 RET((uint64_t []) { 1ULL << 40 });
411 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
412 RET((uint64_t []) { 48 << 10 });
413 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
414 RET((uint64_t []) { 512 << 10 });
415 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
416 RET((uint64_t []) { 4096 });
417 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
418 RET((uint32_t []) { 32 });
419 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
420 RET((uint64_t []) { 1ULL << 40 });
421 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
422 RET((uint32_t []) { 0 });
423 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
424 RET((uint32_t []) { screen->mp_count_compute });
425 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
426 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
427 default:
428 return 0;
429 }
430
431 #undef RET
432 }
433
434 static void
435 nvc0_screen_destroy(struct pipe_screen *pscreen)
436 {
437 struct nvc0_screen *screen = nvc0_screen(pscreen);
438
439 if (!nouveau_drm_screen_unref(&screen->base))
440 return;
441
442 if (screen->base.fence.current) {
443 struct nouveau_fence *current = NULL;
444
445 /* nouveau_fence_wait will create a new current fence, so wait on the
446 * _current_ one, and remove both.
447 */
448 nouveau_fence_ref(screen->base.fence.current, &current);
449 nouveau_fence_wait(current, NULL);
450 nouveau_fence_ref(NULL, &current);
451 nouveau_fence_ref(NULL, &screen->base.fence.current);
452 }
453 if (screen->base.pushbuf)
454 screen->base.pushbuf->user_priv = NULL;
455
456 if (screen->blitter)
457 nvc0_blitter_destroy(screen);
458 if (screen->pm.prog) {
459 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
460 nvc0_program_destroy(NULL, screen->pm.prog);
461 FREE(screen->pm.prog);
462 }
463
464 nouveau_bo_ref(NULL, &screen->text);
465 nouveau_bo_ref(NULL, &screen->uniform_bo);
466 nouveau_bo_ref(NULL, &screen->tls);
467 nouveau_bo_ref(NULL, &screen->txc);
468 nouveau_bo_ref(NULL, &screen->fence.bo);
469 nouveau_bo_ref(NULL, &screen->poly_cache);
470 nouveau_bo_ref(NULL, &screen->parm);
471
472 nouveau_heap_destroy(&screen->lib_code);
473 nouveau_heap_destroy(&screen->text_heap);
474
475 FREE(screen->tic.entries);
476
477 nouveau_object_del(&screen->eng3d);
478 nouveau_object_del(&screen->eng2d);
479 nouveau_object_del(&screen->m2mf);
480 nouveau_object_del(&screen->compute);
481 nouveau_object_del(&screen->nvsw);
482
483 nouveau_screen_fini(&screen->base);
484
485 FREE(screen);
486 }
487
488 static int
489 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
490 unsigned size, const uint32_t *data)
491 {
492 struct nouveau_pushbuf *push = screen->base.pushbuf;
493
494 size /= 4;
495
496 assert((pos + size) <= 0x800);
497
498 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
499 PUSH_DATA (push, (m - 0x3800) / 8);
500 PUSH_DATA (push, pos);
501 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
502 PUSH_DATA (push, pos);
503 PUSH_DATAp(push, data, size);
504
505 return pos + size;
506 }
507
508 static void
509 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
510 {
511 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
512 PUSH_DATA (push, 0xff);
513 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
514 PUSH_DATA (push, 0xff);
515 PUSH_DATA (push, 0xff);
516 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
517 PUSH_DATA (push, 0xff);
518 PUSH_DATA (push, 0xff);
519 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
520 PUSH_DATA (push, 0x3f);
521
522 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
523 PUSH_DATA (push, (3 << 16) | 3);
524 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
525 PUSH_DATA (push, (2 << 16) | 2);
526
527 if (obj_class < GM107_3D_CLASS) {
528 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
529 PUSH_DATA (push, 0);
530 }
531 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
532 PUSH_DATA (push, 0x10);
533 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
534 PUSH_DATA (push, 0x10);
535 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
536 PUSH_DATA (push, 0x10);
537 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
538 PUSH_DATA (push, 0x10);
539 PUSH_DATA (push, 0x10);
540 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
541 PUSH_DATA (push, 0x10);
542 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
543 PUSH_DATA (push, 0xe);
544
545 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
546 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
547 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
548 PUSH_DATA (push, 0);
549 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
550 PUSH_DATA (push, 3);
551
552 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
553 PUSH_DATA (push, 0x3fffff);
554 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
555 PUSH_DATA (push, 1);
556 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
557 PUSH_DATA (push, 1);
558
559 if (obj_class < GM107_3D_CLASS) {
560 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
561 PUSH_DATA (push, 3);
562
563 if (obj_class >= NVE4_3D_CLASS) {
564 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
565 PUSH_DATA (push, 1);
566 }
567 }
568
569 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
570 * are supposed to do */
571 }
572
573 static void
574 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
575 {
576 struct nvc0_screen *screen = nvc0_screen(pscreen);
577 struct nouveau_pushbuf *push = screen->base.pushbuf;
578
579 /* we need to do it after possible flush in MARK_RING */
580 *sequence = ++screen->base.fence.sequence;
581
582 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
583 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
584 PUSH_DATAh(push, screen->fence.bo->offset);
585 PUSH_DATA (push, screen->fence.bo->offset);
586 PUSH_DATA (push, *sequence);
587 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
588 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
589 }
590
591 static u32
592 nvc0_screen_fence_update(struct pipe_screen *pscreen)
593 {
594 struct nvc0_screen *screen = nvc0_screen(pscreen);
595 return screen->fence.map[0];
596 }
597
598 static int
599 nvc0_screen_init_compute(struct nvc0_screen *screen)
600 {
601 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
602
603 switch (screen->base.device->chipset & ~0xf) {
604 case 0xc0:
605 case 0xd0:
606 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
607 case 0xe0:
608 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
609 case 0xf0:
610 case 0x100:
611 case 0x110:
612 if (debug_get_bool_option("NVF0_COMPUTE", false))
613 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
614 case 0x120:
615 return 0;
616 default:
617 return -1;
618 }
619 }
620
621 bool
622 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
623 uint32_t lpos, uint32_t lneg, uint32_t cstack)
624 {
625 struct nouveau_bo *bo = NULL;
626 int ret;
627 uint64_t size = (lpos + lneg) * 32 + cstack;
628
629 if (size >= (1 << 20)) {
630 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
631 return false;
632 }
633
634 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
635 size = align(size, 0x8000);
636 size *= screen->mp_count;
637
638 size = align(size, 1 << 17);
639
640 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
641 NULL, &bo);
642 if (ret) {
643 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
644 return false;
645 }
646 nouveau_bo_ref(NULL, &screen->tls);
647 screen->tls = bo;
648 return true;
649 }
650
651 #define FAIL_SCREEN_INIT(str, err) \
652 do { \
653 NOUVEAU_ERR(str, err); \
654 goto fail; \
655 } while(0)
656
657 struct nouveau_screen *
658 nvc0_screen_create(struct nouveau_device *dev)
659 {
660 struct nvc0_screen *screen;
661 struct pipe_screen *pscreen;
662 struct nouveau_object *chan;
663 struct nouveau_pushbuf *push;
664 uint64_t value;
665 uint32_t obj_class;
666 uint32_t flags;
667 int ret;
668 unsigned i;
669
670 switch (dev->chipset & ~0xf) {
671 case 0xc0:
672 case 0xd0:
673 case 0xe0:
674 case 0xf0:
675 case 0x100:
676 case 0x110:
677 case 0x120:
678 break;
679 default:
680 return NULL;
681 }
682
683 screen = CALLOC_STRUCT(nvc0_screen);
684 if (!screen)
685 return NULL;
686 pscreen = &screen->base.base;
687 pscreen->destroy = nvc0_screen_destroy;
688
689 ret = nouveau_screen_init(&screen->base, dev);
690 if (ret) {
691 nvc0_screen_destroy(pscreen);
692 return NULL;
693 }
694 chan = screen->base.channel;
695 push = screen->base.pushbuf;
696 push->user_priv = screen;
697 push->rsvd_kick = 5;
698
699 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
700 PIPE_BIND_SHADER_BUFFER |
701 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
702 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
703 screen->base.sysmem_bindings |=
704 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
705
706 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
707 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
708 screen->base.vidmem_bindings = 0;
709 }
710
711 pscreen->context_create = nvc0_create;
712 pscreen->is_format_supported = nvc0_screen_is_format_supported;
713 pscreen->get_param = nvc0_screen_get_param;
714 pscreen->get_shader_param = nvc0_screen_get_shader_param;
715 pscreen->get_paramf = nvc0_screen_get_paramf;
716 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
717 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
718
719 nvc0_screen_init_resource_functions(pscreen);
720
721 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
722 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
723
724 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
725 if (screen->base.drm->version >= 0x01000202)
726 flags |= NOUVEAU_BO_COHERENT;
727
728 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
729 if (ret)
730 goto fail;
731 nouveau_bo_map(screen->fence.bo, 0, NULL);
732 screen->fence.map = screen->fence.bo->map;
733 screen->base.fence.emit = nvc0_screen_fence_emit;
734 screen->base.fence.update = nvc0_screen_fence_update;
735
736
737 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
738 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
739 if (ret)
740 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
741
742 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
743 PUSH_DATA (push, screen->nvsw->handle);
744
745 switch (dev->chipset & ~0xf) {
746 case 0x120:
747 case 0x110:
748 case 0x100:
749 case 0xf0:
750 obj_class = NVF0_P2MF_CLASS;
751 break;
752 case 0xe0:
753 obj_class = NVE4_P2MF_CLASS;
754 break;
755 default:
756 obj_class = NVC0_M2MF_CLASS;
757 break;
758 }
759 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
760 &screen->m2mf);
761 if (ret)
762 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
763
764 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
765 PUSH_DATA (push, screen->m2mf->oclass);
766 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
767 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
768 PUSH_DATA (push, 0xa0b5);
769 }
770
771 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
772 &screen->eng2d);
773 if (ret)
774 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
775
776 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
777 PUSH_DATA (push, screen->eng2d->oclass);
778 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
779 PUSH_DATA (push, 0);
780 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
781 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
782 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
783 PUSH_DATA (push, 0);
784 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
785 PUSH_DATA (push, 0);
786 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
787 PUSH_DATA (push, 0x3f);
788 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
789 PUSH_DATA (push, 1);
790 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
791 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
792
793 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
794 PUSH_DATAh(push, screen->fence.bo->offset + 16);
795 PUSH_DATA (push, screen->fence.bo->offset + 16);
796
797 switch (dev->chipset & ~0xf) {
798 case 0x120:
799 obj_class = GM200_3D_CLASS;
800 break;
801 case 0x110:
802 obj_class = GM107_3D_CLASS;
803 break;
804 case 0x100:
805 case 0xf0:
806 obj_class = NVF0_3D_CLASS;
807 break;
808 case 0xe0:
809 switch (dev->chipset) {
810 case 0xea:
811 obj_class = NVEA_3D_CLASS;
812 break;
813 default:
814 obj_class = NVE4_3D_CLASS;
815 break;
816 }
817 break;
818 case 0xd0:
819 obj_class = NVC8_3D_CLASS;
820 break;
821 case 0xc0:
822 default:
823 switch (dev->chipset) {
824 case 0xc8:
825 obj_class = NVC8_3D_CLASS;
826 break;
827 case 0xc1:
828 obj_class = NVC1_3D_CLASS;
829 break;
830 default:
831 obj_class = NVC0_3D_CLASS;
832 break;
833 }
834 break;
835 }
836 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
837 &screen->eng3d);
838 if (ret)
839 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
840 screen->base.class_3d = obj_class;
841
842 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
843 PUSH_DATA (push, screen->eng3d->oclass);
844
845 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
846 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
847
848 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
849 /* kill shaders after about 1 second (at 100 MHz) */
850 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
851 PUSH_DATA (push, 0x17);
852 }
853
854 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
855 screen->base.drm->version >= 0x01000101);
856 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
857 for (i = 0; i < 8; ++i)
858 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
859
860 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
861 PUSH_DATA (push, 1);
862
863 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
864 PUSH_DATA (push, 0);
865 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
866 PUSH_DATA (push, 0);
867 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
868 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
869 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
870 PUSH_DATA (push, 0);
871 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
872 PUSH_DATA (push, 1);
873 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
874 PUSH_DATA (push, 1);
875 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
876 PUSH_DATA (push, 1);
877 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
878 PUSH_DATA (push, 0);
879 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
880 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
881 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
882 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
883 } else {
884 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
885 PUSH_DATA (push, 15);
886 }
887 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
888 PUSH_DATA (push, 8); /* 128 */
889 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
890 PUSH_DATA (push, 1);
891 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
892 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
893 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
894 }
895
896 nvc0_magic_3d_init(push, screen->eng3d->oclass);
897
898 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
899 &screen->text);
900 if (ret)
901 goto fail;
902
903 /* XXX: getting a page fault at the end of the code buffer every few
904 * launches, don't use the last 256 bytes to work around them - prefetch ?
905 */
906 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
907
908 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
909 &screen->uniform_bo);
910 if (ret)
911 goto fail;
912
913 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
914
915 for (i = 0; i < 5; ++i) {
916 /* TIC and TSC entries for each unit (nve4+ only) */
917 /* auxiliary constants (6 user clip planes, base instance id) */
918 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
919 PUSH_DATA (push, 1024);
920 PUSH_DATAh(push, screen->uniform_bo->offset + (6 << 16) + (i << 10));
921 PUSH_DATA (push, screen->uniform_bo->offset + (6 << 16) + (i << 10));
922 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
923 PUSH_DATA (push, (15 << 4) | 1);
924 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
925 unsigned j;
926 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
927 PUSH_DATA (push, 0);
928 for (j = 0; j < 8; ++j)
929 PUSH_DATA(push, j);
930 } else {
931 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
932 PUSH_DATA (push, 0x54);
933 }
934 }
935 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
936 PUSH_DATA (push, 0);
937
938 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
939 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
940 PUSH_DATA (push, 256);
941 PUSH_DATAh(push, screen->uniform_bo->offset + (6 << 16) + (6 << 10));
942 PUSH_DATA (push, screen->uniform_bo->offset + (6 << 16) + (6 << 10));
943 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
944 PUSH_DATA (push, 0);
945 PUSH_DATAf(push, 0.0f);
946 PUSH_DATAf(push, 0.0f);
947 PUSH_DATAf(push, 0.0f);
948 PUSH_DATAf(push, 0.0f);
949 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
950 PUSH_DATAh(push, screen->uniform_bo->offset + (6 << 16) + (6 << 10));
951 PUSH_DATA (push, screen->uniform_bo->offset + (6 << 16) + (6 << 10));
952
953 if (screen->base.drm->version >= 0x01000101) {
954 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
955 if (ret) {
956 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
957 goto fail;
958 }
959 } else {
960 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
961 value = (8 << 8) | 4;
962 else
963 value = (16 << 8) | 4;
964 }
965 screen->gpc_count = value & 0x000000ff;
966 screen->mp_count = value >> 8;
967 screen->mp_count_compute = screen->mp_count;
968
969 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
970
971 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
972 PUSH_DATAh(push, screen->text->offset);
973 PUSH_DATA (push, screen->text->offset);
974 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
975 PUSH_DATAh(push, screen->tls->offset);
976 PUSH_DATA (push, screen->tls->offset);
977 PUSH_DATA (push, screen->tls->size >> 32);
978 PUSH_DATA (push, screen->tls->size);
979 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
980 PUSH_DATA (push, 0);
981 /* Reduce likelihood of collision with real buffers by placing the hole at
982 * the top of the 4G area. This will have to be dealt with for real
983 * eventually by blocking off that area from the VM.
984 */
985 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
986 PUSH_DATA (push, 0xff << 24);
987
988 if (screen->eng3d->oclass < GM107_3D_CLASS) {
989 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
990 &screen->poly_cache);
991 if (ret)
992 goto fail;
993
994 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
995 PUSH_DATAh(push, screen->poly_cache->offset);
996 PUSH_DATA (push, screen->poly_cache->offset);
997 PUSH_DATA (push, 3);
998 }
999
1000 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1001 &screen->txc);
1002 if (ret)
1003 goto fail;
1004
1005 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1006 PUSH_DATAh(push, screen->txc->offset);
1007 PUSH_DATA (push, screen->txc->offset);
1008 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1009 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1010 screen->tic.maxwell = true;
1011 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1012 screen->tic.maxwell =
1013 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1014 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1015 }
1016 }
1017
1018 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1019 PUSH_DATAh(push, screen->txc->offset + 65536);
1020 PUSH_DATA (push, screen->txc->offset + 65536);
1021 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1022
1023 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1024 PUSH_DATA (push, 0);
1025 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1026 PUSH_DATA (push, 0);
1027 PUSH_DATA (push, 0);
1028 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1029 PUSH_DATA (push, 0x3f);
1030
1031 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1032 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1033 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1034 for (i = 0; i < 8 * 2; ++i)
1035 PUSH_DATA(push, 0);
1036 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1037 PUSH_DATA (push, 0);
1038 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1039 PUSH_DATA (push, 0);
1040
1041 /* neither scissors, viewport nor stencil mask should affect clears */
1042 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1043 PUSH_DATA (push, 0);
1044
1045 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1046 PUSH_DATA (push, 1);
1047 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1048 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1049 PUSH_DATAf(push, 0.0f);
1050 PUSH_DATAf(push, 1.0f);
1051 }
1052 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1053 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1054
1055 /* We use scissors instead of exact view volume clipping,
1056 * so they're always enabled.
1057 */
1058 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1059 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1060 PUSH_DATA (push, 1);
1061 PUSH_DATA (push, 8192 << 16);
1062 PUSH_DATA (push, 8192 << 16);
1063 }
1064
1065 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1066
1067 i = 0;
1068 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1069 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1070 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1071 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1072 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1073 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1074 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1075 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1076 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1077 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1078 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1079 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1080 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1081
1082 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1083 PUSH_DATA (push, 1);
1084 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1085 PUSH_DATA (push, 1);
1086 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1087 PUSH_DATA (push, 0x40);
1088 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1089 PUSH_DATA (push, 0);
1090 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1091 PUSH_DATA (push, 0x30);
1092 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1093 PUSH_DATA (push, 3);
1094 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1095 PUSH_DATA (push, 0x20);
1096 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1097 PUSH_DATA (push, 0x00);
1098 screen->save_state.patch_vertices = 3;
1099
1100 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1101 PUSH_DATA (push, 0);
1102 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1103 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1104
1105 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1106
1107 if (nvc0_screen_init_compute(screen))
1108 goto fail;
1109
1110 PUSH_KICK (push);
1111
1112 screen->tic.entries = CALLOC(4096, sizeof(void *));
1113 screen->tsc.entries = screen->tic.entries + 2048;
1114
1115 if (!nvc0_blitter_create(screen))
1116 goto fail;
1117
1118 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1119
1120 return &screen->base;
1121
1122 fail:
1123 screen->base.base.context_create = NULL;
1124 return &screen->base;
1125 }
1126
1127 int
1128 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1129 {
1130 int i = screen->tic.next;
1131
1132 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1133 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1134
1135 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1136
1137 if (screen->tic.entries[i])
1138 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1139
1140 screen->tic.entries[i] = entry;
1141 return i;
1142 }
1143
1144 int
1145 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1146 {
1147 int i = screen->tsc.next;
1148
1149 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1150 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1151
1152 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1153
1154 if (screen->tsc.entries[i])
1155 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1156
1157 screen->tsc.entries[i] = entry;
1158 return i;
1159 }