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nvc0: organize screen caps
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/mme/com9097.mme.h"
36
37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
39 #endif
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 if (sample_count > 8)
49 return FALSE;
50 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
51 return FALSE;
52
53 if (!util_format_is_supported(format, bindings))
54 return FALSE;
55
56 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
57 if (util_format_get_blocksizebits(format) == 3 * 32)
58 return FALSE;
59
60 /* transfers & shared are always supported */
61 bindings &= ~(PIPE_BIND_TRANSFER_READ |
62 PIPE_BIND_TRANSFER_WRITE |
63 PIPE_BIND_SHARED);
64
65 return (nvc0_format_table[format].usage & bindings) == bindings;
66 }
67
68 static int
69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
70 {
71 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
72
73 switch (param) {
74 /* non-boolean caps */
75 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
76 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
77 return 15;
78 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
79 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
80 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
81 return 2048;
82 case PIPE_CAP_MIN_TEXEL_OFFSET:
83 return -8;
84 case PIPE_CAP_MAX_TEXEL_OFFSET:
85 return 7;
86 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
87 return -32;
88 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
89 return 31;
90 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
91 return 65536;
92 case PIPE_CAP_GLSL_FEATURE_LEVEL:
93 return 330;
94 case PIPE_CAP_MAX_RENDER_TARGETS:
95 return 8;
96 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
97 return 1;
98 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
99 return 4;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
101 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
102 return 128;
103 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
104 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
105 return 1024;
106 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
107 return 256;
108 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
109 return 1; /* 256 for binding as RT, but that's not possible in GL */
110 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
111 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
112 case PIPE_CAP_MAX_VIEWPORTS:
113 return NVC0_MAX_VIEWPORTS;
114 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
115 return 4;
116 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
117 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
118 case PIPE_CAP_ENDIANNESS:
119 return PIPE_ENDIAN_LITTLE;
120
121 /* supported caps */
122 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
123 case PIPE_CAP_TEXTURE_SWIZZLE:
124 case PIPE_CAP_TEXTURE_SHADOW_MAP:
125 case PIPE_CAP_NPOT_TEXTURES:
126 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
127 case PIPE_CAP_ANISOTROPIC_FILTER:
128 case PIPE_CAP_SEAMLESS_CUBE_MAP:
129 case PIPE_CAP_CUBE_MAP_ARRAY:
130 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
131 case PIPE_CAP_TEXTURE_MULTISAMPLE:
132 case PIPE_CAP_TWO_SIDED_STENCIL:
133 case PIPE_CAP_DEPTH_CLIP_DISABLE:
134 case PIPE_CAP_POINT_SPRITE:
135 case PIPE_CAP_TGSI_TEXCOORD:
136 case PIPE_CAP_SM3:
137 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
138 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
139 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
140 case PIPE_CAP_QUERY_TIMESTAMP:
141 case PIPE_CAP_QUERY_TIME_ELAPSED:
142 case PIPE_CAP_OCCLUSION_QUERY:
143 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
144 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
145 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
146 case PIPE_CAP_INDEP_BLEND_ENABLE:
147 case PIPE_CAP_INDEP_BLEND_FUNC:
148 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
149 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
150 case PIPE_CAP_PRIMITIVE_RESTART:
151 case PIPE_CAP_TGSI_INSTANCEID:
152 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
153 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
154 case PIPE_CAP_CONDITIONAL_RENDER:
155 case PIPE_CAP_TEXTURE_BARRIER:
156 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
157 case PIPE_CAP_START_INSTANCE:
158 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
159 case PIPE_CAP_USER_CONSTANT_BUFFERS:
160 case PIPE_CAP_USER_INDEX_BUFFERS:
161 case PIPE_CAP_USER_VERTEX_BUFFERS:
162 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
163 case PIPE_CAP_TEXTURE_QUERY_LOD:
164 case PIPE_CAP_SAMPLE_SHADING:
165 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
166 case PIPE_CAP_TEXTURE_GATHER_SM5:
167 return 1;
168 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
169 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
170 case PIPE_CAP_COMPUTE:
171 return (class_3d == NVE4_3D_CLASS) ? 1 : 0;
172
173 /* unsupported caps */
174 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
175 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
176 case PIPE_CAP_SHADER_STENCIL_EXPORT:
177 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
178 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
179 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
180 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
181 case PIPE_CAP_TGSI_VS_LAYER:
182 case PIPE_CAP_FAKE_SW_MSAA:
183 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
184 return 0;
185 }
186
187 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
188 return 0;
189 }
190
191 static int
192 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
193 enum pipe_shader_cap param)
194 {
195 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
196
197 switch (shader) {
198 case PIPE_SHADER_VERTEX:
199 /*
200 case PIPE_SHADER_TESSELLATION_CONTROL:
201 case PIPE_SHADER_TESSELLATION_EVALUATION:
202 */
203 case PIPE_SHADER_GEOMETRY:
204 case PIPE_SHADER_FRAGMENT:
205 break;
206 case PIPE_SHADER_COMPUTE:
207 if (class_3d != NVE4_3D_CLASS)
208 return 0;
209 break;
210 default:
211 return 0;
212 }
213
214 switch (param) {
215 case PIPE_SHADER_CAP_PREFERRED_IR:
216 return PIPE_SHADER_IR_TGSI;
217 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
218 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
219 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
220 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
221 return 16384;
222 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
223 return 16;
224 case PIPE_SHADER_CAP_MAX_INPUTS:
225 if (shader == PIPE_SHADER_VERTEX)
226 return 32;
227 /* NOTE: These only count our slots for GENERIC varyings.
228 * The address space may be larger, but the actual hard limit seems to be
229 * less than what the address space layout permits, so don't add TEXCOORD,
230 * COLOR, etc. here.
231 */
232 if (shader == PIPE_SHADER_FRAGMENT)
233 return 0x1f0 / 16;
234 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
235 * and excludes 0x60 per-patch inputs.
236 */
237 return 0x200 / 16;
238 case PIPE_SHADER_CAP_MAX_CONSTS:
239 return 65536 / 16;
240 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
241 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
242 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
243 return NVC0_MAX_PIPE_CONSTBUFS;
244 case PIPE_SHADER_CAP_MAX_ADDRS:
245 return 1;
246 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
247 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
248 return shader != PIPE_SHADER_FRAGMENT;
249 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
250 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
251 return 1;
252 case PIPE_SHADER_CAP_MAX_PREDS:
253 return 0;
254 case PIPE_SHADER_CAP_MAX_TEMPS:
255 return NVC0_CAP_MAX_PROGRAM_TEMPS;
256 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
257 return 1;
258 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
259 return 0;
260 case PIPE_SHADER_CAP_SUBROUTINES:
261 return 1;
262 case PIPE_SHADER_CAP_INTEGERS:
263 return 1;
264 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
265 return 16; /* would be 32 in linked (OpenGL-style) mode */
266 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
267 return 16; /* XXX not sure if more are really safe */
268 default:
269 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
270 return 0;
271 }
272 }
273
274 static float
275 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
276 {
277 switch (param) {
278 case PIPE_CAPF_MAX_LINE_WIDTH:
279 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
280 return 10.0f;
281 case PIPE_CAPF_MAX_POINT_WIDTH:
282 return 63.0f;
283 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
284 return 63.375f;
285 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
286 return 16.0f;
287 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
288 return 15.0f;
289 case PIPE_CAPF_GUARD_BAND_LEFT:
290 case PIPE_CAPF_GUARD_BAND_TOP:
291 return 0.0f;
292 case PIPE_CAPF_GUARD_BAND_RIGHT:
293 case PIPE_CAPF_GUARD_BAND_BOTTOM:
294 return 0.0f; /* that or infinity */
295 }
296
297 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
298 return 0.0f;
299 }
300
301 static int
302 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
303 enum pipe_compute_cap param, void *data)
304 {
305 uint64_t *data64 = (uint64_t *)data;
306 const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
307
308 switch (param) {
309 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
310 data64[0] = 3;
311 return 8;
312 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
313 data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
314 data64[1] = 65535;
315 data64[2] = 65535;
316 return 24;
317 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
318 data64[0] = 1024;
319 data64[1] = 1024;
320 data64[2] = 64;
321 return 24;
322 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
323 data64[0] = 1024;
324 return 8;
325 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
326 data64[0] = (uint64_t)1 << 40;
327 return 8;
328 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
329 data64[0] = 48 << 10;
330 return 8;
331 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
332 data64[0] = 512 << 10;
333 return 8;
334 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
335 data64[0] = 4096;
336 return 8;
337 default:
338 return 0;
339 }
340 }
341
342 static void
343 nvc0_screen_destroy(struct pipe_screen *pscreen)
344 {
345 struct nvc0_screen *screen = nvc0_screen(pscreen);
346
347 if (!nouveau_drm_screen_unref(&screen->base))
348 return;
349
350 if (screen->base.fence.current) {
351 struct nouveau_fence *current = NULL;
352
353 /* nouveau_fence_wait will create a new current fence, so wait on the
354 * _current_ one, and remove both.
355 */
356 nouveau_fence_ref(screen->base.fence.current, &current);
357 nouveau_fence_wait(current);
358 nouveau_fence_ref(NULL, &current);
359 nouveau_fence_ref(NULL, &screen->base.fence.current);
360 }
361 if (screen->base.pushbuf)
362 screen->base.pushbuf->user_priv = NULL;
363
364 if (screen->blitter)
365 nvc0_blitter_destroy(screen);
366 if (screen->pm.prog) {
367 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
368 nvc0_program_destroy(NULL, screen->pm.prog);
369 }
370
371 nouveau_bo_ref(NULL, &screen->text);
372 nouveau_bo_ref(NULL, &screen->uniform_bo);
373 nouveau_bo_ref(NULL, &screen->tls);
374 nouveau_bo_ref(NULL, &screen->txc);
375 nouveau_bo_ref(NULL, &screen->fence.bo);
376 nouveau_bo_ref(NULL, &screen->poly_cache);
377 nouveau_bo_ref(NULL, &screen->parm);
378
379 nouveau_heap_destroy(&screen->lib_code);
380 nouveau_heap_destroy(&screen->text_heap);
381
382 FREE(screen->tic.entries);
383
384 nouveau_mm_destroy(screen->mm_VRAM_fe0);
385
386 nouveau_object_del(&screen->eng3d);
387 nouveau_object_del(&screen->eng2d);
388 nouveau_object_del(&screen->m2mf);
389 nouveau_object_del(&screen->compute);
390 nouveau_object_del(&screen->nvsw);
391
392 nouveau_screen_fini(&screen->base);
393
394 FREE(screen);
395 }
396
397 static int
398 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
399 unsigned size, const uint32_t *data)
400 {
401 struct nouveau_pushbuf *push = screen->base.pushbuf;
402
403 size /= 4;
404
405 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
406 PUSH_DATA (push, (m - 0x3800) / 8);
407 PUSH_DATA (push, pos);
408 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
409 PUSH_DATA (push, pos);
410 PUSH_DATAp(push, data, size);
411
412 return pos + size;
413 }
414
415 static void
416 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
417 {
418 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
419 PUSH_DATA (push, 0xff);
420 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
421 PUSH_DATA (push, 0xff);
422 PUSH_DATA (push, 0xff);
423 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
424 PUSH_DATA (push, 0xff);
425 PUSH_DATA (push, 0xff);
426 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
427 PUSH_DATA (push, 0x3f);
428
429 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
430 PUSH_DATA (push, (3 << 16) | 3);
431 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
432 PUSH_DATA (push, (2 << 16) | 2);
433 BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
434 PUSH_DATA (push, 1);
435
436 if (obj_class < GM107_3D_CLASS) {
437 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
438 PUSH_DATA (push, 0);
439 }
440 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
441 PUSH_DATA (push, 0x10);
442 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
443 PUSH_DATA (push, 0x10);
444 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
445 PUSH_DATA (push, 0x10);
446 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
447 PUSH_DATA (push, 0x10);
448 PUSH_DATA (push, 0x10);
449 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
450 PUSH_DATA (push, 0x10);
451 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
452 PUSH_DATA (push, 0xe);
453
454 BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
455 PUSH_DATA (push, 1 << 12);
456 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
457 PUSH_DATA (push, 0);
458 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
459 PUSH_DATA (push, 3);
460
461 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
462 PUSH_DATA (push, 0x3fffff);
463 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
464 PUSH_DATA (push, 1);
465 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
466 PUSH_DATA (push, 1);
467
468 if (obj_class < GM107_3D_CLASS) {
469 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
470 PUSH_DATA (push, 3);
471
472 if (obj_class >= NVE4_3D_CLASS) {
473 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
474 PUSH_DATA (push, 1);
475 }
476 }
477
478 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
479 * are supposed to do */
480 }
481
482 static void
483 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
484 {
485 struct nvc0_screen *screen = nvc0_screen(pscreen);
486 struct nouveau_pushbuf *push = screen->base.pushbuf;
487
488 /* we need to do it after possible flush in MARK_RING */
489 *sequence = ++screen->base.fence.sequence;
490
491 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
492 PUSH_DATAh(push, screen->fence.bo->offset);
493 PUSH_DATA (push, screen->fence.bo->offset);
494 PUSH_DATA (push, *sequence);
495 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
496 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
497 }
498
499 static u32
500 nvc0_screen_fence_update(struct pipe_screen *pscreen)
501 {
502 struct nvc0_screen *screen = nvc0_screen(pscreen);
503 return screen->fence.map[0];
504 }
505
506 static int
507 nvc0_screen_init_compute(struct nvc0_screen *screen)
508 {
509 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
510
511 switch (screen->base.device->chipset & ~0xf) {
512 case 0xc0:
513 case 0xd0:
514 /* Using COMPUTE has weird effects on 3D state, we need to
515 * investigate this further before enabling it by default.
516 */
517 if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
518 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
519 return 0;
520 case 0xe0:
521 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
522 case 0xf0:
523 case 0x100:
524 case 0x110:
525 return 0;
526 default:
527 return -1;
528 }
529 }
530
531 boolean
532 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
533 uint32_t lpos, uint32_t lneg, uint32_t cstack)
534 {
535 struct nouveau_bo *bo = NULL;
536 int ret;
537 uint64_t size = (lpos + lneg) * 32 + cstack;
538
539 if (size >= (1 << 20)) {
540 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
541 return FALSE;
542 }
543
544 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
545 size = align(size, 0x8000);
546 size *= screen->mp_count;
547
548 size = align(size, 1 << 17);
549
550 ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
551 NULL, &bo);
552 if (ret) {
553 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
554 return FALSE;
555 }
556 nouveau_bo_ref(NULL, &screen->tls);
557 screen->tls = bo;
558 return TRUE;
559 }
560
561 #define FAIL_SCREEN_INIT(str, err) \
562 do { \
563 NOUVEAU_ERR(str, err); \
564 nvc0_screen_destroy(pscreen); \
565 return NULL; \
566 } while(0)
567
568 struct pipe_screen *
569 nvc0_screen_create(struct nouveau_device *dev)
570 {
571 struct nvc0_screen *screen;
572 struct pipe_screen *pscreen;
573 struct nouveau_object *chan;
574 struct nouveau_pushbuf *push;
575 uint64_t value;
576 uint32_t obj_class;
577 int ret;
578 unsigned i;
579 union nouveau_bo_config mm_config;
580
581 switch (dev->chipset & ~0xf) {
582 case 0xc0:
583 case 0xd0:
584 case 0xe0:
585 case 0xf0:
586 case 0x100:
587 case 0x110:
588 break;
589 default:
590 return NULL;
591 }
592
593 screen = CALLOC_STRUCT(nvc0_screen);
594 if (!screen)
595 return NULL;
596 pscreen = &screen->base.base;
597
598 ret = nouveau_screen_init(&screen->base, dev);
599 if (ret) {
600 nvc0_screen_destroy(pscreen);
601 return NULL;
602 }
603 chan = screen->base.channel;
604 push = screen->base.pushbuf;
605 push->user_priv = screen;
606 push->rsvd_kick = 5;
607
608 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
609 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
610 screen->base.sysmem_bindings |=
611 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
612
613 pscreen->destroy = nvc0_screen_destroy;
614 pscreen->context_create = nvc0_create;
615 pscreen->is_format_supported = nvc0_screen_is_format_supported;
616 pscreen->get_param = nvc0_screen_get_param;
617 pscreen->get_shader_param = nvc0_screen_get_shader_param;
618 pscreen->get_paramf = nvc0_screen_get_paramf;
619 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
620
621 nvc0_screen_init_resource_functions(pscreen);
622
623 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
624 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
625
626 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
627 &screen->fence.bo);
628 if (ret)
629 goto fail;
630 nouveau_bo_map(screen->fence.bo, 0, NULL);
631 screen->fence.map = screen->fence.bo->map;
632 screen->base.fence.emit = nvc0_screen_fence_emit;
633 screen->base.fence.update = nvc0_screen_fence_update;
634
635
636 ret = nouveau_object_new(chan,
637 (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
638 NULL, 0, &screen->nvsw);
639 if (ret)
640 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
641
642
643 switch (dev->chipset & ~0xf) {
644 case 0x110:
645 case 0x100:
646 case 0xf0:
647 obj_class = NVF0_P2MF_CLASS;
648 break;
649 case 0xe0:
650 obj_class = NVE4_P2MF_CLASS;
651 break;
652 default:
653 obj_class = NVC0_M2MF_CLASS;
654 break;
655 }
656 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
657 &screen->m2mf);
658 if (ret)
659 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
660
661 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
662 PUSH_DATA (push, screen->m2mf->oclass);
663 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
664 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
665 PUSH_DATA (push, 0xa0b5);
666 }
667
668 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
669 &screen->eng2d);
670 if (ret)
671 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
672
673 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
674 PUSH_DATA (push, screen->eng2d->oclass);
675 BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
676 PUSH_DATA (push, 0);
677 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
678 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
679 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
680 PUSH_DATA (push, 0);
681 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
682 PUSH_DATA (push, 0);
683 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
684 PUSH_DATA (push, 0x3f);
685 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
686 PUSH_DATA (push, 1);
687 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
688 PUSH_DATA (push, NVC0_2D_COND_MODE_ALWAYS);
689
690 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
691 PUSH_DATAh(push, screen->fence.bo->offset + 16);
692 PUSH_DATA (push, screen->fence.bo->offset + 16);
693
694 switch (dev->chipset & ~0xf) {
695 case 0x110:
696 obj_class = GM107_3D_CLASS;
697 break;
698 case 0x100:
699 case 0xf0:
700 obj_class = NVF0_3D_CLASS;
701 break;
702 case 0xe0:
703 switch (dev->chipset) {
704 case 0xea:
705 obj_class = NVEA_3D_CLASS;
706 break;
707 default:
708 obj_class = NVE4_3D_CLASS;
709 break;
710 }
711 break;
712 case 0xd0:
713 obj_class = NVC8_3D_CLASS;
714 break;
715 case 0xc0:
716 default:
717 switch (dev->chipset) {
718 case 0xc8:
719 obj_class = NVC8_3D_CLASS;
720 break;
721 case 0xc1:
722 obj_class = NVC1_3D_CLASS;
723 break;
724 default:
725 obj_class = NVC0_3D_CLASS;
726 break;
727 }
728 break;
729 }
730 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
731 &screen->eng3d);
732 if (ret)
733 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
734 screen->base.class_3d = obj_class;
735
736 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
737 PUSH_DATA (push, screen->eng3d->oclass);
738
739 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
740 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
741
742 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
743 /* kill shaders after about 1 second (at 100 MHz) */
744 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
745 PUSH_DATA (push, 0x17);
746 }
747
748 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
749 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
750 for (i = 0; i < 8; ++i)
751 PUSH_DATA(push, dev->drm_version >= 0x01000101);
752
753 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
754 PUSH_DATA (push, 1);
755
756 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
757 PUSH_DATA (push, 0);
758 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
759 PUSH_DATA (push, 0);
760 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
761 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
762 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
763 PUSH_DATA (push, 0);
764 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
765 PUSH_DATA (push, 1);
766 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
767 PUSH_DATA (push, 0);
768 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
769 PUSH_DATA (push, 1);
770 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
771 PUSH_DATA (push, 0);
772 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
773 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
774 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
775 } else {
776 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
777 PUSH_DATA (push, 15);
778 }
779 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
780 PUSH_DATA (push, 8); /* 128 */
781 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
782 PUSH_DATA (push, 1);
783 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
784 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
785 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
786 }
787
788 nvc0_magic_3d_init(push, screen->eng3d->oclass);
789
790 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
791 &screen->text);
792 if (ret)
793 goto fail;
794
795 /* XXX: getting a page fault at the end of the code buffer every few
796 * launches, don't use the last 256 bytes to work around them - prefetch ?
797 */
798 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
799
800 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
801 &screen->uniform_bo);
802 if (ret)
803 goto fail;
804
805 PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
806
807 for (i = 0; i < 5; ++i) {
808 /* TIC and TSC entries for each unit (nve4+ only) */
809 /* auxiliary constants (6 user clip planes, base instance id) */
810 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
811 PUSH_DATA (push, 512);
812 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
813 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
814 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
815 PUSH_DATA (push, (15 << 4) | 1);
816 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
817 unsigned j;
818 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
819 PUSH_DATA (push, 0);
820 for (j = 0; j < 8; ++j)
821 PUSH_DATA(push, j);
822 } else {
823 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
824 PUSH_DATA (push, 0x54);
825 }
826 }
827 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
828 PUSH_DATA (push, 0);
829
830 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
831 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
832 PUSH_DATA (push, 256);
833 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
834 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
835 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
836 PUSH_DATA (push, 0);
837 PUSH_DATAf(push, 0.0f);
838 PUSH_DATAf(push, 0.0f);
839 PUSH_DATAf(push, 0.0f);
840 PUSH_DATAf(push, 0.0f);
841 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
842 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
843 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
844
845 if (dev->drm_version >= 0x01000101) {
846 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
847 if (ret) {
848 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
849 goto fail;
850 }
851 } else {
852 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
853 value = (8 << 8) | 4;
854 else
855 value = (16 << 8) | 4;
856 }
857 screen->mp_count = value >> 8;
858 screen->mp_count_compute = screen->mp_count;
859
860 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
861
862 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
863 PUSH_DATAh(push, screen->text->offset);
864 PUSH_DATA (push, screen->text->offset);
865 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
866 PUSH_DATAh(push, screen->tls->offset);
867 PUSH_DATA (push, screen->tls->offset);
868 PUSH_DATA (push, screen->tls->size >> 32);
869 PUSH_DATA (push, screen->tls->size);
870 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
871 PUSH_DATA (push, 0);
872 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
873 PUSH_DATA (push, 0);
874
875 if (screen->eng3d->oclass < GM107_3D_CLASS) {
876 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
877 &screen->poly_cache);
878 if (ret)
879 goto fail;
880
881 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
882 PUSH_DATAh(push, screen->poly_cache->offset);
883 PUSH_DATA (push, screen->poly_cache->offset);
884 PUSH_DATA (push, 3);
885 }
886
887 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
888 &screen->txc);
889 if (ret)
890 goto fail;
891
892 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
893 PUSH_DATAh(push, screen->txc->offset);
894 PUSH_DATA (push, screen->txc->offset);
895 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
896
897 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
898 PUSH_DATAh(push, screen->txc->offset + 65536);
899 PUSH_DATA (push, screen->txc->offset + 65536);
900 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
901
902 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
903 PUSH_DATA (push, 0);
904 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
905 PUSH_DATA (push, 0);
906 PUSH_DATA (push, 0);
907 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
908 PUSH_DATA (push, 0x3f);
909
910 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
911 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
912 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
913 for (i = 0; i < 8 * 2; ++i)
914 PUSH_DATA(push, 0);
915 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
916 PUSH_DATA (push, 0);
917 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
918 PUSH_DATA (push, 0);
919
920 /* neither scissors, viewport nor stencil mask should affect clears */
921 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
922 PUSH_DATA (push, 0);
923
924 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
925 PUSH_DATA (push, 1);
926 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
927 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
928 PUSH_DATAf(push, 0.0f);
929 PUSH_DATAf(push, 1.0f);
930 }
931 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
932 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
933
934 /* We use scissors instead of exact view volume clipping,
935 * so they're always enabled.
936 */
937 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
938 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
939 PUSH_DATA (push, 1);
940 PUSH_DATA (push, 8192 << 16);
941 PUSH_DATA (push, 8192 << 16);
942 }
943
944 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
945
946 i = 0;
947 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
948 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
949 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
950 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
951 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
952 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
953 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
954
955 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
956 PUSH_DATA (push, 1);
957 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
958 PUSH_DATA (push, 1);
959 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
960 PUSH_DATA (push, 0x40);
961 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
962 PUSH_DATA (push, 0);
963 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
964 PUSH_DATA (push, 0x30);
965 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
966 PUSH_DATA (push, 3);
967 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
968 PUSH_DATA (push, 0x20);
969 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
970 PUSH_DATA (push, 0x00);
971
972 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
973 PUSH_DATA (push, 0);
974 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
975 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
976
977 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
978
979 if (nvc0_screen_init_compute(screen))
980 goto fail;
981
982 PUSH_KICK (push);
983
984 screen->tic.entries = CALLOC(4096, sizeof(void *));
985 screen->tsc.entries = screen->tic.entries + 2048;
986
987 mm_config.nvc0.tile_mode = 0;
988 mm_config.nvc0.memtype = 0xfe0;
989 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
990
991 if (!nvc0_blitter_create(screen))
992 goto fail;
993
994 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
995
996 return pscreen;
997
998 fail:
999 nvc0_screen_destroy(pscreen);
1000 return NULL;
1001 }
1002
1003 int
1004 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1005 {
1006 int i = screen->tic.next;
1007
1008 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1009 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1010
1011 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1012
1013 if (screen->tic.entries[i])
1014 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1015
1016 screen->tic.entries[i] = entry;
1017 return i;
1018 }
1019
1020 int
1021 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1022 {
1023 int i = screen->tsc.next;
1024
1025 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1026 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1027
1028 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1029
1030 if (screen->tsc.entries[i])
1031 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1032
1033 screen->tsc.entries[i] = entry;
1034 return i;
1035 }