src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    const struct util_format_description *desc = util_format_description(format);
  49
  50    if (sample_count > 8)
  51       return false;
  52    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  53       return false;
  54
  55    /* Short-circuit the rest of the logic -- this is used by the state tracker
  56     * to determine valid MS levels in a no-attachments scenario.
  57     */
  58    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  59       return true;
  60
  61    if (!util_format_is_supported(format, bindings))
  62       return false;
  63
  64    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  65       if (util_format_get_blocksizebits(format) == 3 * 32)
  66          return false;
  67
  68    if (bindings & PIPE_BIND_LINEAR)
  69       if (util_format_is_depth_or_stencil(format) ||
  70           (target != PIPE_TEXTURE_1D &&
  71            target != PIPE_TEXTURE_2D &&
  72            target != PIPE_TEXTURE_RECT) ||
  73           sample_count > 1)
  74          return false;
  75
  76    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  77     */
  78    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  79         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  80        /* The claim is that this should work on GM107 but it doesn't. Need to
  81         * test further and figure out if it's a nouveau issue or a HW one.
  82        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  83         */
  84        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  85       return false;
  86
  87    /* transfers & shared are always supported */
  88    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  89                  PIPE_BIND_TRANSFER_WRITE |
  90                  PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    return (( nvc0_format_table[format].usage |
  94             nvc0_vertex_format[format].usage) & bindings) == bindings;
  95 }
  96
  97 static int
  98 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  99 {
 100    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 101    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 102
 103    switch (param) {
 104    /* non-boolean caps */
 105    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 106    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 107       return 15;
 108    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 109       return 12;
 110    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 111       return 2048;
 112    case PIPE_CAP_MIN_TEXEL_OFFSET:
 113       return -8;
 114    case PIPE_CAP_MAX_TEXEL_OFFSET:
 115       return 7;
 116    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 117       return -32;
 118    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 119       return 31;
 120    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 121       return 128 * 1024 * 1024;
 122    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 123       if (class_3d <= NVF0_3D_CLASS)
 124          return 430;
 125       return 410;
 126    case PIPE_CAP_MAX_RENDER_TARGETS:
 127       return 8;
 128    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 129       return 1;
 130    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 131       return 4;
 132    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 133    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 134       return 128;
 135    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 136    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 137       return 1024;
 138    case PIPE_CAP_MAX_VERTEX_STREAMS:
 139       return 4;
 140    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 141       return 2048;
 142    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 143       return 256;
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145       return 16; /* 256 for binding as RT, but that's not possible in GL */
 146    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 147       return 16;
 148    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 149       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 150    case PIPE_CAP_MAX_VIEWPORTS:
 151       return NVC0_MAX_VIEWPORTS;
 152    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 153       return 4;
 154    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 155       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 156    case PIPE_CAP_ENDIANNESS:
 157       return PIPE_ENDIAN_LITTLE;
 158    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 159       return 30;
 160    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 161       return NVC0_MAX_WINDOW_RECTANGLES;
 162
 163    /* supported caps */
 164    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 165    case PIPE_CAP_TEXTURE_SWIZZLE:
 166    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 167    case PIPE_CAP_NPOT_TEXTURES:
 168    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 169    case PIPE_CAP_ANISOTROPIC_FILTER:
 170    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 171    case PIPE_CAP_CUBE_MAP_ARRAY:
 172    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 173    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 174    case PIPE_CAP_TWO_SIDED_STENCIL:
 175    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 176    case PIPE_CAP_POINT_SPRITE:
 177    case PIPE_CAP_TGSI_TEXCOORD:
 178    case PIPE_CAP_SM3:
 179    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 180    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 181    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 182    case PIPE_CAP_QUERY_TIMESTAMP:
 183    case PIPE_CAP_QUERY_TIME_ELAPSED:
 184    case PIPE_CAP_OCCLUSION_QUERY:
 185    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 186    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 187    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 188    case PIPE_CAP_INDEP_BLEND_ENABLE:
 189    case PIPE_CAP_INDEP_BLEND_FUNC:
 190    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 191    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 192    case PIPE_CAP_PRIMITIVE_RESTART:
 193    case PIPE_CAP_TGSI_INSTANCEID:
 194    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 195    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 196    case PIPE_CAP_CONDITIONAL_RENDER:
 197    case PIPE_CAP_TEXTURE_BARRIER:
 198    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 199    case PIPE_CAP_START_INSTANCE:
 200    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 201    case PIPE_CAP_DRAW_INDIRECT:
 202    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 203    case PIPE_CAP_USER_INDEX_BUFFERS:
 204    case PIPE_CAP_USER_VERTEX_BUFFERS:
 205    case PIPE_CAP_TEXTURE_QUERY_LOD:
 206    case PIPE_CAP_SAMPLE_SHADING:
 207    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 208    case PIPE_CAP_TEXTURE_GATHER_SM5:
 209    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 210    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 211    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 212    case PIPE_CAP_CLIP_HALFZ:
 213    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 214    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 215    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 216    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 217    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 218    case PIPE_CAP_TGSI_TXQS:
 219    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 220    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 221    case PIPE_CAP_SHAREABLE_SHADERS:
 222    case PIPE_CAP_CLEAR_TEXTURE:
 223    case PIPE_CAP_DRAW_PARAMETERS:
 224    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 225    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 226    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 227    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 228    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 229    case PIPE_CAP_INVALIDATE_BUFFER:
 230    case PIPE_CAP_STRING_MARKER:
 231    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 232    case PIPE_CAP_CULL_DISTANCE:
 233    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 234    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 235    case PIPE_CAP_COMPUTE:
 236    case PIPE_CAP_TGSI_VOTE:
 237       return 1;
 238    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 239       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 240    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 241       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 242
 243    /* unsupported caps */
 244    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 245    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 246    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 247    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 248    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 249    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 250    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 251    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 252    case PIPE_CAP_FAKE_SW_MSAA:
 253    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 254    case PIPE_CAP_VERTEXID_NOBASE:
 255    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 256    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 257    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 258    case PIPE_CAP_GENERATE_MIPMAP:
 259    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 260    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 261    case PIPE_CAP_QUERY_MEMORY_INFO:
 262    case PIPE_CAP_PCI_GROUP:
 263    case PIPE_CAP_PCI_BUS:
 264    case PIPE_CAP_PCI_DEVICE:
 265    case PIPE_CAP_PCI_FUNCTION:
 266       return 0;
 267
 268    case PIPE_CAP_VENDOR_ID:
 269       return 0x10de;
 270    case PIPE_CAP_DEVICE_ID: {
 271       uint64_t device_id;
 272       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 273          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 274          return -1;
 275       }
 276       return device_id;
 277    }
 278    case PIPE_CAP_ACCELERATED:
 279       return 1;
 280    case PIPE_CAP_VIDEO_MEMORY:
 281       return dev->vram_size >> 20;
 282    case PIPE_CAP_UMA:
 283       return 0;
 284    }
 285
 286    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 287    return 0;
 288 }
 289
 290 static int
 291 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 292                              enum pipe_shader_cap param)
 293 {
 294    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 295
 296    switch (shader) {
 297    case PIPE_SHADER_VERTEX:
 298    case PIPE_SHADER_GEOMETRY:
 299    case PIPE_SHADER_FRAGMENT:
 300    case PIPE_SHADER_COMPUTE:
 301       break;
 302    case PIPE_SHADER_TESS_CTRL:
 303    case PIPE_SHADER_TESS_EVAL:
 304       if (class_3d >= GM107_3D_CLASS)
 305          return 0;
 306       break;
 307    default:
 308       return 0;
 309    }
 310
 311    switch (param) {
 312    case PIPE_SHADER_CAP_PREFERRED_IR:
 313       return PIPE_SHADER_IR_TGSI;
 314    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 315       return 1 << PIPE_SHADER_IR_TGSI;
 316    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 317    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 318    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 319    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 320       return 16384;
 321    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 322       return 16;
 323    case PIPE_SHADER_CAP_MAX_INPUTS:
 324       if (shader == PIPE_SHADER_VERTEX)
 325          return 32;
 326       /* NOTE: These only count our slots for GENERIC varyings.
 327        * The address space may be larger, but the actual hard limit seems to be
 328        * less than what the address space layout permits, so don't add TEXCOORD,
 329        * COLOR, etc. here.
 330        */
 331       if (shader == PIPE_SHADER_FRAGMENT)
 332          return 0x1f0 / 16;
 333       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 334        * and excludes 0x60 per-patch inputs.
 335        */
 336       return 0x200 / 16;
 337    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 338       return 32;
 339    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 340       return 65536;
 341    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 342       return NVC0_MAX_PIPE_CONSTBUFS;
 343    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 344       return shader != PIPE_SHADER_FRAGMENT;
 345    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 346       return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
 347    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 348    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 349       return 1;
 350    case PIPE_SHADER_CAP_MAX_PREDS:
 351       return 0;
 352    case PIPE_SHADER_CAP_MAX_TEMPS:
 353       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 354    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 355       return 1;
 356    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 357       return 1;
 358    case PIPE_SHADER_CAP_SUBROUTINES:
 359       return 1;
 360    case PIPE_SHADER_CAP_INTEGERS:
 361       return 1;
 362    case PIPE_SHADER_CAP_DOUBLES:
 363       return 1;
 364    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 365       return 1;
 366    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 367       return 1;
 368    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 369    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 370       return 0;
 371    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 372       return NVC0_MAX_BUFFERS;
 373    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 374       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 375    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 376       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 377    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 378       return 32;
 379    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 380       if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
 381          return NVC0_MAX_IMAGES;
 382       if (class_3d < NVE4_3D_CLASS)
 383          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 384             return NVC0_MAX_IMAGES;
 385       return 0;
 386    default:
 387       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 388       return 0;
 389    }
 390 }
 391
 392 static float
 393 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 394 {
 395    switch (param) {
 396    case PIPE_CAPF_MAX_LINE_WIDTH:
 397    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 398       return 10.0f;
 399    case PIPE_CAPF_MAX_POINT_WIDTH:
 400       return 63.0f;
 401    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 402       return 63.375f;
 403    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 404       return 16.0f;
 405    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 406       return 15.0f;
 407    case PIPE_CAPF_GUARD_BAND_LEFT:
 408    case PIPE_CAPF_GUARD_BAND_TOP:
 409       return 0.0f;
 410    case PIPE_CAPF_GUARD_BAND_RIGHT:
 411    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 412       return 0.0f; /* that or infinity */
 413    }
 414
 415    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 416    return 0.0f;
 417 }
 418
 419 static int
 420 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 421                               enum pipe_shader_ir ir_type,
 422                               enum pipe_compute_cap param, void *data)
 423 {
 424    struct nvc0_screen *screen = nvc0_screen(pscreen);
 425    const uint16_t obj_class = screen->compute->oclass;
 426
 427 #define RET(x) do {                  \
 428    if (data)                         \
 429       memcpy(data, x, sizeof(x));    \
 430    return sizeof(x);                 \
 431 } while (0)
 432
 433    switch (param) {
 434    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 435       RET((uint64_t []) { 3 });
 436    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 437       if (obj_class >= NVE4_COMPUTE_CLASS) {
 438          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 439       } else {
 440          RET(((uint64_t []) { 65535, 65535, 65535 }));
 441       }
 442    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 443       RET(((uint64_t []) { 1024, 1024, 64 }));
 444    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 445       RET((uint64_t []) { 1024 });
 446    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 447       RET((uint64_t []) { 1ULL << 40 });
 448    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 449       switch (obj_class) {
 450       case GM200_COMPUTE_CLASS:
 451          RET((uint64_t []) { 96 << 10 });
 452          break;
 453       case GM107_COMPUTE_CLASS:
 454          RET((uint64_t []) { 64 << 10 });
 455          break;
 456       default:
 457          RET((uint64_t []) { 48 << 10 });
 458          break;
 459       }
 460    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 461       RET((uint64_t []) { 512 << 10 });
 462    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 463       RET((uint64_t []) { 4096 });
 464    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 465       RET((uint32_t []) { 32 });
 466    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 467       RET((uint64_t []) { 1ULL << 40 });
 468    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 469       RET((uint32_t []) { 0 });
 470    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 471       RET((uint32_t []) { screen->mp_count_compute });
 472    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 473       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 474    default:
 475       return 0;
 476    }
 477
 478 #undef RET
 479 }
 480
 481 static void
 482 nvc0_screen_destroy(struct pipe_screen *pscreen)
 483 {
 484    struct nvc0_screen *screen = nvc0_screen(pscreen);
 485
 486    if (!nouveau_drm_screen_unref(&screen->base))
 487       return;
 488
 489    if (screen->base.fence.current) {
 490       struct nouveau_fence *current = NULL;
 491
 492       /* nouveau_fence_wait will create a new current fence, so wait on the
 493        * _current_ one, and remove both.
 494        */
 495       nouveau_fence_ref(screen->base.fence.current, &current);
 496       nouveau_fence_wait(current, NULL);
 497       nouveau_fence_ref(NULL, &current);
 498       nouveau_fence_ref(NULL, &screen->base.fence.current);
 499    }
 500    if (screen->base.pushbuf)
 501       screen->base.pushbuf->user_priv = NULL;
 502
 503    if (screen->blitter)
 504       nvc0_blitter_destroy(screen);
 505    if (screen->pm.prog) {
 506       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 507       nvc0_program_destroy(NULL, screen->pm.prog);
 508       FREE(screen->pm.prog);
 509    }
 510
 511    nouveau_bo_ref(NULL, &screen->text);
 512    nouveau_bo_ref(NULL, &screen->uniform_bo);
 513    nouveau_bo_ref(NULL, &screen->tls);
 514    nouveau_bo_ref(NULL, &screen->txc);
 515    nouveau_bo_ref(NULL, &screen->fence.bo);
 516    nouveau_bo_ref(NULL, &screen->poly_cache);
 517
 518    nouveau_heap_destroy(&screen->lib_code);
 519    nouveau_heap_destroy(&screen->text_heap);
 520
 521    FREE(screen->tic.entries);
 522
 523    nouveau_object_del(&screen->eng3d);
 524    nouveau_object_del(&screen->eng2d);
 525    nouveau_object_del(&screen->m2mf);
 526    nouveau_object_del(&screen->compute);
 527    nouveau_object_del(&screen->nvsw);
 528
 529    nouveau_screen_fini(&screen->base);
 530
 531    FREE(screen);
 532 }
 533
 534 static int
 535 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 536                      unsigned size, const uint32_t *data)
 537 {
 538    struct nouveau_pushbuf *push = screen->base.pushbuf;
 539
 540    size /= 4;
 541
 542    assert((pos + size) <= 0x800);
 543
 544    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 545    PUSH_DATA (push, (m - 0x3800) / 8);
 546    PUSH_DATA (push, pos);
 547    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 548    PUSH_DATA (push, pos);
 549    PUSH_DATAp(push, data, size);
 550
 551    return pos + size;
 552 }
 553
 554 static void
 555 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 556 {
 557    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 558    PUSH_DATA (push, 0xff);
 559    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 560    PUSH_DATA (push, 0xff);
 561    PUSH_DATA (push, 0xff);
 562    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 563    PUSH_DATA (push, 0xff);
 564    PUSH_DATA (push, 0xff);
 565    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 566    PUSH_DATA (push, 0x3f);
 567
 568    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 569    PUSH_DATA (push, (3 << 16) | 3);
 570    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 571    PUSH_DATA (push, (2 << 16) | 2);
 572
 573    if (obj_class < GM107_3D_CLASS) {
 574       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 575       PUSH_DATA (push, 0);
 576    }
 577    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 578    PUSH_DATA (push, 0x10);
 579    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 580    PUSH_DATA (push, 0x10);
 581    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 582    PUSH_DATA (push, 0x10);
 583    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 584    PUSH_DATA (push, 0x10);
 585    PUSH_DATA (push, 0x10);
 586    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 587    PUSH_DATA (push, 0x10);
 588    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 589    PUSH_DATA (push, 0xe);
 590
 591    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 592    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 593    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 594    PUSH_DATA (push, 0);
 595    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 596    PUSH_DATA (push, 3);
 597
 598    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 599    PUSH_DATA (push, 0x3fffff);
 600    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 601    PUSH_DATA (push, 1);
 602    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 603    PUSH_DATA (push, 1);
 604
 605    if (obj_class < GM107_3D_CLASS) {
 606       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 607       PUSH_DATA (push, 3);
 608
 609       if (obj_class >= NVE4_3D_CLASS) {
 610          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 611          PUSH_DATA (push, 1);
 612       }
 613    }
 614
 615    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 616     * are supposed to do */
 617 }
 618
 619 static void
 620 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 621 {
 622    struct nvc0_screen *screen = nvc0_screen(pscreen);
 623    struct nouveau_pushbuf *push = screen->base.pushbuf;
 624
 625    /* we need to do it after possible flush in MARK_RING */
 626    *sequence = ++screen->base.fence.sequence;
 627
 628    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 629    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 630    PUSH_DATAh(push, screen->fence.bo->offset);
 631    PUSH_DATA (push, screen->fence.bo->offset);
 632    PUSH_DATA (push, *sequence);
 633    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 634               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 635 }
 636
 637 static u32
 638 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 639 {
 640    struct nvc0_screen *screen = nvc0_screen(pscreen);
 641    return screen->fence.map[0];
 642 }
 643
 644 static int
 645 nvc0_screen_init_compute(struct nvc0_screen *screen)
 646 {
 647    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 648
 649    switch (screen->base.device->chipset & ~0xf) {
 650    case 0xc0:
 651    case 0xd0:
 652       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 653    case 0xe0:
 654    case 0xf0:
 655    case 0x100:
 656    case 0x110:
 657    case 0x120:
 658       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 659    default:
 660       return -1;
 661    }
 662 }
 663
 664 bool
 665 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 666                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 667 {
 668    struct nouveau_bo *bo = NULL;
 669    int ret;
 670    uint64_t size = (lpos + lneg) * 32 + cstack;
 671
 672    if (size >= (1 << 20)) {
 673       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 674       return false;
 675    }
 676
 677    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 678    size  = align(size, 0x8000);
 679    size *= screen->mp_count;
 680
 681    size = align(size, 1 << 17);
 682
 683    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 684                         NULL, &bo);
 685    if (ret) {
 686       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 687       return false;
 688    }
 689    nouveau_bo_ref(NULL, &screen->tls);
 690    screen->tls = bo;
 691    return true;
 692 }
 693
 694 #define FAIL_SCREEN_INIT(str, err)                    \
 695    do {                                               \
 696       NOUVEAU_ERR(str, err);                          \
 697       goto fail;                                      \
 698    } while(0)
 699
 700 struct nouveau_screen *
 701 nvc0_screen_create(struct nouveau_device *dev)
 702 {
 703    struct nvc0_screen *screen;
 704    struct pipe_screen *pscreen;
 705    struct nouveau_object *chan;
 706    struct nouveau_pushbuf *push;
 707    uint64_t value;
 708    uint32_t obj_class;
 709    uint32_t flags;
 710    int ret;
 711    unsigned i;
 712
 713    switch (dev->chipset & ~0xf) {
 714    case 0xc0:
 715    case 0xd0:
 716    case 0xe0:
 717    case 0xf0:
 718    case 0x100:
 719    case 0x110:
 720    case 0x120:
 721       break;
 722    default:
 723       return NULL;
 724    }
 725
 726    screen = CALLOC_STRUCT(nvc0_screen);
 727    if (!screen)
 728       return NULL;
 729    pscreen = &screen->base.base;
 730    pscreen->destroy = nvc0_screen_destroy;
 731
 732    ret = nouveau_screen_init(&screen->base, dev);
 733    if (ret) {
 734       nvc0_screen_destroy(pscreen);
 735       return NULL;
 736    }
 737    chan = screen->base.channel;
 738    push = screen->base.pushbuf;
 739    push->user_priv = screen;
 740    push->rsvd_kick = 5;
 741
 742    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 743       PIPE_BIND_SHADER_BUFFER |
 744       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 745       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 746    screen->base.sysmem_bindings |=
 747       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 748
 749    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 750       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 751       screen->base.vidmem_bindings = 0;
 752    }
 753
 754    pscreen->context_create = nvc0_create;
 755    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 756    pscreen->get_param = nvc0_screen_get_param;
 757    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 758    pscreen->get_paramf = nvc0_screen_get_paramf;
 759    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 760    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 761
 762    nvc0_screen_init_resource_functions(pscreen);
 763
 764    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 765    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 766
 767    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 768    if (screen->base.drm->version >= 0x01000202)
 769       flags |= NOUVEAU_BO_COHERENT;
 770
 771    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 772    if (ret)
 773       goto fail;
 774    nouveau_bo_map(screen->fence.bo, 0, NULL);
 775    screen->fence.map = screen->fence.bo->map;
 776    screen->base.fence.emit = nvc0_screen_fence_emit;
 777    screen->base.fence.update = nvc0_screen_fence_update;
 778
 779
 780    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 781                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 782    if (ret)
 783       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 784
 785    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 786    PUSH_DATA (push, screen->nvsw->handle);
 787
 788    switch (dev->chipset & ~0xf) {
 789    case 0x120:
 790    case 0x110:
 791    case 0x100:
 792    case 0xf0:
 793       obj_class = NVF0_P2MF_CLASS;
 794       break;
 795    case 0xe0:
 796       obj_class = NVE4_P2MF_CLASS;
 797       break;
 798    default:
 799       obj_class = NVC0_M2MF_CLASS;
 800       break;
 801    }
 802    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 803                             &screen->m2mf);
 804    if (ret)
 805       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 806
 807    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 808    PUSH_DATA (push, screen->m2mf->oclass);
 809    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 810       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 811       PUSH_DATA (push, 0xa0b5);
 812    }
 813
 814    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 815                             &screen->eng2d);
 816    if (ret)
 817       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 818
 819    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 820    PUSH_DATA (push, screen->eng2d->oclass);
 821    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 822    PUSH_DATA (push, 0);
 823    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 824    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 825    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 826    PUSH_DATA (push, 0);
 827    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 828    PUSH_DATA (push, 0);
 829    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 830    PUSH_DATA (push, 0x3f);
 831    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 832    PUSH_DATA (push, 1);
 833    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 834    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 835
 836    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 837    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 838    PUSH_DATA (push, screen->fence.bo->offset + 16);
 839
 840    switch (dev->chipset & ~0xf) {
 841    case 0x120:
 842       obj_class = GM200_3D_CLASS;
 843       break;
 844    case 0x110:
 845       obj_class = GM107_3D_CLASS;
 846       break;
 847    case 0x100:
 848    case 0xf0:
 849       obj_class = NVF0_3D_CLASS;
 850       break;
 851    case 0xe0:
 852       switch (dev->chipset) {
 853       case 0xea:
 854          obj_class = NVEA_3D_CLASS;
 855          break;
 856       default:
 857          obj_class = NVE4_3D_CLASS;
 858          break;
 859       }
 860       break;
 861    case 0xd0:
 862       obj_class = NVC8_3D_CLASS;
 863       break;
 864    case 0xc0:
 865    default:
 866       switch (dev->chipset) {
 867       case 0xc8:
 868          obj_class = NVC8_3D_CLASS;
 869          break;
 870       case 0xc1:
 871          obj_class = NVC1_3D_CLASS;
 872          break;
 873       default:
 874          obj_class = NVC0_3D_CLASS;
 875          break;
 876       }
 877       break;
 878    }
 879    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 880                             &screen->eng3d);
 881    if (ret)
 882       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 883    screen->base.class_3d = obj_class;
 884
 885    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 886    PUSH_DATA (push, screen->eng3d->oclass);
 887
 888    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 889    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 890
 891    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 892       /* kill shaders after about 1 second (at 100 MHz) */
 893       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 894       PUSH_DATA (push, 0x17);
 895    }
 896
 897    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 898                     screen->base.drm->version >= 0x01000101);
 899    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 900    for (i = 0; i < 8; ++i)
 901            PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 902
 903    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 904    PUSH_DATA (push, 1);
 905
 906    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 907    PUSH_DATA (push, 0);
 908    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 909    PUSH_DATA (push, 0);
 910    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 911    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 912    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 913    PUSH_DATA (push, 0);
 914    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 915    PUSH_DATA (push, 1);
 916    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 917    PUSH_DATA (push, 1);
 918    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 919    PUSH_DATA (push, 1);
 920    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 921    PUSH_DATA (push, 0);
 922    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 923    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 924    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 925       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 926    } else {
 927       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 928       PUSH_DATA (push, 15);
 929    }
 930    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 931    PUSH_DATA (push, 8); /* 128 */
 932    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 933    PUSH_DATA (push, 1);
 934    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 935       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 936       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 937    }
 938
 939    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 940
 941    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
 942                         &screen->text);
 943    if (ret)
 944       goto fail;
 945
 946    /* XXX: getting a page fault at the end of the code buffer every few
 947     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 948     */
 949    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 950
 951    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
 952                         &screen->uniform_bo);
 953    if (ret)
 954       goto fail;
 955
 956    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
 957
 958    for (i = 0; i < 5; ++i) {
 959       /* TIC and TSC entries for each unit (nve4+ only) */
 960       /* auxiliary constants (6 user clip planes, base instance id) */
 961       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 962       PUSH_DATA (push, 2048);
 963       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 964       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 965       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 966       PUSH_DATA (push, (15 << 4) | 1);
 967       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 968          unsigned j;
 969          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 970          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
 971          for (j = 0; j < 8; ++j)
 972             PUSH_DATA(push, j);
 973       } else {
 974          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 975          PUSH_DATA (push, 0x54);
 976       }
 977    }
 978    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 979    PUSH_DATA (push, 0);
 980
 981    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 982    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 983    PUSH_DATA (push, 256);
 984    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 985    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 986    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 987    PUSH_DATA (push, 0);
 988    PUSH_DATAf(push, 0.0f);
 989    PUSH_DATAf(push, 0.0f);
 990    PUSH_DATAf(push, 0.0f);
 991    PUSH_DATAf(push, 0.0f);
 992    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 993    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 994    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 995
 996    if (screen->base.drm->version >= 0x01000101) {
 997       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 998       if (ret) {
 999          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
1000          goto fail;
1001       }
1002    } else {
1003       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1004          value = (8 << 8) | 4;
1005       else
1006          value = (16 << 8) | 4;
1007    }
1008    screen->gpc_count = value & 0x000000ff;
1009    screen->mp_count = value >> 8;
1010    screen->mp_count_compute = screen->mp_count;
1011
1012    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1013
1014    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
1015    PUSH_DATAh(push, screen->text->offset);
1016    PUSH_DATA (push, screen->text->offset);
1017    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1018    PUSH_DATAh(push, screen->tls->offset);
1019    PUSH_DATA (push, screen->tls->offset);
1020    PUSH_DATA (push, screen->tls->size >> 32);
1021    PUSH_DATA (push, screen->tls->size);
1022    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1023    PUSH_DATA (push, 0);
1024    /* Reduce likelihood of collision with real buffers by placing the hole at
1025     * the top of the 4G area. This will have to be dealt with for real
1026     * eventually by blocking off that area from the VM.
1027     */
1028    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1029    PUSH_DATA (push, 0xff << 24);
1030
1031    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1032       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1033                            &screen->poly_cache);
1034       if (ret)
1035          goto fail;
1036
1037       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1038       PUSH_DATAh(push, screen->poly_cache->offset);
1039       PUSH_DATA (push, screen->poly_cache->offset);
1040       PUSH_DATA (push, 3);
1041    }
1042
1043    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1044                         &screen->txc);
1045    if (ret)
1046       goto fail;
1047
1048    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1049    PUSH_DATAh(push, screen->txc->offset);
1050    PUSH_DATA (push, screen->txc->offset);
1051    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1052    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1053       screen->tic.maxwell = true;
1054       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1055          screen->tic.maxwell =
1056             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1057          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1058       }
1059    }
1060
1061    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1062    PUSH_DATAh(push, screen->txc->offset + 65536);
1063    PUSH_DATA (push, screen->txc->offset + 65536);
1064    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1065
1066    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1067    PUSH_DATA (push, 0);
1068    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1069    PUSH_DATA (push, 0);
1070    PUSH_DATA (push, 0);
1071    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1072    PUSH_DATA (push, 0x3f);
1073
1074    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1075    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1076    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1077    for (i = 0; i < 8 * 2; ++i)
1078       PUSH_DATA(push, 0);
1079    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1080    PUSH_DATA (push, 0);
1081    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1082    PUSH_DATA (push, 0);
1083
1084    /* neither scissors, viewport nor stencil mask should affect clears */
1085    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1086    PUSH_DATA (push, 0);
1087
1088    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1089    PUSH_DATA (push, 1);
1090    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1091       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1092       PUSH_DATAf(push, 0.0f);
1093       PUSH_DATAf(push, 1.0f);
1094    }
1095    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1096    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1097
1098    /* We use scissors instead of exact view volume clipping,
1099     * so they're always enabled.
1100     */
1101    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1102       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1103       PUSH_DATA (push, 1);
1104       PUSH_DATA (push, 8192 << 16);
1105       PUSH_DATA (push, 8192 << 16);
1106    }
1107
1108 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1109
1110    i = 0;
1111    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1112    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1113    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1114    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1115    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1116    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1117    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1118    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1119    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1120    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1121    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1122    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1123    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1124
1125    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1126    PUSH_DATA (push, 1);
1127    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1128    PUSH_DATA (push, 1);
1129    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1130    PUSH_DATA (push, 0x40);
1131    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1132    PUSH_DATA (push, 0);
1133    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1134    PUSH_DATA (push, 0x30);
1135    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1136    PUSH_DATA (push, 3);
1137    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1138    PUSH_DATA (push, 0x20);
1139    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1140    PUSH_DATA (push, 0x00);
1141    screen->save_state.patch_vertices = 3;
1142
1143    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1144    PUSH_DATA (push, 0);
1145    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1146    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1147
1148    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1149
1150    if (nvc0_screen_init_compute(screen))
1151       goto fail;
1152
1153    PUSH_KICK (push);
1154
1155    screen->tic.entries = CALLOC(4096, sizeof(void *));
1156    screen->tsc.entries = screen->tic.entries + 2048;
1157
1158    if (!nvc0_blitter_create(screen))
1159       goto fail;
1160
1161    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1162
1163    return &screen->base;
1164
1165 fail:
1166    screen->base.base.context_create = NULL;
1167    return &screen->base;
1168 }
1169
1170 int
1171 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1172 {
1173    int i = screen->tic.next;
1174
1175    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1176       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1177
1178    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1179
1180    if (screen->tic.entries[i])
1181       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1182
1183    screen->tic.entries[i] = entry;
1184    return i;
1185 }
1186
1187 int
1188 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1189 {
1190    int i = screen->tsc.next;
1191
1192    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1193       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1194
1195    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1196
1197    if (screen->tsc.entries[i])
1198       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1199
1200    screen->tsc.entries[i] = entry;
1201    return i;
1202 }