src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    const struct util_format_description *desc = util_format_description(format);
  49
  50    if (sample_count > 8)
  51       return false;
  52    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  53       return false;
  54
  55    /* Short-circuit the rest of the logic -- this is used by the state tracker
  56     * to determine valid MS levels in a no-attachments scenario.
  57     */
  58    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  59       return true;
  60
  61    if (!util_format_is_supported(format, bindings))
  62       return false;
  63
  64    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  65       if (util_format_get_blocksizebits(format) == 3 * 32)
  66          return false;
  67
  68    if (bindings & PIPE_BIND_LINEAR)
  69       if (util_format_is_depth_or_stencil(format) ||
  70           (target != PIPE_TEXTURE_1D &&
  71            target != PIPE_TEXTURE_2D &&
  72            target != PIPE_TEXTURE_RECT) ||
  73           sample_count > 1)
  74          return false;
  75
  76    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  77     */
  78    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  79         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  80        /* The claim is that this should work on GM107 but it doesn't. Need to
  81         * test further and figure out if it's a nouveau issue or a HW one.
  82        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  83         */
  84        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  85       return false;
  86
  87    /* transfers & shared are always supported */
  88    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  89                  PIPE_BIND_TRANSFER_WRITE |
  90                  PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    return (( nvc0_format_table[format].usage |
  94             nvc0_vertex_format[format].usage) & bindings) == bindings;
  95 }
  96
  97 static int
  98 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  99 {
 100    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 101    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 102
 103    switch (param) {
 104    /* non-boolean caps */
 105    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 106    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 107       return 15;
 108    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 109       return 12;
 110    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 111       return 2048;
 112    case PIPE_CAP_MIN_TEXEL_OFFSET:
 113       return -8;
 114    case PIPE_CAP_MAX_TEXEL_OFFSET:
 115       return 7;
 116    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 117       return -32;
 118    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 119       return 31;
 120    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 121       return 128 * 1024 * 1024;
 122    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 123       if (class_3d <= NVF0_3D_CLASS)
 124          return 420;
 125       return 410;
 126    case PIPE_CAP_MAX_RENDER_TARGETS:
 127       return 8;
 128    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 129       return 1;
 130    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 131       return 4;
 132    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 133    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 134       return 128;
 135    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 136    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 137       return 1024;
 138    case PIPE_CAP_MAX_VERTEX_STREAMS:
 139       return 4;
 140    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 141       return 2048;
 142    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 143       return 256;
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145       return 16; /* 256 for binding as RT, but that's not possible in GL */
 146    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 147       return 16;
 148    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 149       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 150    case PIPE_CAP_MAX_VIEWPORTS:
 151       return NVC0_MAX_VIEWPORTS;
 152    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 153       return 4;
 154    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 155       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 156    case PIPE_CAP_ENDIANNESS:
 157       return PIPE_ENDIAN_LITTLE;
 158    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 159       return 30;
 160
 161    /* supported caps */
 162    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 163    case PIPE_CAP_TEXTURE_SWIZZLE:
 164    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 165    case PIPE_CAP_NPOT_TEXTURES:
 166    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 167    case PIPE_CAP_ANISOTROPIC_FILTER:
 168    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 169    case PIPE_CAP_CUBE_MAP_ARRAY:
 170    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 171    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 172    case PIPE_CAP_TWO_SIDED_STENCIL:
 173    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 174    case PIPE_CAP_POINT_SPRITE:
 175    case PIPE_CAP_TGSI_TEXCOORD:
 176    case PIPE_CAP_SM3:
 177    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 178    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 179    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 180    case PIPE_CAP_QUERY_TIMESTAMP:
 181    case PIPE_CAP_QUERY_TIME_ELAPSED:
 182    case PIPE_CAP_OCCLUSION_QUERY:
 183    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 184    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 185    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 186    case PIPE_CAP_INDEP_BLEND_ENABLE:
 187    case PIPE_CAP_INDEP_BLEND_FUNC:
 188    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 189    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 190    case PIPE_CAP_PRIMITIVE_RESTART:
 191    case PIPE_CAP_TGSI_INSTANCEID:
 192    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 193    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 194    case PIPE_CAP_CONDITIONAL_RENDER:
 195    case PIPE_CAP_TEXTURE_BARRIER:
 196    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 197    case PIPE_CAP_START_INSTANCE:
 198    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 199    case PIPE_CAP_DRAW_INDIRECT:
 200    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 201    case PIPE_CAP_USER_INDEX_BUFFERS:
 202    case PIPE_CAP_USER_VERTEX_BUFFERS:
 203    case PIPE_CAP_TEXTURE_QUERY_LOD:
 204    case PIPE_CAP_SAMPLE_SHADING:
 205    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 206    case PIPE_CAP_TEXTURE_GATHER_SM5:
 207    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 208    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 209    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 210    case PIPE_CAP_CLIP_HALFZ:
 211    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 212    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 213    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 214    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 215    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 216    case PIPE_CAP_TGSI_TXQS:
 217    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 218    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 219    case PIPE_CAP_SHAREABLE_SHADERS:
 220    case PIPE_CAP_CLEAR_TEXTURE:
 221    case PIPE_CAP_DRAW_PARAMETERS:
 222    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 223    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 224    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 225    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 226    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 227    case PIPE_CAP_INVALIDATE_BUFFER:
 228    case PIPE_CAP_STRING_MARKER:
 229    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 230    case PIPE_CAP_CULL_DISTANCE:
 231    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 232    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 233       return 1;
 234    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 235       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 236    case PIPE_CAP_COMPUTE:
 237       return 1;
 238    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 239       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 240
 241    /* unsupported caps */
 242    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 243    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 244    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 245    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 246    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 247    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 248    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 249    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 250    case PIPE_CAP_FAKE_SW_MSAA:
 251    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 252    case PIPE_CAP_VERTEXID_NOBASE:
 253    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 254    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 255    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 256    case PIPE_CAP_GENERATE_MIPMAP:
 257    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 258    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 259    case PIPE_CAP_QUERY_MEMORY_INFO:
 260    case PIPE_CAP_PCI_GROUP:
 261    case PIPE_CAP_PCI_BUS:
 262    case PIPE_CAP_PCI_DEVICE:
 263    case PIPE_CAP_PCI_FUNCTION:
 264       return 0;
 265
 266    case PIPE_CAP_VENDOR_ID:
 267       return 0x10de;
 268    case PIPE_CAP_DEVICE_ID: {
 269       uint64_t device_id;
 270       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 271          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 272          return -1;
 273       }
 274       return device_id;
 275    }
 276    case PIPE_CAP_ACCELERATED:
 277       return 1;
 278    case PIPE_CAP_VIDEO_MEMORY:
 279       return dev->vram_size >> 20;
 280    case PIPE_CAP_UMA:
 281       return 0;
 282    }
 283
 284    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 285    return 0;
 286 }
 287
 288 static int
 289 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 290                              enum pipe_shader_cap param)
 291 {
 292    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 293
 294    switch (shader) {
 295    case PIPE_SHADER_VERTEX:
 296    case PIPE_SHADER_GEOMETRY:
 297    case PIPE_SHADER_FRAGMENT:
 298    case PIPE_SHADER_COMPUTE:
 299       break;
 300    case PIPE_SHADER_TESS_CTRL:
 301    case PIPE_SHADER_TESS_EVAL:
 302       if (class_3d >= GM107_3D_CLASS)
 303          return 0;
 304       break;
 305    default:
 306       return 0;
 307    }
 308
 309    switch (param) {
 310    case PIPE_SHADER_CAP_PREFERRED_IR:
 311       return PIPE_SHADER_IR_TGSI;
 312    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 313       return 1 << PIPE_SHADER_IR_TGSI;
 314    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 315    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 316    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 317    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 318       return 16384;
 319    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 320       return 16;
 321    case PIPE_SHADER_CAP_MAX_INPUTS:
 322       if (shader == PIPE_SHADER_VERTEX)
 323          return 32;
 324       /* NOTE: These only count our slots for GENERIC varyings.
 325        * The address space may be larger, but the actual hard limit seems to be
 326        * less than what the address space layout permits, so don't add TEXCOORD,
 327        * COLOR, etc. here.
 328        */
 329       if (shader == PIPE_SHADER_FRAGMENT)
 330          return 0x1f0 / 16;
 331       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 332        * and excludes 0x60 per-patch inputs.
 333        */
 334       return 0x200 / 16;
 335    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 336       return 32;
 337    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 338       return 65536;
 339    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 340       return NVC0_MAX_PIPE_CONSTBUFS;
 341    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 342       return shader != PIPE_SHADER_FRAGMENT;
 343    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 344       return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
 345    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 346    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 347       return 1;
 348    case PIPE_SHADER_CAP_MAX_PREDS:
 349       return 0;
 350    case PIPE_SHADER_CAP_MAX_TEMPS:
 351       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 352    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 353       return 1;
 354    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 355       return 1;
 356    case PIPE_SHADER_CAP_SUBROUTINES:
 357       return 1;
 358    case PIPE_SHADER_CAP_INTEGERS:
 359       return 1;
 360    case PIPE_SHADER_CAP_DOUBLES:
 361       return 1;
 362    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 363       return 1;
 364    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 365       return 1;
 366    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 367    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 368       return 0;
 369    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 370       return NVC0_MAX_BUFFERS;
 371    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 372       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 373    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 374       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 375    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 376       return 32;
 377    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 378       if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
 379          return NVC0_MAX_IMAGES;
 380       if (class_3d < NVE4_3D_CLASS)
 381          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 382             return NVC0_MAX_IMAGES;
 383       return 0;
 384    default:
 385       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 386       return 0;
 387    }
 388 }
 389
 390 static float
 391 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 392 {
 393    switch (param) {
 394    case PIPE_CAPF_MAX_LINE_WIDTH:
 395    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 396       return 10.0f;
 397    case PIPE_CAPF_MAX_POINT_WIDTH:
 398       return 63.0f;
 399    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 400       return 63.375f;
 401    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 402       return 16.0f;
 403    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 404       return 15.0f;
 405    case PIPE_CAPF_GUARD_BAND_LEFT:
 406    case PIPE_CAPF_GUARD_BAND_TOP:
 407       return 0.0f;
 408    case PIPE_CAPF_GUARD_BAND_RIGHT:
 409    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 410       return 0.0f; /* that or infinity */
 411    }
 412
 413    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 414    return 0.0f;
 415 }
 416
 417 static int
 418 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 419                               enum pipe_shader_ir ir_type,
 420                               enum pipe_compute_cap param, void *data)
 421 {
 422    struct nvc0_screen *screen = nvc0_screen(pscreen);
 423    const uint16_t obj_class = screen->compute->oclass;
 424
 425 #define RET(x) do {                  \
 426    if (data)                         \
 427       memcpy(data, x, sizeof(x));    \
 428    return sizeof(x);                 \
 429 } while (0)
 430
 431    switch (param) {
 432    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 433       RET((uint64_t []) { 3 });
 434    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 435       if (obj_class >= NVE4_COMPUTE_CLASS) {
 436          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 437       } else {
 438          RET(((uint64_t []) { 65535, 65535, 65535 }));
 439       }
 440    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 441       RET(((uint64_t []) { 1024, 1024, 64 }));
 442    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 443       RET((uint64_t []) { 1024 });
 444    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 445       RET((uint64_t []) { 1ULL << 40 });
 446    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 447       switch (obj_class) {
 448       case GM200_COMPUTE_CLASS:
 449          RET((uint64_t []) { 96 << 10 });
 450          break;
 451       case GM107_COMPUTE_CLASS:
 452          RET((uint64_t []) { 64 << 10 });
 453          break;
 454       default:
 455          RET((uint64_t []) { 48 << 10 });
 456          break;
 457       }
 458    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 459       RET((uint64_t []) { 512 << 10 });
 460    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 461       RET((uint64_t []) { 4096 });
 462    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 463       RET((uint32_t []) { 32 });
 464    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 465       RET((uint64_t []) { 1ULL << 40 });
 466    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 467       RET((uint32_t []) { 0 });
 468    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 469       RET((uint32_t []) { screen->mp_count_compute });
 470    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 471       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 472    default:
 473       return 0;
 474    }
 475
 476 #undef RET
 477 }
 478
 479 static void
 480 nvc0_screen_destroy(struct pipe_screen *pscreen)
 481 {
 482    struct nvc0_screen *screen = nvc0_screen(pscreen);
 483
 484    if (!nouveau_drm_screen_unref(&screen->base))
 485       return;
 486
 487    if (screen->base.fence.current) {
 488       struct nouveau_fence *current = NULL;
 489
 490       /* nouveau_fence_wait will create a new current fence, so wait on the
 491        * _current_ one, and remove both.
 492        */
 493       nouveau_fence_ref(screen->base.fence.current, &current);
 494       nouveau_fence_wait(current, NULL);
 495       nouveau_fence_ref(NULL, &current);
 496       nouveau_fence_ref(NULL, &screen->base.fence.current);
 497    }
 498    if (screen->base.pushbuf)
 499       screen->base.pushbuf->user_priv = NULL;
 500
 501    if (screen->blitter)
 502       nvc0_blitter_destroy(screen);
 503    if (screen->pm.prog) {
 504       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 505       nvc0_program_destroy(NULL, screen->pm.prog);
 506       FREE(screen->pm.prog);
 507    }
 508
 509    nouveau_bo_ref(NULL, &screen->text);
 510    nouveau_bo_ref(NULL, &screen->uniform_bo);
 511    nouveau_bo_ref(NULL, &screen->tls);
 512    nouveau_bo_ref(NULL, &screen->txc);
 513    nouveau_bo_ref(NULL, &screen->fence.bo);
 514    nouveau_bo_ref(NULL, &screen->poly_cache);
 515
 516    nouveau_heap_destroy(&screen->lib_code);
 517    nouveau_heap_destroy(&screen->text_heap);
 518
 519    FREE(screen->tic.entries);
 520
 521    nouveau_object_del(&screen->eng3d);
 522    nouveau_object_del(&screen->eng2d);
 523    nouveau_object_del(&screen->m2mf);
 524    nouveau_object_del(&screen->compute);
 525    nouveau_object_del(&screen->nvsw);
 526
 527    nouveau_screen_fini(&screen->base);
 528
 529    FREE(screen);
 530 }
 531
 532 static int
 533 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 534                      unsigned size, const uint32_t *data)
 535 {
 536    struct nouveau_pushbuf *push = screen->base.pushbuf;
 537
 538    size /= 4;
 539
 540    assert((pos + size) <= 0x800);
 541
 542    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 543    PUSH_DATA (push, (m - 0x3800) / 8);
 544    PUSH_DATA (push, pos);
 545    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 546    PUSH_DATA (push, pos);
 547    PUSH_DATAp(push, data, size);
 548
 549    return pos + size;
 550 }
 551
 552 static void
 553 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 554 {
 555    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 556    PUSH_DATA (push, 0xff);
 557    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 558    PUSH_DATA (push, 0xff);
 559    PUSH_DATA (push, 0xff);
 560    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 561    PUSH_DATA (push, 0xff);
 562    PUSH_DATA (push, 0xff);
 563    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 564    PUSH_DATA (push, 0x3f);
 565
 566    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 567    PUSH_DATA (push, (3 << 16) | 3);
 568    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 569    PUSH_DATA (push, (2 << 16) | 2);
 570
 571    if (obj_class < GM107_3D_CLASS) {
 572       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 573       PUSH_DATA (push, 0);
 574    }
 575    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 576    PUSH_DATA (push, 0x10);
 577    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 578    PUSH_DATA (push, 0x10);
 579    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 580    PUSH_DATA (push, 0x10);
 581    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 582    PUSH_DATA (push, 0x10);
 583    PUSH_DATA (push, 0x10);
 584    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 585    PUSH_DATA (push, 0x10);
 586    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 587    PUSH_DATA (push, 0xe);
 588
 589    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 590    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 591    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 592    PUSH_DATA (push, 0);
 593    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 594    PUSH_DATA (push, 3);
 595
 596    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 597    PUSH_DATA (push, 0x3fffff);
 598    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 599    PUSH_DATA (push, 1);
 600    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 601    PUSH_DATA (push, 1);
 602
 603    if (obj_class < GM107_3D_CLASS) {
 604       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 605       PUSH_DATA (push, 3);
 606
 607       if (obj_class >= NVE4_3D_CLASS) {
 608          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 609          PUSH_DATA (push, 1);
 610       }
 611    }
 612
 613    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 614     * are supposed to do */
 615 }
 616
 617 static void
 618 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 619 {
 620    struct nvc0_screen *screen = nvc0_screen(pscreen);
 621    struct nouveau_pushbuf *push = screen->base.pushbuf;
 622
 623    /* we need to do it after possible flush in MARK_RING */
 624    *sequence = ++screen->base.fence.sequence;
 625
 626    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 627    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 628    PUSH_DATAh(push, screen->fence.bo->offset);
 629    PUSH_DATA (push, screen->fence.bo->offset);
 630    PUSH_DATA (push, *sequence);
 631    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 632               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 633 }
 634
 635 static u32
 636 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 637 {
 638    struct nvc0_screen *screen = nvc0_screen(pscreen);
 639    return screen->fence.map[0];
 640 }
 641
 642 static int
 643 nvc0_screen_init_compute(struct nvc0_screen *screen)
 644 {
 645    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 646
 647    switch (screen->base.device->chipset & ~0xf) {
 648    case 0xc0:
 649    case 0xd0:
 650       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 651    case 0xe0:
 652    case 0xf0:
 653    case 0x100:
 654    case 0x110:
 655    case 0x120:
 656       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 657    default:
 658       return -1;
 659    }
 660 }
 661
 662 bool
 663 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 664                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 665 {
 666    struct nouveau_bo *bo = NULL;
 667    int ret;
 668    uint64_t size = (lpos + lneg) * 32 + cstack;
 669
 670    if (size >= (1 << 20)) {
 671       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 672       return false;
 673    }
 674
 675    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 676    size  = align(size, 0x8000);
 677    size *= screen->mp_count;
 678
 679    size = align(size, 1 << 17);
 680
 681    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 682                         NULL, &bo);
 683    if (ret) {
 684       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 685       return false;
 686    }
 687    nouveau_bo_ref(NULL, &screen->tls);
 688    screen->tls = bo;
 689    return true;
 690 }
 691
 692 #define FAIL_SCREEN_INIT(str, err)                    \
 693    do {                                               \
 694       NOUVEAU_ERR(str, err);                          \
 695       goto fail;                                      \
 696    } while(0)
 697
 698 struct nouveau_screen *
 699 nvc0_screen_create(struct nouveau_device *dev)
 700 {
 701    struct nvc0_screen *screen;
 702    struct pipe_screen *pscreen;
 703    struct nouveau_object *chan;
 704    struct nouveau_pushbuf *push;
 705    uint64_t value;
 706    uint32_t obj_class;
 707    uint32_t flags;
 708    int ret;
 709    unsigned i;
 710
 711    switch (dev->chipset & ~0xf) {
 712    case 0xc0:
 713    case 0xd0:
 714    case 0xe0:
 715    case 0xf0:
 716    case 0x100:
 717    case 0x110:
 718    case 0x120:
 719       break;
 720    default:
 721       return NULL;
 722    }
 723
 724    screen = CALLOC_STRUCT(nvc0_screen);
 725    if (!screen)
 726       return NULL;
 727    pscreen = &screen->base.base;
 728    pscreen->destroy = nvc0_screen_destroy;
 729
 730    ret = nouveau_screen_init(&screen->base, dev);
 731    if (ret) {
 732       nvc0_screen_destroy(pscreen);
 733       return NULL;
 734    }
 735    chan = screen->base.channel;
 736    push = screen->base.pushbuf;
 737    push->user_priv = screen;
 738    push->rsvd_kick = 5;
 739
 740    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 741       PIPE_BIND_SHADER_BUFFER |
 742       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 743       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 744    screen->base.sysmem_bindings |=
 745       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 746
 747    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 748       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 749       screen->base.vidmem_bindings = 0;
 750    }
 751
 752    pscreen->context_create = nvc0_create;
 753    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 754    pscreen->get_param = nvc0_screen_get_param;
 755    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 756    pscreen->get_paramf = nvc0_screen_get_paramf;
 757    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 758    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 759
 760    nvc0_screen_init_resource_functions(pscreen);
 761
 762    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 763    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 764
 765    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 766    if (screen->base.drm->version >= 0x01000202)
 767       flags |= NOUVEAU_BO_COHERENT;
 768
 769    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 770    if (ret)
 771       goto fail;
 772    nouveau_bo_map(screen->fence.bo, 0, NULL);
 773    screen->fence.map = screen->fence.bo->map;
 774    screen->base.fence.emit = nvc0_screen_fence_emit;
 775    screen->base.fence.update = nvc0_screen_fence_update;
 776
 777
 778    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 779                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 780    if (ret)
 781       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 782
 783    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 784    PUSH_DATA (push, screen->nvsw->handle);
 785
 786    switch (dev->chipset & ~0xf) {
 787    case 0x120:
 788    case 0x110:
 789    case 0x100:
 790    case 0xf0:
 791       obj_class = NVF0_P2MF_CLASS;
 792       break;
 793    case 0xe0:
 794       obj_class = NVE4_P2MF_CLASS;
 795       break;
 796    default:
 797       obj_class = NVC0_M2MF_CLASS;
 798       break;
 799    }
 800    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 801                             &screen->m2mf);
 802    if (ret)
 803       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 804
 805    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 806    PUSH_DATA (push, screen->m2mf->oclass);
 807    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 808       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 809       PUSH_DATA (push, 0xa0b5);
 810    }
 811
 812    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 813                             &screen->eng2d);
 814    if (ret)
 815       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 816
 817    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 818    PUSH_DATA (push, screen->eng2d->oclass);
 819    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 820    PUSH_DATA (push, 0);
 821    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 822    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 823    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 824    PUSH_DATA (push, 0);
 825    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 826    PUSH_DATA (push, 0);
 827    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 828    PUSH_DATA (push, 0x3f);
 829    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 830    PUSH_DATA (push, 1);
 831    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 832    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 833
 834    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 835    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 836    PUSH_DATA (push, screen->fence.bo->offset + 16);
 837
 838    switch (dev->chipset & ~0xf) {
 839    case 0x120:
 840       obj_class = GM200_3D_CLASS;
 841       break;
 842    case 0x110:
 843       obj_class = GM107_3D_CLASS;
 844       break;
 845    case 0x100:
 846    case 0xf0:
 847       obj_class = NVF0_3D_CLASS;
 848       break;
 849    case 0xe0:
 850       switch (dev->chipset) {
 851       case 0xea:
 852          obj_class = NVEA_3D_CLASS;
 853          break;
 854       default:
 855          obj_class = NVE4_3D_CLASS;
 856          break;
 857       }
 858       break;
 859    case 0xd0:
 860       obj_class = NVC8_3D_CLASS;
 861       break;
 862    case 0xc0:
 863    default:
 864       switch (dev->chipset) {
 865       case 0xc8:
 866          obj_class = NVC8_3D_CLASS;
 867          break;
 868       case 0xc1:
 869          obj_class = NVC1_3D_CLASS;
 870          break;
 871       default:
 872          obj_class = NVC0_3D_CLASS;
 873          break;
 874       }
 875       break;
 876    }
 877    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 878                             &screen->eng3d);
 879    if (ret)
 880       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 881    screen->base.class_3d = obj_class;
 882
 883    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 884    PUSH_DATA (push, screen->eng3d->oclass);
 885
 886    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 887    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 888
 889    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 890       /* kill shaders after about 1 second (at 100 MHz) */
 891       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 892       PUSH_DATA (push, 0x17);
 893    }
 894
 895    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 896                     screen->base.drm->version >= 0x01000101);
 897    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 898    for (i = 0; i < 8; ++i)
 899            PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 900
 901    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 902    PUSH_DATA (push, 1);
 903
 904    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 905    PUSH_DATA (push, 0);
 906    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 907    PUSH_DATA (push, 0);
 908    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 909    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 910    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 911    PUSH_DATA (push, 0);
 912    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 913    PUSH_DATA (push, 1);
 914    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 915    PUSH_DATA (push, 1);
 916    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 917    PUSH_DATA (push, 1);
 918    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 919    PUSH_DATA (push, 0);
 920    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 921    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 922    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 923       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 924    } else {
 925       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 926       PUSH_DATA (push, 15);
 927    }
 928    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 929    PUSH_DATA (push, 8); /* 128 */
 930    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 931    PUSH_DATA (push, 1);
 932    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 933       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 934       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 935    }
 936
 937    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 938
 939    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
 940                         &screen->text);
 941    if (ret)
 942       goto fail;
 943
 944    /* XXX: getting a page fault at the end of the code buffer every few
 945     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 946     */
 947    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 948
 949    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
 950                         &screen->uniform_bo);
 951    if (ret)
 952       goto fail;
 953
 954    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
 955
 956    for (i = 0; i < 5; ++i) {
 957       /* TIC and TSC entries for each unit (nve4+ only) */
 958       /* auxiliary constants (6 user clip planes, base instance id) */
 959       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 960       PUSH_DATA (push, 2048);
 961       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 962       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 963       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 964       PUSH_DATA (push, (15 << 4) | 1);
 965       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 966          unsigned j;
 967          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 968          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
 969          for (j = 0; j < 8; ++j)
 970             PUSH_DATA(push, j);
 971       } else {
 972          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 973          PUSH_DATA (push, 0x54);
 974       }
 975    }
 976    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 977    PUSH_DATA (push, 0);
 978
 979    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 980    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 981    PUSH_DATA (push, 256);
 982    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 983    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 984    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 985    PUSH_DATA (push, 0);
 986    PUSH_DATAf(push, 0.0f);
 987    PUSH_DATAf(push, 0.0f);
 988    PUSH_DATAf(push, 0.0f);
 989    PUSH_DATAf(push, 0.0f);
 990    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 991    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 992    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 993
 994    if (screen->base.drm->version >= 0x01000101) {
 995       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 996       if (ret) {
 997          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 998          goto fail;
 999       }
1000    } else {
1001       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1002          value = (8 << 8) | 4;
1003       else
1004          value = (16 << 8) | 4;
1005    }
1006    screen->gpc_count = value & 0x000000ff;
1007    screen->mp_count = value >> 8;
1008    screen->mp_count_compute = screen->mp_count;
1009
1010    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1011
1012    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
1013    PUSH_DATAh(push, screen->text->offset);
1014    PUSH_DATA (push, screen->text->offset);
1015    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1016    PUSH_DATAh(push, screen->tls->offset);
1017    PUSH_DATA (push, screen->tls->offset);
1018    PUSH_DATA (push, screen->tls->size >> 32);
1019    PUSH_DATA (push, screen->tls->size);
1020    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1021    PUSH_DATA (push, 0);
1022    /* Reduce likelihood of collision with real buffers by placing the hole at
1023     * the top of the 4G area. This will have to be dealt with for real
1024     * eventually by blocking off that area from the VM.
1025     */
1026    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1027    PUSH_DATA (push, 0xff << 24);
1028
1029    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1030       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1031                            &screen->poly_cache);
1032       if (ret)
1033          goto fail;
1034
1035       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1036       PUSH_DATAh(push, screen->poly_cache->offset);
1037       PUSH_DATA (push, screen->poly_cache->offset);
1038       PUSH_DATA (push, 3);
1039    }
1040
1041    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1042                         &screen->txc);
1043    if (ret)
1044       goto fail;
1045
1046    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1047    PUSH_DATAh(push, screen->txc->offset);
1048    PUSH_DATA (push, screen->txc->offset);
1049    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1050    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1051       screen->tic.maxwell = true;
1052       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1053          screen->tic.maxwell =
1054             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1055          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1056       }
1057    }
1058
1059    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1060    PUSH_DATAh(push, screen->txc->offset + 65536);
1061    PUSH_DATA (push, screen->txc->offset + 65536);
1062    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1063
1064    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1065    PUSH_DATA (push, 0);
1066    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1067    PUSH_DATA (push, 0);
1068    PUSH_DATA (push, 0);
1069    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1070    PUSH_DATA (push, 0x3f);
1071
1072    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1073    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1074    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1075    for (i = 0; i < 8 * 2; ++i)
1076       PUSH_DATA(push, 0);
1077    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1078    PUSH_DATA (push, 0);
1079    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1080    PUSH_DATA (push, 0);
1081
1082    /* neither scissors, viewport nor stencil mask should affect clears */
1083    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1084    PUSH_DATA (push, 0);
1085
1086    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1087    PUSH_DATA (push, 1);
1088    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1089       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1090       PUSH_DATAf(push, 0.0f);
1091       PUSH_DATAf(push, 1.0f);
1092    }
1093    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1094    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1095
1096    /* We use scissors instead of exact view volume clipping,
1097     * so they're always enabled.
1098     */
1099    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1100       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1101       PUSH_DATA (push, 1);
1102       PUSH_DATA (push, 8192 << 16);
1103       PUSH_DATA (push, 8192 << 16);
1104    }
1105
1106 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1107
1108    i = 0;
1109    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1110    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1111    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1112    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1113    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1114    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1115    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1116    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1117    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1118    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1119    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1120    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1121    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1122
1123    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1124    PUSH_DATA (push, 1);
1125    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1126    PUSH_DATA (push, 1);
1127    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1128    PUSH_DATA (push, 0x40);
1129    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1130    PUSH_DATA (push, 0);
1131    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1132    PUSH_DATA (push, 0x30);
1133    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1134    PUSH_DATA (push, 3);
1135    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1136    PUSH_DATA (push, 0x20);
1137    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1138    PUSH_DATA (push, 0x00);
1139    screen->save_state.patch_vertices = 3;
1140
1141    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1142    PUSH_DATA (push, 0);
1143    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1144    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1145
1146    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1147
1148    if (nvc0_screen_init_compute(screen))
1149       goto fail;
1150
1151    PUSH_KICK (push);
1152
1153    screen->tic.entries = CALLOC(4096, sizeof(void *));
1154    screen->tsc.entries = screen->tic.entries + 2048;
1155
1156    if (!nvc0_blitter_create(screen))
1157       goto fail;
1158
1159    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1160
1161    return &screen->base;
1162
1163 fail:
1164    screen->base.base.context_create = NULL;
1165    return &screen->base;
1166 }
1167
1168 int
1169 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1170 {
1171    int i = screen->tic.next;
1172
1173    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1174       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1175
1176    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1177
1178    if (screen->tic.entries[i])
1179       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1180
1181    screen->tic.entries[i] = entry;
1182    return i;
1183 }
1184
1185 int
1186 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1187 {
1188    int i = screen->tsc.next;
1189
1190    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1191       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1192
1193    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1194
1195    if (screen->tsc.entries[i])
1196       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1197
1198    screen->tsc.entries[i] = entry;
1199    return i;
1200 }