src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include "util/u_format.h"
  26 #include "util/u_format_s3tc.h"
  27 #include "pipe/p_screen.h"
  28
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31
  32 #include "nouveau_vp3_video.h"
  33
  34 #include "nvc0/nvc0_context.h"
  35 #include "nvc0/nvc0_screen.h"
  36
  37 #include "nvc0/mme/com9097.mme.h"
  38
  39 static boolean
  40 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  41                                 enum pipe_format format,
  42                                 enum pipe_texture_target target,
  43                                 unsigned sample_count,
  44                                 unsigned bindings)
  45 {
  46    if (sample_count > 8)
  47       return FALSE;
  48    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  49       return FALSE;
  50
  51    if (!util_format_is_supported(format, bindings))
  52       return FALSE;
  53
  54    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  55       if (util_format_get_blocksizebits(format) == 3 * 32)
  56          return FALSE;
  57
  58    /* transfers & shared are always supported */
  59    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  60                  PIPE_BIND_TRANSFER_WRITE |
  61                  PIPE_BIND_SHARED);
  62
  63    return (nvc0_format_table[format].usage & bindings) == bindings;
  64 }
  65
  66 static int
  67 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  68 {
  69    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  70    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  71
  72    switch (param) {
  73    /* non-boolean caps */
  74    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  75    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  76       return 15;
  77    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  78       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  79    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  80       return 2048;
  81    case PIPE_CAP_MIN_TEXEL_OFFSET:
  82       return -8;
  83    case PIPE_CAP_MAX_TEXEL_OFFSET:
  84       return 7;
  85    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  86       return -32;
  87    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
  88       return 31;
  89    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  90       return 65536;
  91    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  92       return 410;
  93    case PIPE_CAP_MAX_RENDER_TARGETS:
  94       return 8;
  95    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  96       return 1;
  97    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
  98       return 4;
  99    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 100    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 101       return 128;
 102    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 103    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 104       return 1024;
 105    case PIPE_CAP_MAX_VERTEX_STREAMS:
 106       return 4;
 107    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 108       return 2048;
 109    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 110       return 256;
 111    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 112       return 1; /* 256 for binding as RT, but that's not possible in GL */
 113    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 114       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 115    case PIPE_CAP_MAX_VIEWPORTS:
 116       return NVC0_MAX_VIEWPORTS;
 117    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 118       return 4;
 119    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 120       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 121    case PIPE_CAP_ENDIANNESS:
 122       return PIPE_ENDIAN_LITTLE;
 123
 124    /* supported caps */
 125    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 126    case PIPE_CAP_TEXTURE_SWIZZLE:
 127    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 128    case PIPE_CAP_NPOT_TEXTURES:
 129    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 130    case PIPE_CAP_ANISOTROPIC_FILTER:
 131    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 132    case PIPE_CAP_CUBE_MAP_ARRAY:
 133    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 134    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 135    case PIPE_CAP_TWO_SIDED_STENCIL:
 136    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 137    case PIPE_CAP_POINT_SPRITE:
 138    case PIPE_CAP_TGSI_TEXCOORD:
 139    case PIPE_CAP_SM3:
 140    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 141    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 142    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 143    case PIPE_CAP_QUERY_TIMESTAMP:
 144    case PIPE_CAP_QUERY_TIME_ELAPSED:
 145    case PIPE_CAP_OCCLUSION_QUERY:
 146    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 147    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 148    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 149    case PIPE_CAP_INDEP_BLEND_ENABLE:
 150    case PIPE_CAP_INDEP_BLEND_FUNC:
 151    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 152    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 153    case PIPE_CAP_PRIMITIVE_RESTART:
 154    case PIPE_CAP_TGSI_INSTANCEID:
 155    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 156    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 157    case PIPE_CAP_CONDITIONAL_RENDER:
 158    case PIPE_CAP_TEXTURE_BARRIER:
 159    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 160    case PIPE_CAP_START_INSTANCE:
 161    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 162    case PIPE_CAP_DRAW_INDIRECT:
 163    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 164    case PIPE_CAP_USER_INDEX_BUFFERS:
 165    case PIPE_CAP_USER_VERTEX_BUFFERS:
 166    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 167    case PIPE_CAP_TEXTURE_QUERY_LOD:
 168    case PIPE_CAP_SAMPLE_SHADING:
 169    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 170    case PIPE_CAP_TEXTURE_GATHER_SM5:
 171    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 172    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 173    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 174    case PIPE_CAP_CLIP_HALFZ:
 175    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 176    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 177       return 1;
 178    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 179       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 180    case PIPE_CAP_COMPUTE:
 181       return (class_3d == NVE4_3D_CLASS) ? 1 : 0;
 182
 183    /* unsupported caps */
 184    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 185    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 186    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 187    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 188    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 189    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 190    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 191    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 192    case PIPE_CAP_FAKE_SW_MSAA:
 193    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 194    case PIPE_CAP_VERTEXID_NOBASE:
 195    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 196    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 197       return 0;
 198
 199    case PIPE_CAP_VENDOR_ID:
 200       return 0x10de;
 201    case PIPE_CAP_DEVICE_ID: {
 202       uint64_t device_id;
 203       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 204          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 205          return -1;
 206       }
 207       return device_id;
 208    }
 209    case PIPE_CAP_ACCELERATED:
 210       return 1;
 211    case PIPE_CAP_VIDEO_MEMORY:
 212       return dev->vram_size >> 20;
 213    case PIPE_CAP_UMA:
 214       return 0;
 215    }
 216
 217    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 218    return 0;
 219 }
 220
 221 static int
 222 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 223                              enum pipe_shader_cap param)
 224 {
 225    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 226
 227    switch (shader) {
 228    case PIPE_SHADER_VERTEX:
 229       /*
 230    case PIPE_SHADER_TESSELLATION_CONTROL:
 231    case PIPE_SHADER_TESSELLATION_EVALUATION:
 232       */
 233    case PIPE_SHADER_GEOMETRY:
 234    case PIPE_SHADER_FRAGMENT:
 235       break;
 236    case PIPE_SHADER_COMPUTE:
 237       if (class_3d != NVE4_3D_CLASS)
 238          return 0;
 239       break;
 240    default:
 241       return 0;
 242    }
 243
 244    switch (param) {
 245    case PIPE_SHADER_CAP_PREFERRED_IR:
 246       return PIPE_SHADER_IR_TGSI;
 247    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 248    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 249    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 250    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 251       return 16384;
 252    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 253       return 16;
 254    case PIPE_SHADER_CAP_MAX_INPUTS:
 255       if (shader == PIPE_SHADER_VERTEX)
 256          return 32;
 257       /* NOTE: These only count our slots for GENERIC varyings.
 258        * The address space may be larger, but the actual hard limit seems to be
 259        * less than what the address space layout permits, so don't add TEXCOORD,
 260        * COLOR, etc. here.
 261        */
 262       if (shader == PIPE_SHADER_FRAGMENT)
 263          return 0x1f0 / 16;
 264       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 265        * and excludes 0x60 per-patch inputs.
 266        */
 267       return 0x200 / 16;
 268    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 269       return 32;
 270    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 271       return 65536;
 272    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 273       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 274          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 275       return NVC0_MAX_PIPE_CONSTBUFS;
 276    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 277    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 278       return shader != PIPE_SHADER_FRAGMENT;
 279    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 280    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 281       return 1;
 282    case PIPE_SHADER_CAP_MAX_PREDS:
 283       return 0;
 284    case PIPE_SHADER_CAP_MAX_TEMPS:
 285       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 286    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 287       return 1;
 288    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 289       return 0;
 290    case PIPE_SHADER_CAP_SUBROUTINES:
 291       return 1;
 292    case PIPE_SHADER_CAP_INTEGERS:
 293       return 1;
 294    case PIPE_SHADER_CAP_DOUBLES:
 295       return 1;
 296    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 297       return 1;
 298    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 299    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 300    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 301       return 0;
 302    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 303       return 16; /* would be 32 in linked (OpenGL-style) mode */
 304    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 305       return 16; /* XXX not sure if more are really safe */
 306    default:
 307       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 308       return 0;
 309    }
 310 }
 311
 312 static float
 313 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 314 {
 315    switch (param) {
 316    case PIPE_CAPF_MAX_LINE_WIDTH:
 317    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 318       return 10.0f;
 319    case PIPE_CAPF_MAX_POINT_WIDTH:
 320       return 63.0f;
 321    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 322       return 63.375f;
 323    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 324       return 16.0f;
 325    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 326       return 15.0f;
 327    case PIPE_CAPF_GUARD_BAND_LEFT:
 328    case PIPE_CAPF_GUARD_BAND_TOP:
 329       return 0.0f;
 330    case PIPE_CAPF_GUARD_BAND_RIGHT:
 331    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 332       return 0.0f; /* that or infinity */
 333    }
 334
 335    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 336    return 0.0f;
 337 }
 338
 339 static int
 340 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 341                               enum pipe_compute_cap param, void *data)
 342 {
 343    uint64_t *data64 = (uint64_t *)data;
 344    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
 345
 346    switch (param) {
 347    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 348       data64[0] = 3;
 349       return 8;
 350    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 351       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
 352       data64[1] = 65535;
 353       data64[2] = 65535;
 354       return 24;
 355    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 356       data64[0] = 1024;
 357       data64[1] = 1024;
 358       data64[2] = 64;
 359       return 24;
 360    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 361       data64[0] = 1024;
 362       return 8;
 363    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 364       data64[0] = (uint64_t)1 << 40;
 365       return 8;
 366    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 367       data64[0] = 48 << 10;
 368       return 8;
 369    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 370       data64[0] = 512 << 10;
 371       return 8;
 372    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 373       data64[0] = 4096;
 374       return 8;
 375    default:
 376       return 0;
 377    }
 378 }
 379
 380 static void
 381 nvc0_screen_destroy(struct pipe_screen *pscreen)
 382 {
 383    struct nvc0_screen *screen = nvc0_screen(pscreen);
 384
 385    if (!nouveau_drm_screen_unref(&screen->base))
 386       return;
 387
 388    if (screen->base.fence.current) {
 389       struct nouveau_fence *current = NULL;
 390
 391       /* nouveau_fence_wait will create a new current fence, so wait on the
 392        * _current_ one, and remove both.
 393        */
 394       nouveau_fence_ref(screen->base.fence.current, &current);
 395       nouveau_fence_wait(current);
 396       nouveau_fence_ref(NULL, &current);
 397       nouveau_fence_ref(NULL, &screen->base.fence.current);
 398    }
 399    if (screen->base.pushbuf)
 400       screen->base.pushbuf->user_priv = NULL;
 401
 402    if (screen->blitter)
 403       nvc0_blitter_destroy(screen);
 404    if (screen->pm.prog) {
 405       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 406       nvc0_program_destroy(NULL, screen->pm.prog);
 407    }
 408
 409    nouveau_bo_ref(NULL, &screen->text);
 410    nouveau_bo_ref(NULL, &screen->uniform_bo);
 411    nouveau_bo_ref(NULL, &screen->tls);
 412    nouveau_bo_ref(NULL, &screen->txc);
 413    nouveau_bo_ref(NULL, &screen->fence.bo);
 414    nouveau_bo_ref(NULL, &screen->poly_cache);
 415    nouveau_bo_ref(NULL, &screen->parm);
 416
 417    nouveau_heap_destroy(&screen->lib_code);
 418    nouveau_heap_destroy(&screen->text_heap);
 419
 420    FREE(screen->tic.entries);
 421
 422    nouveau_object_del(&screen->eng3d);
 423    nouveau_object_del(&screen->eng2d);
 424    nouveau_object_del(&screen->m2mf);
 425    nouveau_object_del(&screen->compute);
 426    nouveau_object_del(&screen->nvsw);
 427
 428    nouveau_screen_fini(&screen->base);
 429
 430    FREE(screen);
 431 }
 432
 433 static int
 434 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 435                      unsigned size, const uint32_t *data)
 436 {
 437    struct nouveau_pushbuf *push = screen->base.pushbuf;
 438
 439    size /= 4;
 440
 441    assert((pos + size) <= 0x800);
 442
 443    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 444    PUSH_DATA (push, (m - 0x3800) / 8);
 445    PUSH_DATA (push, pos);
 446    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 447    PUSH_DATA (push, pos);
 448    PUSH_DATAp(push, data, size);
 449
 450    return pos + size;
 451 }
 452
 453 static void
 454 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 455 {
 456    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 457    PUSH_DATA (push, 0xff);
 458    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 459    PUSH_DATA (push, 0xff);
 460    PUSH_DATA (push, 0xff);
 461    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 462    PUSH_DATA (push, 0xff);
 463    PUSH_DATA (push, 0xff);
 464    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 465    PUSH_DATA (push, 0x3f);
 466
 467    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 468    PUSH_DATA (push, (3 << 16) | 3);
 469    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 470    PUSH_DATA (push, (2 << 16) | 2);
 471
 472    if (obj_class < GM107_3D_CLASS) {
 473       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 474       PUSH_DATA (push, 0);
 475    }
 476    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 477    PUSH_DATA (push, 0x10);
 478    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 479    PUSH_DATA (push, 0x10);
 480    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 481    PUSH_DATA (push, 0x10);
 482    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 483    PUSH_DATA (push, 0x10);
 484    PUSH_DATA (push, 0x10);
 485    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 486    PUSH_DATA (push, 0x10);
 487    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 488    PUSH_DATA (push, 0xe);
 489
 490    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 491    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 492    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 493    PUSH_DATA (push, 0);
 494    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 495    PUSH_DATA (push, 3);
 496
 497    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 498    PUSH_DATA (push, 0x3fffff);
 499    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 500    PUSH_DATA (push, 1);
 501    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 502    PUSH_DATA (push, 1);
 503
 504    if (obj_class < GM107_3D_CLASS) {
 505       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 506       PUSH_DATA (push, 3);
 507
 508       if (obj_class >= NVE4_3D_CLASS) {
 509          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 510          PUSH_DATA (push, 1);
 511       }
 512    }
 513
 514    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 515     * are supposed to do */
 516 }
 517
 518 static void
 519 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 520 {
 521    struct nvc0_screen *screen = nvc0_screen(pscreen);
 522    struct nouveau_pushbuf *push = screen->base.pushbuf;
 523
 524    /* we need to do it after possible flush in MARK_RING */
 525    *sequence = ++screen->base.fence.sequence;
 526
 527    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
 528    PUSH_DATAh(push, screen->fence.bo->offset);
 529    PUSH_DATA (push, screen->fence.bo->offset);
 530    PUSH_DATA (push, *sequence);
 531    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 532               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 533 }
 534
 535 static u32
 536 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 537 {
 538    struct nvc0_screen *screen = nvc0_screen(pscreen);
 539    return screen->fence.map[0];
 540 }
 541
 542 static int
 543 nvc0_screen_init_compute(struct nvc0_screen *screen)
 544 {
 545    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 546
 547    switch (screen->base.device->chipset & ~0xf) {
 548    case 0xc0:
 549    case 0xd0:
 550       /* Using COMPUTE has weird effects on 3D state, we need to
 551        * investigate this further before enabling it by default.
 552        */
 553       if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
 554          return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 555       return 0;
 556    case 0xe0:
 557       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 558    case 0xf0:
 559    case 0x100:
 560    case 0x110:
 561       return 0;
 562    default:
 563       return -1;
 564    }
 565 }
 566
 567 boolean
 568 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 569                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 570 {
 571    struct nouveau_bo *bo = NULL;
 572    int ret;
 573    uint64_t size = (lpos + lneg) * 32 + cstack;
 574
 575    if (size >= (1 << 20)) {
 576       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 577       return FALSE;
 578    }
 579
 580    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 581    size  = align(size, 0x8000);
 582    size *= screen->mp_count;
 583
 584    size = align(size, 1 << 17);
 585
 586    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
 587                         NULL, &bo);
 588    if (ret) {
 589       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 590       return FALSE;
 591    }
 592    nouveau_bo_ref(NULL, &screen->tls);
 593    screen->tls = bo;
 594    return TRUE;
 595 }
 596
 597 #define FAIL_SCREEN_INIT(str, err)                    \
 598    do {                                               \
 599       NOUVEAU_ERR(str, err);                          \
 600       nvc0_screen_destroy(pscreen);                   \
 601       return NULL;                                    \
 602    } while(0)
 603
 604 struct pipe_screen *
 605 nvc0_screen_create(struct nouveau_device *dev)
 606 {
 607    struct nvc0_screen *screen;
 608    struct pipe_screen *pscreen;
 609    struct nouveau_object *chan;
 610    struct nouveau_pushbuf *push;
 611    uint64_t value;
 612    uint32_t obj_class;
 613    int ret;
 614    unsigned i;
 615
 616    switch (dev->chipset & ~0xf) {
 617    case 0xc0:
 618    case 0xd0:
 619    case 0xe0:
 620    case 0xf0:
 621    case 0x100:
 622    case 0x110:
 623       break;
 624    default:
 625       return NULL;
 626    }
 627
 628    screen = CALLOC_STRUCT(nvc0_screen);
 629    if (!screen)
 630       return NULL;
 631    pscreen = &screen->base.base;
 632
 633    ret = nouveau_screen_init(&screen->base, dev);
 634    if (ret) {
 635       nvc0_screen_destroy(pscreen);
 636       return NULL;
 637    }
 638    chan = screen->base.channel;
 639    push = screen->base.pushbuf;
 640    push->user_priv = screen;
 641    push->rsvd_kick = 5;
 642
 643    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 644       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 645       PIPE_BIND_COMMAND_ARGS_BUFFER;
 646    screen->base.sysmem_bindings |=
 647       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 648
 649    pscreen->destroy = nvc0_screen_destroy;
 650    pscreen->context_create = nvc0_create;
 651    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 652    pscreen->get_param = nvc0_screen_get_param;
 653    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 654    pscreen->get_paramf = nvc0_screen_get_paramf;
 655    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 656    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 657
 658    nvc0_screen_init_resource_functions(pscreen);
 659
 660    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 661    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 662
 663    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
 664                         &screen->fence.bo);
 665    if (ret)
 666       goto fail;
 667    nouveau_bo_map(screen->fence.bo, 0, NULL);
 668    screen->fence.map = screen->fence.bo->map;
 669    screen->base.fence.emit = nvc0_screen_fence_emit;
 670    screen->base.fence.update = nvc0_screen_fence_update;
 671
 672
 673    ret = nouveau_object_new(chan,
 674                             (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
 675                             NULL, 0, &screen->nvsw);
 676    if (ret)
 677       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 678
 679
 680    switch (dev->chipset & ~0xf) {
 681    case 0x110:
 682    case 0x100:
 683    case 0xf0:
 684       obj_class = NVF0_P2MF_CLASS;
 685       break;
 686    case 0xe0:
 687       obj_class = NVE4_P2MF_CLASS;
 688       break;
 689    default:
 690       obj_class = NVC0_M2MF_CLASS;
 691       break;
 692    }
 693    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 694                             &screen->m2mf);
 695    if (ret)
 696       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 697
 698    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 699    PUSH_DATA (push, screen->m2mf->oclass);
 700    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 701       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 702       PUSH_DATA (push, 0xa0b5);
 703    }
 704
 705    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 706                             &screen->eng2d);
 707    if (ret)
 708       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 709
 710    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 711    PUSH_DATA (push, screen->eng2d->oclass);
 712    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 713    PUSH_DATA (push, 0);
 714    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 715    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 716    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 717    PUSH_DATA (push, 0);
 718    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 719    PUSH_DATA (push, 0);
 720    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 721    PUSH_DATA (push, 0x3f);
 722    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 723    PUSH_DATA (push, 1);
 724    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 725    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 726
 727    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 728    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 729    PUSH_DATA (push, screen->fence.bo->offset + 16);
 730
 731    switch (dev->chipset & ~0xf) {
 732    case 0x110:
 733       obj_class = GM107_3D_CLASS;
 734       break;
 735    case 0x100:
 736    case 0xf0:
 737       obj_class = NVF0_3D_CLASS;
 738       break;
 739    case 0xe0:
 740       switch (dev->chipset) {
 741       case 0xea:
 742          obj_class = NVEA_3D_CLASS;
 743          break;
 744       default:
 745          obj_class = NVE4_3D_CLASS;
 746          break;
 747       }
 748       break;
 749    case 0xd0:
 750       obj_class = NVC8_3D_CLASS;
 751       break;
 752    case 0xc0:
 753    default:
 754       switch (dev->chipset) {
 755       case 0xc8:
 756          obj_class = NVC8_3D_CLASS;
 757          break;
 758       case 0xc1:
 759          obj_class = NVC1_3D_CLASS;
 760          break;
 761       default:
 762          obj_class = NVC0_3D_CLASS;
 763          break;
 764       }
 765       break;
 766    }
 767    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 768                             &screen->eng3d);
 769    if (ret)
 770       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 771    screen->base.class_3d = obj_class;
 772
 773    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 774    PUSH_DATA (push, screen->eng3d->oclass);
 775
 776    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 777    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 778
 779    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 780       /* kill shaders after about 1 second (at 100 MHz) */
 781       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 782       PUSH_DATA (push, 0x17);
 783    }
 784
 785    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
 786    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 787    for (i = 0; i < 8; ++i)
 788            PUSH_DATA(push, dev->drm_version >= 0x01000101);
 789
 790    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 791    PUSH_DATA (push, 1);
 792
 793    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 794    PUSH_DATA (push, 0);
 795    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 796    PUSH_DATA (push, 0);
 797    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 798    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 799    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 800    PUSH_DATA (push, 0);
 801    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 802    PUSH_DATA (push, 1);
 803    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 804    PUSH_DATA (push, 1);
 805    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 806    PUSH_DATA (push, 1);
 807    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 808    PUSH_DATA (push, 0);
 809    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 810       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 811       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 812    } else {
 813       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 814       PUSH_DATA (push, 15);
 815    }
 816    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 817    PUSH_DATA (push, 8); /* 128 */
 818    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 819    PUSH_DATA (push, 1);
 820    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 821       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 822       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 823    }
 824
 825    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 826
 827    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 828                         &screen->text);
 829    if (ret)
 830       goto fail;
 831
 832    /* XXX: getting a page fault at the end of the code buffer every few
 833     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 834     */
 835    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 836
 837    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
 838                         &screen->uniform_bo);
 839    if (ret)
 840       goto fail;
 841
 842    PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 843
 844    for (i = 0; i < 5; ++i) {
 845       /* TIC and TSC entries for each unit (nve4+ only) */
 846       /* auxiliary constants (6 user clip planes, base instance id) */
 847       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 848       PUSH_DATA (push, 512);
 849       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 850       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 851       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 852       PUSH_DATA (push, (15 << 4) | 1);
 853       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 854          unsigned j;
 855          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 856          PUSH_DATA (push, 0);
 857          for (j = 0; j < 8; ++j)
 858             PUSH_DATA(push, j);
 859       } else {
 860          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 861          PUSH_DATA (push, 0x54);
 862       }
 863    }
 864    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 865    PUSH_DATA (push, 0);
 866
 867    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 868    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 869    PUSH_DATA (push, 256);
 870    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 871    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 872    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 873    PUSH_DATA (push, 0);
 874    PUSH_DATAf(push, 0.0f);
 875    PUSH_DATAf(push, 0.0f);
 876    PUSH_DATAf(push, 0.0f);
 877    PUSH_DATAf(push, 0.0f);
 878    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 879    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 880    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 881
 882    if (dev->drm_version >= 0x01000101) {
 883       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 884       if (ret) {
 885          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 886          goto fail;
 887       }
 888    } else {
 889       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 890          value = (8 << 8) | 4;
 891       else
 892          value = (16 << 8) | 4;
 893    }
 894    screen->mp_count = value >> 8;
 895    screen->mp_count_compute = screen->mp_count;
 896
 897    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 898
 899    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 900    PUSH_DATAh(push, screen->text->offset);
 901    PUSH_DATA (push, screen->text->offset);
 902    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 903    PUSH_DATAh(push, screen->tls->offset);
 904    PUSH_DATA (push, screen->tls->offset);
 905    PUSH_DATA (push, screen->tls->size >> 32);
 906    PUSH_DATA (push, screen->tls->size);
 907    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 908    PUSH_DATA (push, 0);
 909    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 910    PUSH_DATA (push, 0);
 911
 912    if (screen->eng3d->oclass < GM107_3D_CLASS) {
 913       ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 914                            &screen->poly_cache);
 915       if (ret)
 916          goto fail;
 917
 918       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 919       PUSH_DATAh(push, screen->poly_cache->offset);
 920       PUSH_DATA (push, screen->poly_cache->offset);
 921       PUSH_DATA (push, 3);
 922    }
 923
 924    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
 925                         &screen->txc);
 926    if (ret)
 927       goto fail;
 928
 929    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 930    PUSH_DATAh(push, screen->txc->offset);
 931    PUSH_DATA (push, screen->txc->offset);
 932    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 933
 934    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 935    PUSH_DATAh(push, screen->txc->offset + 65536);
 936    PUSH_DATA (push, screen->txc->offset + 65536);
 937    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 938
 939    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 940    PUSH_DATA (push, 0);
 941    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 942    PUSH_DATA (push, 0);
 943    PUSH_DATA (push, 0);
 944    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 945    PUSH_DATA (push, 0x3f);
 946
 947    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 948    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 949    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 950    for (i = 0; i < 8 * 2; ++i)
 951       PUSH_DATA(push, 0);
 952    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 953    PUSH_DATA (push, 0);
 954    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 955    PUSH_DATA (push, 0);
 956
 957    /* neither scissors, viewport nor stencil mask should affect clears */
 958    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 959    PUSH_DATA (push, 0);
 960
 961    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 962    PUSH_DATA (push, 1);
 963    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
 964       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
 965       PUSH_DATAf(push, 0.0f);
 966       PUSH_DATAf(push, 1.0f);
 967    }
 968    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 969    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 970
 971    /* We use scissors instead of exact view volume clipping,
 972     * so they're always enabled.
 973     */
 974    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
 975       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
 976       PUSH_DATA (push, 1);
 977       PUSH_DATA (push, 8192 << 16);
 978       PUSH_DATA (push, 8192 << 16);
 979    }
 980
 981 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 982
 983    i = 0;
 984    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
 985    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
 986    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
 987    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
 988    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
 989    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
 990    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
 991    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
 992    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
 993
 994    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
 995    PUSH_DATA (push, 1);
 996    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
 997    PUSH_DATA (push, 1);
 998    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 999    PUSH_DATA (push, 0x40);
1000    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1001    PUSH_DATA (push, 0);
1002    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1003    PUSH_DATA (push, 0x30);
1004    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1005    PUSH_DATA (push, 3);
1006    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1007    PUSH_DATA (push, 0x20);
1008    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1009    PUSH_DATA (push, 0x00);
1010
1011    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1012    PUSH_DATA (push, 0);
1013    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1014    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1015
1016    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1017
1018    if (nvc0_screen_init_compute(screen))
1019       goto fail;
1020
1021    PUSH_KICK (push);
1022
1023    screen->tic.entries = CALLOC(4096, sizeof(void *));
1024    screen->tsc.entries = screen->tic.entries + 2048;
1025
1026    if (!nvc0_blitter_create(screen))
1027       goto fail;
1028
1029    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
1030
1031    return pscreen;
1032
1033 fail:
1034    nvc0_screen_destroy(pscreen);
1035    return NULL;
1036 }
1037
1038 int
1039 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1040 {
1041    int i = screen->tic.next;
1042
1043    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1044       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1045
1046    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1047
1048    if (screen->tic.entries[i])
1049       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1050
1051    screen->tic.entries[i] = entry;
1052    return i;
1053 }
1054
1055 int
1056 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1057 {
1058    int i = screen->tsc.next;
1059
1060    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1061       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1062
1063    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1064
1065    if (screen->tsc.entries[i])
1066       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1067
1068    screen->tsc.entries[i] = entry;
1069    return i;
1070 }