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nvc0: implement multisampled images on Maxwell+
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/mme/com9097.mme.h"
36 #include "nvc0/mme/com90c0.mme.h"
37
38 #include "nv50/g80_texture.xml.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 const struct util_format_description *desc = util_format_description(format);
48
49 if (sample_count > 8)
50 return false;
51 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
52 return false;
53
54 /* Short-circuit the rest of the logic -- this is used by the state tracker
55 * to determine valid MS levels in a no-attachments scenario.
56 */
57 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
58 return true;
59
60 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
61 if (util_format_get_blocksizebits(format) == 3 * 32)
62 return false;
63
64 if (bindings & PIPE_BIND_LINEAR)
65 if (util_format_is_depth_or_stencil(format) ||
66 (target != PIPE_TEXTURE_1D &&
67 target != PIPE_TEXTURE_2D &&
68 target != PIPE_TEXTURE_RECT) ||
69 sample_count > 1)
70 return false;
71
72 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
73 */
74 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
75 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
76 /* The claim is that this should work on GM107 but it doesn't. Need to
77 * test further and figure out if it's a nouveau issue or a HW one.
78 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
79 */
80 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
81 return false;
82
83 /* shared is always supported */
84 bindings &= ~(PIPE_BIND_LINEAR |
85 PIPE_BIND_SHARED);
86
87 if (bindings & PIPE_BIND_SHADER_IMAGE) {
88 if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
89 nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
90 /* This should work on Fermi, but for currently unknown reasons it
91 * does not and results in breaking reads from pbos. */
92 return false;
93 }
94 }
95
96 return (( nvc0_format_table[format].usage |
97 nvc0_vertex_format[format].usage) & bindings) == bindings;
98 }
99
100 static int
101 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
102 {
103 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
104 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
105
106 switch (param) {
107 /* non-boolean caps */
108 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
109 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
110 return 15;
111 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
112 return 12;
113 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
114 return 2048;
115 case PIPE_CAP_MIN_TEXEL_OFFSET:
116 return -8;
117 case PIPE_CAP_MAX_TEXEL_OFFSET:
118 return 7;
119 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
120 return -32;
121 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
122 return 31;
123 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
124 return 128 * 1024 * 1024;
125 case PIPE_CAP_GLSL_FEATURE_LEVEL:
126 return 430;
127 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
128 return 140;
129 case PIPE_CAP_MAX_RENDER_TARGETS:
130 return 8;
131 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
132 return 1;
133 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
134 return 4;
135 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
136 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
137 return 128;
138 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
139 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
140 return 1024;
141 case PIPE_CAP_MAX_VERTEX_STREAMS:
142 return 4;
143 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
144 return 2048;
145 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
146 return 256;
147 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
148 if (class_3d < GM107_3D_CLASS)
149 return 256; /* IMAGE bindings require alignment to 256 */
150 return 16;
151 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
152 return 16;
153 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
154 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
155 case PIPE_CAP_MAX_VIEWPORTS:
156 return NVC0_MAX_VIEWPORTS;
157 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
158 return 4;
159 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
160 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
161 case PIPE_CAP_ENDIANNESS:
162 return PIPE_ENDIAN_LITTLE;
163 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
164 return 30;
165 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
166 return NVC0_MAX_WINDOW_RECTANGLES;
167 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
168 return class_3d >= GM200_3D_CLASS ? 8 : 0;
169
170 /* supported caps */
171 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
172 case PIPE_CAP_TEXTURE_SWIZZLE:
173 case PIPE_CAP_NPOT_TEXTURES:
174 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
175 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
176 case PIPE_CAP_ANISOTROPIC_FILTER:
177 case PIPE_CAP_SEAMLESS_CUBE_MAP:
178 case PIPE_CAP_CUBE_MAP_ARRAY:
179 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
180 case PIPE_CAP_TEXTURE_MULTISAMPLE:
181 case PIPE_CAP_DEPTH_CLIP_DISABLE:
182 case PIPE_CAP_POINT_SPRITE:
183 case PIPE_CAP_TGSI_TEXCOORD:
184 case PIPE_CAP_SM3:
185 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
186 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
187 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
188 case PIPE_CAP_QUERY_TIMESTAMP:
189 case PIPE_CAP_QUERY_TIME_ELAPSED:
190 case PIPE_CAP_OCCLUSION_QUERY:
191 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
192 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
193 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
194 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
195 case PIPE_CAP_INDEP_BLEND_ENABLE:
196 case PIPE_CAP_INDEP_BLEND_FUNC:
197 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
198 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
199 case PIPE_CAP_PRIMITIVE_RESTART:
200 case PIPE_CAP_TGSI_INSTANCEID:
201 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
202 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
203 case PIPE_CAP_CONDITIONAL_RENDER:
204 case PIPE_CAP_TEXTURE_BARRIER:
205 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
206 case PIPE_CAP_START_INSTANCE:
207 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
208 case PIPE_CAP_DRAW_INDIRECT:
209 case PIPE_CAP_USER_VERTEX_BUFFERS:
210 case PIPE_CAP_TEXTURE_QUERY_LOD:
211 case PIPE_CAP_SAMPLE_SHADING:
212 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
213 case PIPE_CAP_TEXTURE_GATHER_SM5:
214 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
215 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
216 case PIPE_CAP_SAMPLER_VIEW_TARGET:
217 case PIPE_CAP_CLIP_HALFZ:
218 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
219 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
220 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
221 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
222 case PIPE_CAP_DEPTH_BOUNDS_TEST:
223 case PIPE_CAP_TGSI_TXQS:
224 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
225 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
226 case PIPE_CAP_SHAREABLE_SHADERS:
227 case PIPE_CAP_CLEAR_TEXTURE:
228 case PIPE_CAP_DRAW_PARAMETERS:
229 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
230 case PIPE_CAP_MULTI_DRAW_INDIRECT:
231 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
232 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
233 case PIPE_CAP_QUERY_BUFFER_OBJECT:
234 case PIPE_CAP_INVALIDATE_BUFFER:
235 case PIPE_CAP_STRING_MARKER:
236 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
237 case PIPE_CAP_CULL_DISTANCE:
238 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
239 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
240 case PIPE_CAP_TGSI_VOTE:
241 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
242 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
243 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
244 case PIPE_CAP_DOUBLES:
245 case PIPE_CAP_INT64:
246 case PIPE_CAP_TGSI_TEX_TXF_LZ:
247 case PIPE_CAP_TGSI_CLOCK:
248 case PIPE_CAP_COMPUTE:
249 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
250 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
251 case PIPE_CAP_QUERY_SO_OVERFLOW:
252 return 1;
253 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
254 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
255 case PIPE_CAP_TGSI_FS_FBFETCH:
256 return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
257 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
258 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
259 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
260 case PIPE_CAP_POST_DEPTH_COVERAGE:
261 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
262 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
263 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
264 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
265 return class_3d >= GM200_3D_CLASS;
266 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
267 return class_3d >= GP100_3D_CLASS;
268 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
269 case PIPE_CAP_TGSI_BALLOT:
270 case PIPE_CAP_BINDLESS_TEXTURE:
271 return class_3d >= NVE4_3D_CLASS;
272
273 /* unsupported caps */
274 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
275 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
276 case PIPE_CAP_SHADER_STENCIL_EXPORT:
277 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
278 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
279 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
280 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
281 case PIPE_CAP_FAKE_SW_MSAA:
282 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
283 case PIPE_CAP_VERTEXID_NOBASE:
284 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
285 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
286 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
287 case PIPE_CAP_GENERATE_MIPMAP:
288 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
289 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
290 case PIPE_CAP_QUERY_MEMORY_INFO:
291 case PIPE_CAP_PCI_GROUP:
292 case PIPE_CAP_PCI_BUS:
293 case PIPE_CAP_PCI_DEVICE:
294 case PIPE_CAP_PCI_FUNCTION:
295 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
296 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
297 case PIPE_CAP_NATIVE_FENCE_FD:
298 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
299 case PIPE_CAP_INT64_DIVMOD:
300 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
301 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
302 case PIPE_CAP_MEMOBJ:
303 case PIPE_CAP_LOAD_CONSTBUF:
304 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
305 case PIPE_CAP_TILE_RASTER_ORDER:
306 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
307 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
308 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
309 case PIPE_CAP_FENCE_SIGNAL:
310 case PIPE_CAP_CONSTBUF0_FLAGS:
311 case PIPE_CAP_PACKED_UNIFORMS:
312 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
313 return 0;
314
315 case PIPE_CAP_VENDOR_ID:
316 return 0x10de;
317 case PIPE_CAP_DEVICE_ID: {
318 uint64_t device_id;
319 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
320 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
321 return -1;
322 }
323 return device_id;
324 }
325 case PIPE_CAP_ACCELERATED:
326 return 1;
327 case PIPE_CAP_VIDEO_MEMORY:
328 return dev->vram_size >> 20;
329 case PIPE_CAP_UMA:
330 return 0;
331 }
332
333 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
334 return 0;
335 }
336
337 static int
338 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
339 enum pipe_shader_type shader,
340 enum pipe_shader_cap param)
341 {
342 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
343
344 switch (shader) {
345 case PIPE_SHADER_VERTEX:
346 case PIPE_SHADER_GEOMETRY:
347 case PIPE_SHADER_FRAGMENT:
348 case PIPE_SHADER_COMPUTE:
349 case PIPE_SHADER_TESS_CTRL:
350 case PIPE_SHADER_TESS_EVAL:
351 break;
352 default:
353 return 0;
354 }
355
356 switch (param) {
357 case PIPE_SHADER_CAP_PREFERRED_IR:
358 return PIPE_SHADER_IR_TGSI;
359 case PIPE_SHADER_CAP_SUPPORTED_IRS:
360 return 1 << PIPE_SHADER_IR_TGSI;
361 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
362 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
363 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
364 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
365 return 16384;
366 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
367 return 16;
368 case PIPE_SHADER_CAP_MAX_INPUTS:
369 if (shader == PIPE_SHADER_VERTEX)
370 return 32;
371 /* NOTE: These only count our slots for GENERIC varyings.
372 * The address space may be larger, but the actual hard limit seems to be
373 * less than what the address space layout permits, so don't add TEXCOORD,
374 * COLOR, etc. here.
375 */
376 if (shader == PIPE_SHADER_FRAGMENT)
377 return 0x1f0 / 16;
378 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
379 * and excludes 0x60 per-patch inputs.
380 */
381 return 0x200 / 16;
382 case PIPE_SHADER_CAP_MAX_OUTPUTS:
383 return 32;
384 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
385 return 65536;
386 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
387 return NVC0_MAX_PIPE_CONSTBUFS;
388 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
389 return shader != PIPE_SHADER_FRAGMENT;
390 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
391 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
392 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
393 return 1;
394 case PIPE_SHADER_CAP_MAX_TEMPS:
395 return NVC0_CAP_MAX_PROGRAM_TEMPS;
396 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
397 return 1;
398 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
399 return 1;
400 case PIPE_SHADER_CAP_SUBROUTINES:
401 return 1;
402 case PIPE_SHADER_CAP_INTEGERS:
403 return 1;
404 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
405 return 1;
406 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
407 return 1;
408 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
409 return 1;
410 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
411 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
412 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
413 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
414 case PIPE_SHADER_CAP_INT64_ATOMICS:
415 case PIPE_SHADER_CAP_FP16:
416 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
417 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
418 return 0;
419 case PIPE_SHADER_CAP_SCALAR_ISA:
420 return 1;
421 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
422 return NVC0_MAX_BUFFERS;
423 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
424 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
425 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
426 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
427 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
428 return 32;
429 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
430 if (class_3d >= NVE4_3D_CLASS)
431 return NVC0_MAX_IMAGES;
432 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
433 return NVC0_MAX_IMAGES;
434 return 0;
435 default:
436 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
437 return 0;
438 }
439 }
440
441 static float
442 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
443 {
444 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
445
446 switch (param) {
447 case PIPE_CAPF_MAX_LINE_WIDTH:
448 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
449 return 10.0f;
450 case PIPE_CAPF_MAX_POINT_WIDTH:
451 return 63.0f;
452 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
453 return 63.375f;
454 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
455 return 16.0f;
456 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
457 return 15.0f;
458 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
459 return 0.0f;
460 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
461 return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
462 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
463 return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
464 }
465
466 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
467 return 0.0f;
468 }
469
470 static int
471 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
472 enum pipe_shader_ir ir_type,
473 enum pipe_compute_cap param, void *data)
474 {
475 struct nvc0_screen *screen = nvc0_screen(pscreen);
476 const uint16_t obj_class = screen->compute->oclass;
477
478 #define RET(x) do { \
479 if (data) \
480 memcpy(data, x, sizeof(x)); \
481 return sizeof(x); \
482 } while (0)
483
484 switch (param) {
485 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
486 RET((uint64_t []) { 3 });
487 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
488 if (obj_class >= NVE4_COMPUTE_CLASS) {
489 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
490 } else {
491 RET(((uint64_t []) { 65535, 65535, 65535 }));
492 }
493 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
494 RET(((uint64_t []) { 1024, 1024, 64 }));
495 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
496 RET((uint64_t []) { 1024 });
497 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
498 if (obj_class >= NVE4_COMPUTE_CLASS) {
499 RET((uint64_t []) { 1024 });
500 } else {
501 RET((uint64_t []) { 512 });
502 }
503 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
504 RET((uint64_t []) { 1ULL << 40 });
505 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
506 switch (obj_class) {
507 case GM200_COMPUTE_CLASS:
508 RET((uint64_t []) { 96 << 10 });
509 break;
510 case GM107_COMPUTE_CLASS:
511 RET((uint64_t []) { 64 << 10 });
512 break;
513 default:
514 RET((uint64_t []) { 48 << 10 });
515 break;
516 }
517 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
518 RET((uint64_t []) { 512 << 10 });
519 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
520 RET((uint64_t []) { 4096 });
521 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
522 RET((uint32_t []) { 32 });
523 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
524 RET((uint64_t []) { 1ULL << 40 });
525 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
526 RET((uint32_t []) { 0 });
527 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
528 RET((uint32_t []) { screen->mp_count_compute });
529 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
530 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
531 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
532 RET((uint32_t []) { 64 });
533 default:
534 return 0;
535 }
536
537 #undef RET
538 }
539
540 static void
541 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
542 unsigned sample_count,
543 unsigned *width, unsigned *height)
544 {
545 switch (sample_count) {
546 case 0:
547 case 1:
548 /* this could be 4x4, but the GL state tracker makes it difficult to
549 * create a 1x MSAA texture and smaller grids save CB space */
550 *width = 2;
551 *height = 4;
552 break;
553 case 2:
554 *width = 2;
555 *height = 4;
556 break;
557 case 4:
558 *width = 2;
559 *height = 2;
560 break;
561 case 8:
562 *width = 1;
563 *height = 2;
564 break;
565 default:
566 assert(0);
567 }
568 }
569
570 static void
571 nvc0_screen_destroy(struct pipe_screen *pscreen)
572 {
573 struct nvc0_screen *screen = nvc0_screen(pscreen);
574
575 if (!nouveau_drm_screen_unref(&screen->base))
576 return;
577
578 if (screen->base.fence.current) {
579 struct nouveau_fence *current = NULL;
580
581 /* nouveau_fence_wait will create a new current fence, so wait on the
582 * _current_ one, and remove both.
583 */
584 nouveau_fence_ref(screen->base.fence.current, &current);
585 nouveau_fence_wait(current, NULL);
586 nouveau_fence_ref(NULL, &current);
587 nouveau_fence_ref(NULL, &screen->base.fence.current);
588 }
589 if (screen->base.pushbuf)
590 screen->base.pushbuf->user_priv = NULL;
591
592 if (screen->blitter)
593 nvc0_blitter_destroy(screen);
594 if (screen->pm.prog) {
595 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
596 nvc0_program_destroy(NULL, screen->pm.prog);
597 FREE(screen->pm.prog);
598 }
599
600 nouveau_bo_ref(NULL, &screen->text);
601 nouveau_bo_ref(NULL, &screen->uniform_bo);
602 nouveau_bo_ref(NULL, &screen->tls);
603 nouveau_bo_ref(NULL, &screen->txc);
604 nouveau_bo_ref(NULL, &screen->fence.bo);
605 nouveau_bo_ref(NULL, &screen->poly_cache);
606
607 nouveau_heap_destroy(&screen->lib_code);
608 nouveau_heap_destroy(&screen->text_heap);
609
610 FREE(screen->default_tsc);
611 FREE(screen->tic.entries);
612
613 nouveau_object_del(&screen->eng3d);
614 nouveau_object_del(&screen->eng2d);
615 nouveau_object_del(&screen->m2mf);
616 nouveau_object_del(&screen->compute);
617 nouveau_object_del(&screen->nvsw);
618
619 nouveau_screen_fini(&screen->base);
620
621 FREE(screen);
622 }
623
624 static int
625 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
626 unsigned size, const uint32_t *data)
627 {
628 struct nouveau_pushbuf *push = screen->base.pushbuf;
629
630 size /= 4;
631
632 assert((pos + size) <= 0x800);
633
634 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
635 PUSH_DATA (push, (m - 0x3800) / 8);
636 PUSH_DATA (push, pos);
637 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
638 PUSH_DATA (push, pos);
639 PUSH_DATAp(push, data, size);
640
641 return pos + size;
642 }
643
644 static void
645 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
646 {
647 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
648 PUSH_DATA (push, 0xff);
649 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
650 PUSH_DATA (push, 0xff);
651 PUSH_DATA (push, 0xff);
652 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
653 PUSH_DATA (push, 0xff);
654 PUSH_DATA (push, 0xff);
655 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
656 PUSH_DATA (push, 0x3f);
657
658 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
659 PUSH_DATA (push, (3 << 16) | 3);
660 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
661 PUSH_DATA (push, (2 << 16) | 2);
662
663 if (obj_class < GM107_3D_CLASS) {
664 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
665 PUSH_DATA (push, 0);
666 }
667 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
668 PUSH_DATA (push, 0x10);
669 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
670 PUSH_DATA (push, 0x10);
671 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
672 PUSH_DATA (push, 0x10);
673 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
674 PUSH_DATA (push, 0x10);
675 PUSH_DATA (push, 0x10);
676 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
677 PUSH_DATA (push, 0x10);
678 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
679 PUSH_DATA (push, 0xe);
680
681 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
682 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
683 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
684 PUSH_DATA (push, 0);
685 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
686 PUSH_DATA (push, 3);
687
688 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
689 PUSH_DATA (push, 0x3fffff);
690 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
691 PUSH_DATA (push, 1);
692 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
693 PUSH_DATA (push, 1);
694
695 if (obj_class < GM107_3D_CLASS) {
696 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
697 PUSH_DATA (push, 3);
698
699 if (obj_class >= NVE4_3D_CLASS) {
700 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
701 PUSH_DATA (push, 1);
702 }
703 }
704
705 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
706 * are supposed to do */
707 }
708
709 static void
710 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
711 {
712 struct nvc0_screen *screen = nvc0_screen(pscreen);
713 struct nouveau_pushbuf *push = screen->base.pushbuf;
714
715 /* we need to do it after possible flush in MARK_RING */
716 *sequence = ++screen->base.fence.sequence;
717
718 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
719 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
720 PUSH_DATAh(push, screen->fence.bo->offset);
721 PUSH_DATA (push, screen->fence.bo->offset);
722 PUSH_DATA (push, *sequence);
723 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
724 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
725 }
726
727 static u32
728 nvc0_screen_fence_update(struct pipe_screen *pscreen)
729 {
730 struct nvc0_screen *screen = nvc0_screen(pscreen);
731 return screen->fence.map[0];
732 }
733
734 static int
735 nvc0_screen_init_compute(struct nvc0_screen *screen)
736 {
737 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
738
739 switch (screen->base.device->chipset & ~0xf) {
740 case 0xc0:
741 case 0xd0:
742 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
743 case 0xe0:
744 case 0xf0:
745 case 0x100:
746 case 0x110:
747 case 0x120:
748 case 0x130:
749 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
750 default:
751 return -1;
752 }
753 }
754
755 static int
756 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
757 uint32_t lpos, uint32_t lneg, uint32_t cstack)
758 {
759 struct nouveau_bo *bo = NULL;
760 int ret;
761 uint64_t size = (lpos + lneg) * 32 + cstack;
762
763 if (size >= (1 << 20)) {
764 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
765 return -1;
766 }
767
768 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
769 size = align(size, 0x8000);
770 size *= screen->mp_count;
771
772 size = align(size, 1 << 17);
773
774 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
775 NULL, &bo);
776 if (ret)
777 return ret;
778
779 /* Make sure that the pushbuf has acquired a reference to the old tls
780 * segment, as it may have commands that will reference it.
781 */
782 if (screen->tls)
783 PUSH_REFN(screen->base.pushbuf, screen->tls,
784 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
785 nouveau_bo_ref(NULL, &screen->tls);
786 screen->tls = bo;
787 return 0;
788 }
789
790 int
791 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
792 {
793 struct nouveau_pushbuf *push = screen->base.pushbuf;
794 struct nouveau_bo *bo;
795 int ret;
796
797 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
798 1 << 17, size, NULL, &bo);
799 if (ret)
800 return ret;
801
802 /* Make sure that the pushbuf has acquired a reference to the old text
803 * segment, as it may have commands that will reference it.
804 */
805 if (screen->text)
806 PUSH_REFN(push, screen->text,
807 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
808 nouveau_bo_ref(NULL, &screen->text);
809 screen->text = bo;
810
811 nouveau_heap_destroy(&screen->lib_code);
812 nouveau_heap_destroy(&screen->text_heap);
813
814 /* XXX: getting a page fault at the end of the code buffer every few
815 * launches, don't use the last 256 bytes to work around them - prefetch ?
816 */
817 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
818
819 /* update the code segment setup */
820 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
821 PUSH_DATAh(push, screen->text->offset);
822 PUSH_DATA (push, screen->text->offset);
823 if (screen->compute) {
824 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
825 PUSH_DATAh(push, screen->text->offset);
826 PUSH_DATA (push, screen->text->offset);
827 }
828
829 return 0;
830 }
831
832 #define FAIL_SCREEN_INIT(str, err) \
833 do { \
834 NOUVEAU_ERR(str, err); \
835 goto fail; \
836 } while(0)
837
838 struct nouveau_screen *
839 nvc0_screen_create(struct nouveau_device *dev)
840 {
841 struct nvc0_screen *screen;
842 struct pipe_screen *pscreen;
843 struct nouveau_object *chan;
844 struct nouveau_pushbuf *push;
845 uint64_t value;
846 uint32_t obj_class;
847 uint32_t flags;
848 int ret;
849 unsigned i;
850
851 switch (dev->chipset & ~0xf) {
852 case 0xc0:
853 case 0xd0:
854 case 0xe0:
855 case 0xf0:
856 case 0x100:
857 case 0x110:
858 case 0x120:
859 case 0x130:
860 break;
861 default:
862 return NULL;
863 }
864
865 screen = CALLOC_STRUCT(nvc0_screen);
866 if (!screen)
867 return NULL;
868 pscreen = &screen->base.base;
869 pscreen->destroy = nvc0_screen_destroy;
870
871 ret = nouveau_screen_init(&screen->base, dev);
872 if (ret)
873 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
874 chan = screen->base.channel;
875 push = screen->base.pushbuf;
876 push->user_priv = screen;
877 push->rsvd_kick = 5;
878
879 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
880 PIPE_BIND_SHADER_BUFFER |
881 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
882 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
883 screen->base.sysmem_bindings |=
884 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
885
886 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
887 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
888 screen->base.vidmem_bindings = 0;
889 }
890
891 pscreen->context_create = nvc0_create;
892 pscreen->is_format_supported = nvc0_screen_is_format_supported;
893 pscreen->get_param = nvc0_screen_get_param;
894 pscreen->get_shader_param = nvc0_screen_get_shader_param;
895 pscreen->get_paramf = nvc0_screen_get_paramf;
896 pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
897 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
898 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
899
900 nvc0_screen_init_resource_functions(pscreen);
901
902 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
903 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
904
905 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
906 if (screen->base.drm->version >= 0x01000202)
907 flags |= NOUVEAU_BO_COHERENT;
908
909 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
910 if (ret)
911 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
912 nouveau_bo_map(screen->fence.bo, 0, NULL);
913 screen->fence.map = screen->fence.bo->map;
914 screen->base.fence.emit = nvc0_screen_fence_emit;
915 screen->base.fence.update = nvc0_screen_fence_update;
916
917
918 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
919 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
920 if (ret)
921 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
922
923 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
924 PUSH_DATA (push, screen->nvsw->handle);
925
926 switch (dev->chipset & ~0xf) {
927 case 0x130:
928 case 0x120:
929 case 0x110:
930 case 0x100:
931 case 0xf0:
932 obj_class = NVF0_P2MF_CLASS;
933 break;
934 case 0xe0:
935 obj_class = NVE4_P2MF_CLASS;
936 break;
937 default:
938 obj_class = NVC0_M2MF_CLASS;
939 break;
940 }
941 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
942 &screen->m2mf);
943 if (ret)
944 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
945
946 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
947 PUSH_DATA (push, screen->m2mf->oclass);
948 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
949 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
950 PUSH_DATA (push, 0xa0b5);
951 }
952
953 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
954 &screen->eng2d);
955 if (ret)
956 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
957
958 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
959 PUSH_DATA (push, screen->eng2d->oclass);
960 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
961 PUSH_DATA (push, 0);
962 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
963 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
964 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
965 PUSH_DATA (push, 0);
966 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
967 PUSH_DATA (push, 0);
968 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
969 PUSH_DATA (push, 0x3f);
970 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
971 PUSH_DATA (push, 1);
972 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
973 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
974
975 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
976 PUSH_DATAh(push, screen->fence.bo->offset + 16);
977 PUSH_DATA (push, screen->fence.bo->offset + 16);
978
979 switch (dev->chipset & ~0xf) {
980 case 0x130:
981 switch (dev->chipset) {
982 case 0x130:
983 case 0x13b:
984 obj_class = GP100_3D_CLASS;
985 break;
986 default:
987 obj_class = GP102_3D_CLASS;
988 break;
989 }
990 break;
991 case 0x120:
992 obj_class = GM200_3D_CLASS;
993 break;
994 case 0x110:
995 obj_class = GM107_3D_CLASS;
996 break;
997 case 0x100:
998 case 0xf0:
999 obj_class = NVF0_3D_CLASS;
1000 break;
1001 case 0xe0:
1002 switch (dev->chipset) {
1003 case 0xea:
1004 obj_class = NVEA_3D_CLASS;
1005 break;
1006 default:
1007 obj_class = NVE4_3D_CLASS;
1008 break;
1009 }
1010 break;
1011 case 0xd0:
1012 obj_class = NVC8_3D_CLASS;
1013 break;
1014 case 0xc0:
1015 default:
1016 switch (dev->chipset) {
1017 case 0xc8:
1018 obj_class = NVC8_3D_CLASS;
1019 break;
1020 case 0xc1:
1021 obj_class = NVC1_3D_CLASS;
1022 break;
1023 default:
1024 obj_class = NVC0_3D_CLASS;
1025 break;
1026 }
1027 break;
1028 }
1029 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1030 &screen->eng3d);
1031 if (ret)
1032 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1033 screen->base.class_3d = obj_class;
1034
1035 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1036 PUSH_DATA (push, screen->eng3d->oclass);
1037
1038 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1039 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1040
1041 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1042 /* kill shaders after about 1 second (at 100 MHz) */
1043 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1044 PUSH_DATA (push, 0x17);
1045 }
1046
1047 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1048 screen->base.drm->version >= 0x01000101);
1049 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1050 for (i = 0; i < 8; ++i)
1051 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1052
1053 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1054 PUSH_DATA (push, 1);
1055
1056 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1057 PUSH_DATA (push, 0);
1058 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1059 PUSH_DATA (push, 0);
1060 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1061 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1062 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1063 PUSH_DATA (push, 0);
1064 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1065 PUSH_DATA (push, 1);
1066 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1067 PUSH_DATA (push, 1);
1068 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1069 PUSH_DATA (push, 1);
1070 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1071 PUSH_DATA (push, 0);
1072 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1073 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1074 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1075 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1076 } else {
1077 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1078 PUSH_DATA (push, 15);
1079 }
1080 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1081 PUSH_DATA (push, 8); /* 128 */
1082 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1083 PUSH_DATA (push, 1);
1084 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1085 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1086 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1087 }
1088
1089 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1090
1091 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1092 if (ret)
1093 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1094
1095 /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1096 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1097 &screen->uniform_bo);
1098 if (ret)
1099 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1100
1101 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1102
1103 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1104 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1105 PUSH_DATA (push, 256);
1106 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1107 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1108 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1109 PUSH_DATA (push, 0);
1110 PUSH_DATAf(push, 0.0f);
1111 PUSH_DATAf(push, 0.0f);
1112 PUSH_DATAf(push, 0.0f);
1113 PUSH_DATAf(push, 0.0f);
1114 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1115 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1116 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1117
1118 if (screen->base.drm->version >= 0x01000101) {
1119 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1120 if (ret)
1121 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1122 } else {
1123 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1124 value = (8 << 8) | 4;
1125 else
1126 value = (16 << 8) | 4;
1127 }
1128 screen->gpc_count = value & 0x000000ff;
1129 screen->mp_count = value >> 8;
1130 screen->mp_count_compute = screen->mp_count;
1131
1132 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1133 if (ret)
1134 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1135
1136 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1137 PUSH_DATAh(push, screen->tls->offset);
1138 PUSH_DATA (push, screen->tls->offset);
1139 PUSH_DATA (push, screen->tls->size >> 32);
1140 PUSH_DATA (push, screen->tls->size);
1141 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1142 PUSH_DATA (push, 0);
1143 /* Reduce likelihood of collision with real buffers by placing the hole at
1144 * the top of the 4G area. This will have to be dealt with for real
1145 * eventually by blocking off that area from the VM.
1146 */
1147 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1148 PUSH_DATA (push, 0xff << 24);
1149
1150 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1151 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1152 &screen->poly_cache);
1153 if (ret)
1154 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1155
1156 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1157 PUSH_DATAh(push, screen->poly_cache->offset);
1158 PUSH_DATA (push, screen->poly_cache->offset);
1159 PUSH_DATA (push, 3);
1160 }
1161
1162 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1163 &screen->txc);
1164 if (ret)
1165 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1166
1167 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1168 PUSH_DATAh(push, screen->txc->offset);
1169 PUSH_DATA (push, screen->txc->offset);
1170 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1171 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1172 screen->tic.maxwell = true;
1173 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1174 screen->tic.maxwell =
1175 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1176 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1177 }
1178 }
1179
1180 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1181 PUSH_DATAh(push, screen->txc->offset + 65536);
1182 PUSH_DATA (push, screen->txc->offset + 65536);
1183 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1184
1185 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1186 PUSH_DATA (push, 0);
1187 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1188 PUSH_DATA (push, 0);
1189 PUSH_DATA (push, 0);
1190 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1191 PUSH_DATA (push, 0x3f);
1192
1193 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1194 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1195 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1196 for (i = 0; i < 8 * 2; ++i)
1197 PUSH_DATA(push, 0);
1198 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1199 PUSH_DATA (push, 0);
1200 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1201 PUSH_DATA (push, 0);
1202
1203 /* neither scissors, viewport nor stencil mask should affect clears */
1204 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1205 PUSH_DATA (push, 0);
1206
1207 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1208 PUSH_DATA (push, 1);
1209 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1210 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1211 PUSH_DATAf(push, 0.0f);
1212 PUSH_DATAf(push, 1.0f);
1213 }
1214 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1215 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1216
1217 /* We use scissors instead of exact view volume clipping,
1218 * so they're always enabled.
1219 */
1220 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1221 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1222 PUSH_DATA (push, 1);
1223 PUSH_DATA (push, 8192 << 16);
1224 PUSH_DATA (push, 8192 << 16);
1225 }
1226
1227 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1228
1229 i = 0;
1230 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1231 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1232 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1233 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1234 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1235 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1236 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1237 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1238 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1239 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1240 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1241 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1242 MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1243 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1244
1245 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1246 PUSH_DATA (push, 1);
1247 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1248 PUSH_DATA (push, 1);
1249 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1250 PUSH_DATA (push, 0x40);
1251 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1252 PUSH_DATA (push, 0);
1253 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1254 PUSH_DATA (push, 0x30);
1255 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1256 PUSH_DATA (push, 3);
1257 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1258 PUSH_DATA (push, 0x20);
1259 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1260 PUSH_DATA (push, 0x00);
1261 screen->save_state.patch_vertices = 3;
1262
1263 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1264 PUSH_DATA (push, 0);
1265 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1266 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1267
1268 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1269
1270 if (nvc0_screen_init_compute(screen))
1271 goto fail;
1272
1273 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1274 for (i = 0; i < 5; ++i) {
1275 /* TIC and TSC entries for each unit (nve4+ only) */
1276 /* auxiliary constants (6 user clip planes, base instance id) */
1277 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1278 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1279 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1280 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1281 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1282 PUSH_DATA (push, (15 << 4) | 1);
1283 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1284 unsigned j;
1285 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1286 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1287 for (j = 0; j < 8; ++j)
1288 PUSH_DATA(push, j);
1289 } else {
1290 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1291 PUSH_DATA (push, 0x54);
1292 }
1293
1294 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1295 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1296 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1297 PUSH_DATA (push, 0); /* 0 */
1298 PUSH_DATA (push, 0);
1299 PUSH_DATA (push, 1); /* 1 */
1300 PUSH_DATA (push, 0);
1301 PUSH_DATA (push, 0); /* 2 */
1302 PUSH_DATA (push, 1);
1303 PUSH_DATA (push, 1); /* 3 */
1304 PUSH_DATA (push, 1);
1305 PUSH_DATA (push, 2); /* 4 */
1306 PUSH_DATA (push, 0);
1307 PUSH_DATA (push, 3); /* 5 */
1308 PUSH_DATA (push, 0);
1309 PUSH_DATA (push, 2); /* 6 */
1310 PUSH_DATA (push, 1);
1311 PUSH_DATA (push, 3); /* 7 */
1312 PUSH_DATA (push, 1);
1313 }
1314 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1315 PUSH_DATA (push, 0);
1316
1317 PUSH_KICK (push);
1318
1319 screen->tic.entries = CALLOC(
1320 NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1321 sizeof(void *));
1322 screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1323 screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1324
1325 if (!nvc0_blitter_create(screen))
1326 goto fail;
1327
1328 screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1329 screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1330
1331 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1332
1333 return &screen->base;
1334
1335 fail:
1336 screen->base.base.context_create = NULL;
1337 return &screen->base;
1338 }
1339
1340 int
1341 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1342 {
1343 int i = screen->tic.next;
1344
1345 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1346 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1347
1348 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1349
1350 if (screen->tic.entries[i])
1351 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1352
1353 screen->tic.entries[i] = entry;
1354 return i;
1355 }
1356
1357 int
1358 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1359 {
1360 int i = screen->tsc.next;
1361
1362 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1363 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1364
1365 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1366
1367 if (screen->tsc.entries[i])
1368 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1369
1370 screen->tsc.entries[i] = entry;
1371 return i;
1372 }