src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/mme/com9097.mme.h"
  36 #include "nvc0/mme/com90c0.mme.h"
  37
  38 #include "nv50/g80_texture.xml.h"
  39
  40 static boolean
  41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  42                                 enum pipe_format format,
  43                                 enum pipe_texture_target target,
  44                                 unsigned sample_count,
  45                                 unsigned storage_sample_count,
  46                                 unsigned bindings)
  47 {
  48    const struct util_format_description *desc = util_format_description(format);
  49
  50    if (sample_count > 8)
  51       return false;
  52    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  53       return false;
  54
  55    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  56       return false;
  57
  58    /* Short-circuit the rest of the logic -- this is used by the state tracker
  59     * to determine valid MS levels in a no-attachments scenario.
  60     */
  61    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  62       return true;
  63
  64    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  65       if (util_format_get_blocksizebits(format) == 3 * 32)
  66          return false;
  67
  68    if (bindings & PIPE_BIND_LINEAR)
  69       if (util_format_is_depth_or_stencil(format) ||
  70           (target != PIPE_TEXTURE_1D &&
  71            target != PIPE_TEXTURE_2D &&
  72            target != PIPE_TEXTURE_RECT) ||
  73           sample_count > 1)
  74          return false;
  75
  76    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  77     */
  78    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  79         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  80        /* The claim is that this should work on GM107 but it doesn't. Need to
  81         * test further and figure out if it's a nouveau issue or a HW one.
  82        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  83         */
  84        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  85       return false;
  86
  87    /* shared is always supported */
  88    bindings &= ~(PIPE_BIND_LINEAR |
  89                  PIPE_BIND_SHARED);
  90
  91    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  92       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  93           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
  94          /* This should work on Fermi, but for currently unknown reasons it
  95           * does not and results in breaking reads from pbos. */
  96          return false;
  97       }
  98    }
  99
 100    return (( nvc0_format_table[format].usage |
 101             nvc0_vertex_format[format].usage) & bindings) == bindings;
 102 }
 103
 104 static int
 105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 106 {
 107    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 108    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 109
 110    switch (param) {
 111    /* non-boolean caps */
 112    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 113    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 114       return 15;
 115    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 116       return 12;
 117    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 118       return 2048;
 119    case PIPE_CAP_MIN_TEXEL_OFFSET:
 120       return -8;
 121    case PIPE_CAP_MAX_TEXEL_OFFSET:
 122       return 7;
 123    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 124       return -32;
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126       return 31;
 127    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 128       return 128 * 1024 * 1024;
 129    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 130       return 430;
 131    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 132       return 140;
 133    case PIPE_CAP_MAX_RENDER_TARGETS:
 134       return 8;
 135    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 136       return 1;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 138       return 4;
 139    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 140    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 141       return 128;
 142    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 143    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 144       return 1024;
 145    case PIPE_CAP_MAX_VERTEX_STREAMS:
 146       return 4;
 147    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 148       return 2048;
 149    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 150       return 256;
 151    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 152       if (class_3d < GM107_3D_CLASS)
 153          return 256; /* IMAGE bindings require alignment to 256 */
 154       return 16;
 155    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 156       return 16;
 157    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 158       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 159    case PIPE_CAP_MAX_VIEWPORTS:
 160       return NVC0_MAX_VIEWPORTS;
 161    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 162       return 4;
 163    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 164       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 165    case PIPE_CAP_ENDIANNESS:
 166       return PIPE_ENDIAN_LITTLE;
 167    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 168       return 30;
 169    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 170       return NVC0_MAX_WINDOW_RECTANGLES;
 171    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 172       return class_3d >= GM200_3D_CLASS ? 8 : 0;
 173
 174    /* supported caps */
 175    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 176    case PIPE_CAP_TEXTURE_SWIZZLE:
 177    case PIPE_CAP_NPOT_TEXTURES:
 178    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 179    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 180    case PIPE_CAP_ANISOTROPIC_FILTER:
 181    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 182    case PIPE_CAP_CUBE_MAP_ARRAY:
 183    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 184    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 185    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 186    case PIPE_CAP_POINT_SPRITE:
 187    case PIPE_CAP_TGSI_TEXCOORD:
 188    case PIPE_CAP_SM3:
 189    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 190    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 191    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 192    case PIPE_CAP_QUERY_TIMESTAMP:
 193    case PIPE_CAP_QUERY_TIME_ELAPSED:
 194    case PIPE_CAP_OCCLUSION_QUERY:
 195    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 196    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 197    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 198    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 199    case PIPE_CAP_INDEP_BLEND_ENABLE:
 200    case PIPE_CAP_INDEP_BLEND_FUNC:
 201    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 202    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 203    case PIPE_CAP_PRIMITIVE_RESTART:
 204    case PIPE_CAP_TGSI_INSTANCEID:
 205    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 206    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 207    case PIPE_CAP_CONDITIONAL_RENDER:
 208    case PIPE_CAP_TEXTURE_BARRIER:
 209    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 210    case PIPE_CAP_START_INSTANCE:
 211    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 212    case PIPE_CAP_DRAW_INDIRECT:
 213    case PIPE_CAP_USER_VERTEX_BUFFERS:
 214    case PIPE_CAP_TEXTURE_QUERY_LOD:
 215    case PIPE_CAP_SAMPLE_SHADING:
 216    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 217    case PIPE_CAP_TEXTURE_GATHER_SM5:
 218    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 219    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 220    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 221    case PIPE_CAP_CLIP_HALFZ:
 222    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 223    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 224    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 225    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 226    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 227    case PIPE_CAP_TGSI_TXQS:
 228    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 229    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 230    case PIPE_CAP_SHAREABLE_SHADERS:
 231    case PIPE_CAP_CLEAR_TEXTURE:
 232    case PIPE_CAP_DRAW_PARAMETERS:
 233    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 234    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 235    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 236    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 237    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 238    case PIPE_CAP_INVALIDATE_BUFFER:
 239    case PIPE_CAP_STRING_MARKER:
 240    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 241    case PIPE_CAP_CULL_DISTANCE:
 242    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 243    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 244    case PIPE_CAP_TGSI_VOTE:
 245    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 246    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 247    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 248    case PIPE_CAP_DOUBLES:
 249    case PIPE_CAP_INT64:
 250    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 251    case PIPE_CAP_TGSI_CLOCK:
 252    case PIPE_CAP_COMPUTE:
 253    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 254    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 255    case PIPE_CAP_QUERY_SO_OVERFLOW:
 256       return 1;
 257    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 258       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 259    case PIPE_CAP_TGSI_FS_FBFETCH:
 260       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 261    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 262    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 263    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 264    case PIPE_CAP_POST_DEPTH_COVERAGE:
 265    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 266    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 267    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 268    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 269       return class_3d >= GM200_3D_CLASS;
 270    case PIPE_CAP_MAX_GS_INVOCATIONS:
 271       return 32;
 272    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 273       return 1 << 27;
 274    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 275       return class_3d >= GP100_3D_CLASS;
 276    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 277    case PIPE_CAP_TGSI_BALLOT:
 278    case PIPE_CAP_BINDLESS_TEXTURE:
 279       return class_3d >= NVE4_3D_CLASS;
 280
 281    /* unsupported caps */
 282    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 283    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 284    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 285    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 286    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 287    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 288    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 289    case PIPE_CAP_FAKE_SW_MSAA:
 290    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 291    case PIPE_CAP_VERTEXID_NOBASE:
 292    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 293    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 294    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 295    case PIPE_CAP_GENERATE_MIPMAP:
 296    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 297    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 298    case PIPE_CAP_QUERY_MEMORY_INFO:
 299    case PIPE_CAP_PCI_GROUP:
 300    case PIPE_CAP_PCI_BUS:
 301    case PIPE_CAP_PCI_DEVICE:
 302    case PIPE_CAP_PCI_FUNCTION:
 303    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 304    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 305    case PIPE_CAP_NATIVE_FENCE_FD:
 306    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 307    case PIPE_CAP_INT64_DIVMOD:
 308    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 309    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 310    case PIPE_CAP_MEMOBJ:
 311    case PIPE_CAP_LOAD_CONSTBUF:
 312    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 313    case PIPE_CAP_TILE_RASTER_ORDER:
 314    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 315    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 316    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 317    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 318    case PIPE_CAP_FENCE_SIGNAL:
 319    case PIPE_CAP_CONSTBUF0_FLAGS:
 320    case PIPE_CAP_PACKED_UNIFORMS:
 321    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 322       return 0;
 323
 324    case PIPE_CAP_VENDOR_ID:
 325       return 0x10de;
 326    case PIPE_CAP_DEVICE_ID: {
 327       uint64_t device_id;
 328       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 329          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 330          return -1;
 331       }
 332       return device_id;
 333    }
 334    case PIPE_CAP_ACCELERATED:
 335       return 1;
 336    case PIPE_CAP_VIDEO_MEMORY:
 337       return dev->vram_size >> 20;
 338    case PIPE_CAP_UMA:
 339       return 0;
 340    }
 341
 342    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 343    return 0;
 344 }
 345
 346 static int
 347 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 348                              enum pipe_shader_type shader,
 349                              enum pipe_shader_cap param)
 350 {
 351    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 352
 353    switch (shader) {
 354    case PIPE_SHADER_VERTEX:
 355    case PIPE_SHADER_GEOMETRY:
 356    case PIPE_SHADER_FRAGMENT:
 357    case PIPE_SHADER_COMPUTE:
 358    case PIPE_SHADER_TESS_CTRL:
 359    case PIPE_SHADER_TESS_EVAL:
 360       break;
 361    default:
 362       return 0;
 363    }
 364
 365    switch (param) {
 366    case PIPE_SHADER_CAP_PREFERRED_IR:
 367       return PIPE_SHADER_IR_TGSI;
 368    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 369       return 1 << PIPE_SHADER_IR_TGSI;
 370    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 371    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 372    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 373    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 374       return 16384;
 375    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 376       return 16;
 377    case PIPE_SHADER_CAP_MAX_INPUTS:
 378       if (shader == PIPE_SHADER_VERTEX)
 379          return 32;
 380       /* NOTE: These only count our slots for GENERIC varyings.
 381        * The address space may be larger, but the actual hard limit seems to be
 382        * less than what the address space layout permits, so don't add TEXCOORD,
 383        * COLOR, etc. here.
 384        */
 385       if (shader == PIPE_SHADER_FRAGMENT)
 386          return 0x1f0 / 16;
 387       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 388        * and excludes 0x60 per-patch inputs.
 389        */
 390       return 0x200 / 16;
 391    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 392       return 32;
 393    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 394       return NVC0_MAX_CONSTBUF_SIZE;
 395    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 396       return NVC0_MAX_PIPE_CONSTBUFS;
 397    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 398       return shader != PIPE_SHADER_FRAGMENT;
 399    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 400    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 401    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 402       return 1;
 403    case PIPE_SHADER_CAP_MAX_TEMPS:
 404       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 405    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 406       return 1;
 407    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 408       return 1;
 409    case PIPE_SHADER_CAP_SUBROUTINES:
 410       return 1;
 411    case PIPE_SHADER_CAP_INTEGERS:
 412       return 1;
 413    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 414       return 1;
 415    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 416       return 1;
 417    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 418       return 1;
 419    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 420    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 421    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 422    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 423    case PIPE_SHADER_CAP_INT64_ATOMICS:
 424    case PIPE_SHADER_CAP_FP16:
 425    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 426    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 427       return 0;
 428    case PIPE_SHADER_CAP_SCALAR_ISA:
 429       return 1;
 430    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 431       return NVC0_MAX_BUFFERS;
 432    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 433       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 434    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 435       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 436    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 437       return 32;
 438    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 439       if (class_3d >= NVE4_3D_CLASS)
 440          return NVC0_MAX_IMAGES;
 441       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 442          return NVC0_MAX_IMAGES;
 443       return 0;
 444    default:
 445       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 446       return 0;
 447    }
 448 }
 449
 450 static float
 451 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 452 {
 453    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 454
 455    switch (param) {
 456    case PIPE_CAPF_MAX_LINE_WIDTH:
 457    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 458       return 10.0f;
 459    case PIPE_CAPF_MAX_POINT_WIDTH:
 460       return 63.0f;
 461    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 462       return 63.375f;
 463    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 464       return 16.0f;
 465    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 466       return 15.0f;
 467    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 468       return 0.0f;
 469    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 470       return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
 471    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 472       return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
 473    }
 474
 475    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 476    return 0.0f;
 477 }
 478
 479 static int
 480 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 481                               enum pipe_shader_ir ir_type,
 482                               enum pipe_compute_cap param, void *data)
 483 {
 484    struct nvc0_screen *screen = nvc0_screen(pscreen);
 485    const uint16_t obj_class = screen->compute->oclass;
 486
 487 #define RET(x) do {                  \
 488    if (data)                         \
 489       memcpy(data, x, sizeof(x));    \
 490    return sizeof(x);                 \
 491 } while (0)
 492
 493    switch (param) {
 494    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 495       RET((uint64_t []) { 3 });
 496    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 497       if (obj_class >= NVE4_COMPUTE_CLASS) {
 498          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 499       } else {
 500          RET(((uint64_t []) { 65535, 65535, 65535 }));
 501       }
 502    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 503       RET(((uint64_t []) { 1024, 1024, 64 }));
 504    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 505       RET((uint64_t []) { 1024 });
 506    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 507       if (obj_class >= NVE4_COMPUTE_CLASS) {
 508          RET((uint64_t []) { 1024 });
 509       } else {
 510          RET((uint64_t []) { 512 });
 511       }
 512    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 513       RET((uint64_t []) { 1ULL << 40 });
 514    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 515       switch (obj_class) {
 516       case GM200_COMPUTE_CLASS:
 517          RET((uint64_t []) { 96 << 10 });
 518          break;
 519       case GM107_COMPUTE_CLASS:
 520          RET((uint64_t []) { 64 << 10 });
 521          break;
 522       default:
 523          RET((uint64_t []) { 48 << 10 });
 524          break;
 525       }
 526    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 527       RET((uint64_t []) { 512 << 10 });
 528    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 529       RET((uint64_t []) { 4096 });
 530    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 531       RET((uint32_t []) { 32 });
 532    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 533       RET((uint64_t []) { 1ULL << 40 });
 534    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 535       RET((uint32_t []) { 0 });
 536    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 537       RET((uint32_t []) { screen->mp_count_compute });
 538    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 539       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 540    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 541       RET((uint32_t []) { 64 });
 542    default:
 543       return 0;
 544    }
 545
 546 #undef RET
 547 }
 548
 549 static void
 550 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
 551                                   unsigned sample_count,
 552                                   unsigned *width, unsigned *height)
 553 {
 554    switch (sample_count) {
 555    case 0:
 556    case 1:
 557       /* this could be 4x4, but the GL state tracker makes it difficult to
 558        * create a 1x MSAA texture and smaller grids save CB space */
 559       *width = 2;
 560       *height = 4;
 561       break;
 562    case 2:
 563       *width = 2;
 564       *height = 4;
 565       break;
 566    case 4:
 567       *width = 2;
 568       *height = 2;
 569       break;
 570    case 8:
 571       *width = 1;
 572       *height = 2;
 573       break;
 574    default:
 575       assert(0);
 576    }
 577 }
 578
 579 static void
 580 nvc0_screen_destroy(struct pipe_screen *pscreen)
 581 {
 582    struct nvc0_screen *screen = nvc0_screen(pscreen);
 583
 584    if (!nouveau_drm_screen_unref(&screen->base))
 585       return;
 586
 587    if (screen->base.fence.current) {
 588       struct nouveau_fence *current = NULL;
 589
 590       /* nouveau_fence_wait will create a new current fence, so wait on the
 591        * _current_ one, and remove both.
 592        */
 593       nouveau_fence_ref(screen->base.fence.current, &current);
 594       nouveau_fence_wait(current, NULL);
 595       nouveau_fence_ref(NULL, &current);
 596       nouveau_fence_ref(NULL, &screen->base.fence.current);
 597    }
 598    if (screen->base.pushbuf)
 599       screen->base.pushbuf->user_priv = NULL;
 600
 601    if (screen->blitter)
 602       nvc0_blitter_destroy(screen);
 603    if (screen->pm.prog) {
 604       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 605       nvc0_program_destroy(NULL, screen->pm.prog);
 606       FREE(screen->pm.prog);
 607    }
 608
 609    nouveau_bo_ref(NULL, &screen->text);
 610    nouveau_bo_ref(NULL, &screen->uniform_bo);
 611    nouveau_bo_ref(NULL, &screen->tls);
 612    nouveau_bo_ref(NULL, &screen->txc);
 613    nouveau_bo_ref(NULL, &screen->fence.bo);
 614    nouveau_bo_ref(NULL, &screen->poly_cache);
 615
 616    nouveau_heap_destroy(&screen->lib_code);
 617    nouveau_heap_destroy(&screen->text_heap);
 618
 619    FREE(screen->default_tsc);
 620    FREE(screen->tic.entries);
 621
 622    nouveau_object_del(&screen->eng3d);
 623    nouveau_object_del(&screen->eng2d);
 624    nouveau_object_del(&screen->m2mf);
 625    nouveau_object_del(&screen->compute);
 626    nouveau_object_del(&screen->nvsw);
 627
 628    nouveau_screen_fini(&screen->base);
 629
 630    FREE(screen);
 631 }
 632
 633 static int
 634 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 635                      unsigned size, const uint32_t *data)
 636 {
 637    struct nouveau_pushbuf *push = screen->base.pushbuf;
 638
 639    size /= 4;
 640
 641    assert((pos + size) <= 0x800);
 642
 643    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 644    PUSH_DATA (push, (m - 0x3800) / 8);
 645    PUSH_DATA (push, pos);
 646    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 647    PUSH_DATA (push, pos);
 648    PUSH_DATAp(push, data, size);
 649
 650    return pos + size;
 651 }
 652
 653 static void
 654 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 655 {
 656    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 657    PUSH_DATA (push, 0xff);
 658    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 659    PUSH_DATA (push, 0xff);
 660    PUSH_DATA (push, 0xff);
 661    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 662    PUSH_DATA (push, 0xff);
 663    PUSH_DATA (push, 0xff);
 664    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 665    PUSH_DATA (push, 0x3f);
 666
 667    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 668    PUSH_DATA (push, (3 << 16) | 3);
 669    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 670    PUSH_DATA (push, (2 << 16) | 2);
 671
 672    if (obj_class < GM107_3D_CLASS) {
 673       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 674       PUSH_DATA (push, 0);
 675    }
 676    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 677    PUSH_DATA (push, 0x10);
 678    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 679    PUSH_DATA (push, 0x10);
 680    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 681    PUSH_DATA (push, 0x10);
 682    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 683    PUSH_DATA (push, 0x10);
 684    PUSH_DATA (push, 0x10);
 685    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 686    PUSH_DATA (push, 0x10);
 687    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 688    PUSH_DATA (push, 0xe);
 689
 690    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 691    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 692    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 693    PUSH_DATA (push, 0);
 694    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 695    PUSH_DATA (push, 3);
 696
 697    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 698    PUSH_DATA (push, 0x3fffff);
 699    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 700    PUSH_DATA (push, 1);
 701    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 702    PUSH_DATA (push, 1);
 703
 704    if (obj_class < GM107_3D_CLASS) {
 705       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 706       PUSH_DATA (push, 3);
 707
 708       if (obj_class >= NVE4_3D_CLASS) {
 709          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 710          PUSH_DATA (push, 1);
 711       }
 712    }
 713
 714    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 715     * are supposed to do */
 716 }
 717
 718 static void
 719 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 720 {
 721    struct nvc0_screen *screen = nvc0_screen(pscreen);
 722    struct nouveau_pushbuf *push = screen->base.pushbuf;
 723
 724    /* we need to do it after possible flush in MARK_RING */
 725    *sequence = ++screen->base.fence.sequence;
 726
 727    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 728    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 729    PUSH_DATAh(push, screen->fence.bo->offset);
 730    PUSH_DATA (push, screen->fence.bo->offset);
 731    PUSH_DATA (push, *sequence);
 732    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 733               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 734 }
 735
 736 static u32
 737 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 738 {
 739    struct nvc0_screen *screen = nvc0_screen(pscreen);
 740    return screen->fence.map[0];
 741 }
 742
 743 static int
 744 nvc0_screen_init_compute(struct nvc0_screen *screen)
 745 {
 746    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 747
 748    switch (screen->base.device->chipset & ~0xf) {
 749    case 0xc0:
 750    case 0xd0:
 751       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 752    case 0xe0:
 753    case 0xf0:
 754    case 0x100:
 755    case 0x110:
 756    case 0x120:
 757    case 0x130:
 758       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 759    default:
 760       return -1;
 761    }
 762 }
 763
 764 static int
 765 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 766                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 767 {
 768    struct nouveau_bo *bo = NULL;
 769    int ret;
 770    uint64_t size = (lpos + lneg) * 32 + cstack;
 771
 772    if (size >= (1 << 20)) {
 773       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 774       return -1;
 775    }
 776
 777    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 778    size  = align(size, 0x8000);
 779    size *= screen->mp_count;
 780
 781    size = align(size, 1 << 17);
 782
 783    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 784                         NULL, &bo);
 785    if (ret)
 786       return ret;
 787
 788    /* Make sure that the pushbuf has acquired a reference to the old tls
 789     * segment, as it may have commands that will reference it.
 790     */
 791    if (screen->tls)
 792       PUSH_REFN(screen->base.pushbuf, screen->tls,
 793                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
 794    nouveau_bo_ref(NULL, &screen->tls);
 795    screen->tls = bo;
 796    return 0;
 797 }
 798
 799 int
 800 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 801 {
 802    struct nouveau_pushbuf *push = screen->base.pushbuf;
 803    struct nouveau_bo *bo;
 804    int ret;
 805
 806    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 807                         1 << 17, size, NULL, &bo);
 808    if (ret)
 809       return ret;
 810
 811    /* Make sure that the pushbuf has acquired a reference to the old text
 812     * segment, as it may have commands that will reference it.
 813     */
 814    if (screen->text)
 815       PUSH_REFN(push, screen->text,
 816                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
 817    nouveau_bo_ref(NULL, &screen->text);
 818    screen->text = bo;
 819
 820    nouveau_heap_destroy(&screen->lib_code);
 821    nouveau_heap_destroy(&screen->text_heap);
 822
 823    /* XXX: getting a page fault at the end of the code buffer every few
 824     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 825     */
 826    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 827
 828    /* update the code segment setup */
 829    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 830    PUSH_DATAh(push, screen->text->offset);
 831    PUSH_DATA (push, screen->text->offset);
 832    if (screen->compute) {
 833       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 834       PUSH_DATAh(push, screen->text->offset);
 835       PUSH_DATA (push, screen->text->offset);
 836    }
 837
 838    return 0;
 839 }
 840
 841 void
 842 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
 843                        int stage, int index, int size, uint64_t addr)
 844 {
 845    assert(stage != 5);
 846
 847    struct nouveau_pushbuf *push = screen->base.pushbuf;
 848
 849    if (screen->base.class_3d >= GM107_3D_CLASS) {
 850       struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
 851
 852       // TODO: Better figure out the conditions in which this is needed
 853       bool serialize = binding->addr == addr && binding->size != size;
 854       if (can_serialize)
 855          serialize = serialize && *can_serialize;
 856       if (serialize) {
 857          IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 858          if (can_serialize)
 859             *can_serialize = false;
 860       }
 861
 862       binding->addr = addr;
 863       binding->size = size;
 864    }
 865
 866    if (size >= 0) {
 867       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 868       PUSH_DATA (push, size);
 869       PUSH_DATAh(push, addr);
 870       PUSH_DATA (push, addr);
 871    }
 872    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
 873 }
 874
 875 #define FAIL_SCREEN_INIT(str, err)                    \
 876    do {                                               \
 877       NOUVEAU_ERR(str, err);                          \
 878       goto fail;                                      \
 879    } while(0)
 880
 881 struct nouveau_screen *
 882 nvc0_screen_create(struct nouveau_device *dev)
 883 {
 884    struct nvc0_screen *screen;
 885    struct pipe_screen *pscreen;
 886    struct nouveau_object *chan;
 887    struct nouveau_pushbuf *push;
 888    uint64_t value;
 889    uint32_t obj_class;
 890    uint32_t flags;
 891    int ret;
 892    unsigned i;
 893
 894    switch (dev->chipset & ~0xf) {
 895    case 0xc0:
 896    case 0xd0:
 897    case 0xe0:
 898    case 0xf0:
 899    case 0x100:
 900    case 0x110:
 901    case 0x120:
 902    case 0x130:
 903       break;
 904    default:
 905       return NULL;
 906    }
 907
 908    screen = CALLOC_STRUCT(nvc0_screen);
 909    if (!screen)
 910       return NULL;
 911    pscreen = &screen->base.base;
 912    pscreen->destroy = nvc0_screen_destroy;
 913
 914    ret = nouveau_screen_init(&screen->base, dev);
 915    if (ret)
 916       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 917    chan = screen->base.channel;
 918    push = screen->base.pushbuf;
 919    push->user_priv = screen;
 920    push->rsvd_kick = 5;
 921
 922    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 923       PIPE_BIND_SHADER_BUFFER |
 924       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 925       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 926    screen->base.sysmem_bindings |=
 927       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 928
 929    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 930       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 931       screen->base.vidmem_bindings = 0;
 932    }
 933
 934    pscreen->context_create = nvc0_create;
 935    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 936    pscreen->get_param = nvc0_screen_get_param;
 937    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 938    pscreen->get_paramf = nvc0_screen_get_paramf;
 939    pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
 940    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 941    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 942
 943    nvc0_screen_init_resource_functions(pscreen);
 944
 945    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 946    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 947
 948    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 949    if (screen->base.drm->version >= 0x01000202)
 950       flags |= NOUVEAU_BO_COHERENT;
 951
 952    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 953    if (ret)
 954       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 955    nouveau_bo_map(screen->fence.bo, 0, NULL);
 956    screen->fence.map = screen->fence.bo->map;
 957    screen->base.fence.emit = nvc0_screen_fence_emit;
 958    screen->base.fence.update = nvc0_screen_fence_update;
 959
 960
 961    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 962                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 963    if (ret)
 964       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 965
 966    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 967    PUSH_DATA (push, screen->nvsw->handle);
 968
 969    switch (dev->chipset & ~0xf) {
 970    case 0x130:
 971    case 0x120:
 972    case 0x110:
 973    case 0x100:
 974    case 0xf0:
 975       obj_class = NVF0_P2MF_CLASS;
 976       break;
 977    case 0xe0:
 978       obj_class = NVE4_P2MF_CLASS;
 979       break;
 980    default:
 981       obj_class = NVC0_M2MF_CLASS;
 982       break;
 983    }
 984    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 985                             &screen->m2mf);
 986    if (ret)
 987       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 988
 989    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 990    PUSH_DATA (push, screen->m2mf->oclass);
 991    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 992       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 993       PUSH_DATA (push, 0xa0b5);
 994    }
 995
 996    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 997                             &screen->eng2d);
 998    if (ret)
 999       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1000
1001    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1002    PUSH_DATA (push, screen->eng2d->oclass);
1003    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1004    PUSH_DATA (push, 0);
1005    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1006    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1007    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1008    PUSH_DATA (push, 0);
1009    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1010    PUSH_DATA (push, 0);
1011    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1012    PUSH_DATA (push, 0x3f);
1013    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1014    PUSH_DATA (push, 1);
1015    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1016    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1017
1018    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1019    PUSH_DATAh(push, screen->fence.bo->offset + 16);
1020    PUSH_DATA (push, screen->fence.bo->offset + 16);
1021
1022    switch (dev->chipset & ~0xf) {
1023    case 0x130:
1024       switch (dev->chipset) {
1025       case 0x130:
1026       case 0x13b:
1027          obj_class = GP100_3D_CLASS;
1028          break;
1029       default:
1030          obj_class = GP102_3D_CLASS;
1031          break;
1032       }
1033       break;
1034    case 0x120:
1035       obj_class = GM200_3D_CLASS;
1036       break;
1037    case 0x110:
1038       obj_class = GM107_3D_CLASS;
1039       break;
1040    case 0x100:
1041    case 0xf0:
1042       obj_class = NVF0_3D_CLASS;
1043       break;
1044    case 0xe0:
1045       switch (dev->chipset) {
1046       case 0xea:
1047          obj_class = NVEA_3D_CLASS;
1048          break;
1049       default:
1050          obj_class = NVE4_3D_CLASS;
1051          break;
1052       }
1053       break;
1054    case 0xd0:
1055       obj_class = NVC8_3D_CLASS;
1056       break;
1057    case 0xc0:
1058    default:
1059       switch (dev->chipset) {
1060       case 0xc8:
1061          obj_class = NVC8_3D_CLASS;
1062          break;
1063       case 0xc1:
1064          obj_class = NVC1_3D_CLASS;
1065          break;
1066       default:
1067          obj_class = NVC0_3D_CLASS;
1068          break;
1069       }
1070       break;
1071    }
1072    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1073                             &screen->eng3d);
1074    if (ret)
1075       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1076    screen->base.class_3d = obj_class;
1077
1078    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1079    PUSH_DATA (push, screen->eng3d->oclass);
1080
1081    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1082    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1083
1084    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1085       /* kill shaders after about 1 second (at 100 MHz) */
1086       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1087       PUSH_DATA (push, 0x17);
1088    }
1089
1090    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1091                     screen->base.drm->version >= 0x01000101);
1092    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1093    for (i = 0; i < 8; ++i)
1094       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1095
1096    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1097    PUSH_DATA (push, 1);
1098
1099    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1100    PUSH_DATA (push, 0);
1101    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1102    PUSH_DATA (push, 0);
1103    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1104    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1105    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1106    PUSH_DATA (push, 0);
1107    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1108    PUSH_DATA (push, 1);
1109    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1110    PUSH_DATA (push, 1);
1111    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1112    PUSH_DATA (push, 1);
1113    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1114    PUSH_DATA (push, 0);
1115    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1116    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1117    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1118       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1119    } else {
1120       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1121       PUSH_DATA (push, 15);
1122    }
1123    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1124    PUSH_DATA (push, 8); /* 128 */
1125    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1126    PUSH_DATA (push, 1);
1127    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1128       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1129       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1130    }
1131
1132    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1133
1134    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1135    if (ret)
1136       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1137
1138    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1139    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1140                         &screen->uniform_bo);
1141    if (ret)
1142       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1143
1144    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1145
1146    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1147    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1148    PUSH_DATA (push, 256);
1149    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1150    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1151    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1152    PUSH_DATA (push, 0);
1153    PUSH_DATAf(push, 0.0f);
1154    PUSH_DATAf(push, 0.0f);
1155    PUSH_DATAf(push, 0.0f);
1156    PUSH_DATAf(push, 0.0f);
1157    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1158    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1159    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1160
1161    if (screen->base.drm->version >= 0x01000101) {
1162       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1163       if (ret)
1164          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1165    } else {
1166       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1167          value = (8 << 8) | 4;
1168       else
1169          value = (16 << 8) | 4;
1170    }
1171    screen->gpc_count = value & 0x000000ff;
1172    screen->mp_count = value >> 8;
1173    screen->mp_count_compute = screen->mp_count;
1174
1175    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1176    if (ret)
1177       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1178
1179    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1180    PUSH_DATAh(push, screen->tls->offset);
1181    PUSH_DATA (push, screen->tls->offset);
1182    PUSH_DATA (push, screen->tls->size >> 32);
1183    PUSH_DATA (push, screen->tls->size);
1184    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1185    PUSH_DATA (push, 0);
1186    /* Reduce likelihood of collision with real buffers by placing the hole at
1187     * the top of the 4G area. This will have to be dealt with for real
1188     * eventually by blocking off that area from the VM.
1189     */
1190    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1191    PUSH_DATA (push, 0xff << 24);
1192
1193    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1194       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1195                            &screen->poly_cache);
1196       if (ret)
1197          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1198
1199       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1200       PUSH_DATAh(push, screen->poly_cache->offset);
1201       PUSH_DATA (push, screen->poly_cache->offset);
1202       PUSH_DATA (push, 3);
1203    }
1204
1205    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1206                         &screen->txc);
1207    if (ret)
1208       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1209
1210    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1211    PUSH_DATAh(push, screen->txc->offset);
1212    PUSH_DATA (push, screen->txc->offset);
1213    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1214    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1215       screen->tic.maxwell = true;
1216       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1217          screen->tic.maxwell =
1218             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1219          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1220       }
1221    }
1222
1223    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1224    PUSH_DATAh(push, screen->txc->offset + 65536);
1225    PUSH_DATA (push, screen->txc->offset + 65536);
1226    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1227
1228    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1229    PUSH_DATA (push, 0);
1230    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1231    PUSH_DATA (push, 0);
1232    PUSH_DATA (push, 0);
1233    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1234    PUSH_DATA (push, 0x3f);
1235
1236    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1237    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1238    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1239    for (i = 0; i < 8 * 2; ++i)
1240       PUSH_DATA(push, 0);
1241    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1242    PUSH_DATA (push, 0);
1243    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1244    PUSH_DATA (push, 0);
1245
1246    /* neither scissors, viewport nor stencil mask should affect clears */
1247    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1248    PUSH_DATA (push, 0);
1249
1250    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1251    PUSH_DATA (push, 1);
1252    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1253       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1254       PUSH_DATAf(push, 0.0f);
1255       PUSH_DATAf(push, 1.0f);
1256    }
1257    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1258    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1259
1260    /* We use scissors instead of exact view volume clipping,
1261     * so they're always enabled.
1262     */
1263    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1264       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1265       PUSH_DATA (push, 1);
1266       PUSH_DATA (push, 8192 << 16);
1267       PUSH_DATA (push, 8192 << 16);
1268    }
1269
1270 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1271
1272    i = 0;
1273    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1274    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1275    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1276    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1277    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1278    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1279    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1280    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1281    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1282    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1283    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1284    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1285    MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1286    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1287
1288    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1289    PUSH_DATA (push, 1);
1290    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1291    PUSH_DATA (push, 1);
1292    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1293    PUSH_DATA (push, 0x40);
1294    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1295    PUSH_DATA (push, 0);
1296    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1297    PUSH_DATA (push, 0x30);
1298    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1299    PUSH_DATA (push, 3);
1300    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1301    PUSH_DATA (push, 0x20);
1302    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1303    PUSH_DATA (push, 0x00);
1304    screen->save_state.patch_vertices = 3;
1305
1306    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1307    PUSH_DATA (push, 0);
1308    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1309    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1310
1311    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1312
1313    if (nvc0_screen_init_compute(screen))
1314       goto fail;
1315
1316    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1317    for (i = 0; i < 5; ++i) {
1318       unsigned j = 0;
1319       for (j = 0; j < 16; j++)
1320          screen->cb_bindings[i][j].size = -1;
1321
1322       /* TIC and TSC entries for each unit (nve4+ only) */
1323       /* auxiliary constants (6 user clip planes, base instance id) */
1324       nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1325                              screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1326       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1327          unsigned j;
1328          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1329          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1330          for (j = 0; j < 8; ++j)
1331             PUSH_DATA(push, j);
1332       } else {
1333          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1334          PUSH_DATA (push, 0x54);
1335       }
1336
1337       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1338       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1339       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1340       PUSH_DATA (push, 0); /* 0 */
1341       PUSH_DATA (push, 0);
1342       PUSH_DATA (push, 1); /* 1 */
1343       PUSH_DATA (push, 0);
1344       PUSH_DATA (push, 0); /* 2 */
1345       PUSH_DATA (push, 1);
1346       PUSH_DATA (push, 1); /* 3 */
1347       PUSH_DATA (push, 1);
1348       PUSH_DATA (push, 2); /* 4 */
1349       PUSH_DATA (push, 0);
1350       PUSH_DATA (push, 3); /* 5 */
1351       PUSH_DATA (push, 0);
1352       PUSH_DATA (push, 2); /* 6 */
1353       PUSH_DATA (push, 1);
1354       PUSH_DATA (push, 3); /* 7 */
1355       PUSH_DATA (push, 1);
1356    }
1357    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1358    PUSH_DATA (push, 0);
1359
1360    PUSH_KICK (push);
1361
1362    screen->tic.entries = CALLOC(
1363          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1364          sizeof(void *));
1365    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1366    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1367
1368    if (!nvc0_blitter_create(screen))
1369       goto fail;
1370
1371    screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1372    screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1373
1374    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1375
1376    return &screen->base;
1377
1378 fail:
1379    screen->base.base.context_create = NULL;
1380    return &screen->base;
1381 }
1382
1383 int
1384 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1385 {
1386    int i = screen->tic.next;
1387
1388    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1389       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1390
1391    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1392
1393    if (screen->tic.entries[i])
1394       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1395
1396    screen->tic.entries[i] = entry;
1397    return i;
1398 }
1399
1400 int
1401 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1402 {
1403    int i = screen->tsc.next;
1404
1405    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1406       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1407
1408    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1409
1410    if (screen->tsc.entries[i])
1411       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1412
1413    screen->tsc.entries[i] = entry;
1414    return i;
1415 }