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gallium: add cap for driver specified max combined shader resources.
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/mme/com9097.mme.h"
36 #include "nvc0/mme/com90c0.mme.h"
37
38 #include "nv50/g80_texture.xml.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 const struct util_format_description *desc = util_format_description(format);
48
49 if (sample_count > 8)
50 return false;
51 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
52 return false;
53
54 /* Short-circuit the rest of the logic -- this is used by the state tracker
55 * to determine valid MS levels in a no-attachments scenario.
56 */
57 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
58 return true;
59
60 if (!util_format_is_supported(format, bindings))
61 return false;
62
63 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
64 if (util_format_get_blocksizebits(format) == 3 * 32)
65 return false;
66
67 if (bindings & PIPE_BIND_LINEAR)
68 if (util_format_is_depth_or_stencil(format) ||
69 (target != PIPE_TEXTURE_1D &&
70 target != PIPE_TEXTURE_2D &&
71 target != PIPE_TEXTURE_RECT) ||
72 sample_count > 1)
73 return false;
74
75 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
76 */
77 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
78 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
79 /* The claim is that this should work on GM107 but it doesn't. Need to
80 * test further and figure out if it's a nouveau issue or a HW one.
81 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
82 */
83 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
84 return false;
85
86 /* shared is always supported */
87 bindings &= ~(PIPE_BIND_LINEAR |
88 PIPE_BIND_SHARED);
89
90 if (bindings & PIPE_BIND_SHADER_IMAGE) {
91 if (sample_count > 1 &&
92 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
93 /* MS images are currently unsupported on Maxwell because they have to
94 * be handled explicitly. */
95 return false;
96 }
97
98 if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
99 nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
100 /* This should work on Fermi, but for currently unknown reasons it
101 * does not and results in breaking reads from pbos. */
102 return false;
103 }
104 }
105
106 return (( nvc0_format_table[format].usage |
107 nvc0_vertex_format[format].usage) & bindings) == bindings;
108 }
109
110 static int
111 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
112 {
113 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
114 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
115
116 switch (param) {
117 /* non-boolean caps */
118 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
119 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
120 return 15;
121 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
122 return 12;
123 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
124 return 2048;
125 case PIPE_CAP_MIN_TEXEL_OFFSET:
126 return -8;
127 case PIPE_CAP_MAX_TEXEL_OFFSET:
128 return 7;
129 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
130 return -32;
131 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
132 return 31;
133 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
134 return 128 * 1024 * 1024;
135 case PIPE_CAP_GLSL_FEATURE_LEVEL:
136 return 430;
137 case PIPE_CAP_MAX_RENDER_TARGETS:
138 return 8;
139 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
140 return 1;
141 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
142 return 4;
143 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
144 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
145 return 128;
146 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
147 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
148 return 1024;
149 case PIPE_CAP_MAX_VERTEX_STREAMS:
150 return 4;
151 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
152 return 2048;
153 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
154 return 256;
155 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
156 if (class_3d < GM107_3D_CLASS)
157 return 256; /* IMAGE bindings require alignment to 256 */
158 return 16;
159 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
160 return 16;
161 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
162 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
163 case PIPE_CAP_MAX_VIEWPORTS:
164 return NVC0_MAX_VIEWPORTS;
165 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
166 return 4;
167 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
168 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
169 case PIPE_CAP_ENDIANNESS:
170 return PIPE_ENDIAN_LITTLE;
171 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
172 return 30;
173 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
174 return NVC0_MAX_WINDOW_RECTANGLES;
175
176 /* supported caps */
177 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
178 case PIPE_CAP_TEXTURE_SWIZZLE:
179 case PIPE_CAP_TEXTURE_SHADOW_MAP:
180 case PIPE_CAP_NPOT_TEXTURES:
181 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
182 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
183 case PIPE_CAP_ANISOTROPIC_FILTER:
184 case PIPE_CAP_SEAMLESS_CUBE_MAP:
185 case PIPE_CAP_CUBE_MAP_ARRAY:
186 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
187 case PIPE_CAP_TEXTURE_MULTISAMPLE:
188 case PIPE_CAP_TWO_SIDED_STENCIL:
189 case PIPE_CAP_DEPTH_CLIP_DISABLE:
190 case PIPE_CAP_POINT_SPRITE:
191 case PIPE_CAP_TGSI_TEXCOORD:
192 case PIPE_CAP_SM3:
193 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
194 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
195 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
196 case PIPE_CAP_QUERY_TIMESTAMP:
197 case PIPE_CAP_QUERY_TIME_ELAPSED:
198 case PIPE_CAP_OCCLUSION_QUERY:
199 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
200 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
201 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
202 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
203 case PIPE_CAP_INDEP_BLEND_ENABLE:
204 case PIPE_CAP_INDEP_BLEND_FUNC:
205 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
206 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
207 case PIPE_CAP_PRIMITIVE_RESTART:
208 case PIPE_CAP_TGSI_INSTANCEID:
209 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
210 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
211 case PIPE_CAP_CONDITIONAL_RENDER:
212 case PIPE_CAP_TEXTURE_BARRIER:
213 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
214 case PIPE_CAP_START_INSTANCE:
215 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
216 case PIPE_CAP_DRAW_INDIRECT:
217 case PIPE_CAP_USER_CONSTANT_BUFFERS:
218 case PIPE_CAP_USER_VERTEX_BUFFERS:
219 case PIPE_CAP_TEXTURE_QUERY_LOD:
220 case PIPE_CAP_SAMPLE_SHADING:
221 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
222 case PIPE_CAP_TEXTURE_GATHER_SM5:
223 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
224 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
225 case PIPE_CAP_SAMPLER_VIEW_TARGET:
226 case PIPE_CAP_CLIP_HALFZ:
227 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
228 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
229 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
230 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
231 case PIPE_CAP_DEPTH_BOUNDS_TEST:
232 case PIPE_CAP_TGSI_TXQS:
233 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
234 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
235 case PIPE_CAP_SHAREABLE_SHADERS:
236 case PIPE_CAP_CLEAR_TEXTURE:
237 case PIPE_CAP_DRAW_PARAMETERS:
238 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
239 case PIPE_CAP_MULTI_DRAW_INDIRECT:
240 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
241 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
242 case PIPE_CAP_QUERY_BUFFER_OBJECT:
243 case PIPE_CAP_INVALIDATE_BUFFER:
244 case PIPE_CAP_STRING_MARKER:
245 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
246 case PIPE_CAP_CULL_DISTANCE:
247 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
248 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
249 case PIPE_CAP_TGSI_VOTE:
250 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
251 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
252 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
253 case PIPE_CAP_DOUBLES:
254 case PIPE_CAP_INT64:
255 case PIPE_CAP_TGSI_TEX_TXF_LZ:
256 case PIPE_CAP_TGSI_CLOCK:
257 case PIPE_CAP_COMPUTE:
258 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
259 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
260 return 1;
261 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
262 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
263 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
264 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
265 case PIPE_CAP_TGSI_FS_FBFETCH:
266 return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
267 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
268 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
269 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
270 case PIPE_CAP_POST_DEPTH_COVERAGE:
271 return class_3d >= GM200_3D_CLASS;
272 case PIPE_CAP_TGSI_BALLOT:
273 return class_3d >= NVE4_3D_CLASS;
274
275 /* unsupported caps */
276 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
277 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
278 case PIPE_CAP_SHADER_STENCIL_EXPORT:
279 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
280 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
281 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
282 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
283 case PIPE_CAP_FAKE_SW_MSAA:
284 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
285 case PIPE_CAP_VERTEXID_NOBASE:
286 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
287 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
288 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
289 case PIPE_CAP_GENERATE_MIPMAP:
290 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
291 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
292 case PIPE_CAP_QUERY_MEMORY_INFO:
293 case PIPE_CAP_PCI_GROUP:
294 case PIPE_CAP_PCI_BUS:
295 case PIPE_CAP_PCI_DEVICE:
296 case PIPE_CAP_PCI_FUNCTION:
297 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
298 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
299 case PIPE_CAP_NATIVE_FENCE_FD:
300 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
301 case PIPE_CAP_INT64_DIVMOD:
302 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
303 case PIPE_CAP_BINDLESS_TEXTURE:
304 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
305 case PIPE_CAP_QUERY_SO_OVERFLOW:
306 case PIPE_CAP_MEMOBJ:
307 case PIPE_CAP_LOAD_CONSTBUF:
308 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
309 case PIPE_CAP_TILE_RASTER_ORDER:
310 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
311 return 0;
312
313 case PIPE_CAP_VENDOR_ID:
314 return 0x10de;
315 case PIPE_CAP_DEVICE_ID: {
316 uint64_t device_id;
317 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
318 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
319 return -1;
320 }
321 return device_id;
322 }
323 case PIPE_CAP_ACCELERATED:
324 return 1;
325 case PIPE_CAP_VIDEO_MEMORY:
326 return dev->vram_size >> 20;
327 case PIPE_CAP_UMA:
328 return 0;
329 }
330
331 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
332 return 0;
333 }
334
335 static int
336 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
337 enum pipe_shader_type shader,
338 enum pipe_shader_cap param)
339 {
340 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
341
342 switch (shader) {
343 case PIPE_SHADER_VERTEX:
344 case PIPE_SHADER_GEOMETRY:
345 case PIPE_SHADER_FRAGMENT:
346 case PIPE_SHADER_COMPUTE:
347 case PIPE_SHADER_TESS_CTRL:
348 case PIPE_SHADER_TESS_EVAL:
349 break;
350 default:
351 return 0;
352 }
353
354 switch (param) {
355 case PIPE_SHADER_CAP_PREFERRED_IR:
356 return PIPE_SHADER_IR_TGSI;
357 case PIPE_SHADER_CAP_SUPPORTED_IRS:
358 return 1 << PIPE_SHADER_IR_TGSI;
359 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
360 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
361 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
362 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
363 return 16384;
364 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
365 return 16;
366 case PIPE_SHADER_CAP_MAX_INPUTS:
367 if (shader == PIPE_SHADER_VERTEX)
368 return 32;
369 /* NOTE: These only count our slots for GENERIC varyings.
370 * The address space may be larger, but the actual hard limit seems to be
371 * less than what the address space layout permits, so don't add TEXCOORD,
372 * COLOR, etc. here.
373 */
374 if (shader == PIPE_SHADER_FRAGMENT)
375 return 0x1f0 / 16;
376 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
377 * and excludes 0x60 per-patch inputs.
378 */
379 return 0x200 / 16;
380 case PIPE_SHADER_CAP_MAX_OUTPUTS:
381 return 32;
382 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
383 return 65536;
384 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
385 return NVC0_MAX_PIPE_CONSTBUFS;
386 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
387 return shader != PIPE_SHADER_FRAGMENT;
388 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
389 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
390 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
391 return 1;
392 case PIPE_SHADER_CAP_MAX_TEMPS:
393 return NVC0_CAP_MAX_PROGRAM_TEMPS;
394 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
395 return 1;
396 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
397 return 1;
398 case PIPE_SHADER_CAP_SUBROUTINES:
399 return 1;
400 case PIPE_SHADER_CAP_INTEGERS:
401 return 1;
402 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
403 return 1;
404 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
405 return 1;
406 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
407 return 1;
408 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
409 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
410 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
411 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
412 case PIPE_SHADER_CAP_INT64_ATOMICS:
413 case PIPE_SHADER_CAP_FP16:
414 return 0;
415 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
416 return NVC0_MAX_BUFFERS;
417 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
418 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
419 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
420 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
421 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
422 return 32;
423 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
424 if (class_3d >= NVE4_3D_CLASS)
425 return NVC0_MAX_IMAGES;
426 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
427 return NVC0_MAX_IMAGES;
428 return 0;
429 default:
430 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
431 return 0;
432 }
433 }
434
435 static float
436 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
437 {
438 switch (param) {
439 case PIPE_CAPF_MAX_LINE_WIDTH:
440 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
441 return 10.0f;
442 case PIPE_CAPF_MAX_POINT_WIDTH:
443 return 63.0f;
444 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
445 return 63.375f;
446 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
447 return 16.0f;
448 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
449 return 15.0f;
450 case PIPE_CAPF_GUARD_BAND_LEFT:
451 case PIPE_CAPF_GUARD_BAND_TOP:
452 return 0.0f;
453 case PIPE_CAPF_GUARD_BAND_RIGHT:
454 case PIPE_CAPF_GUARD_BAND_BOTTOM:
455 return 0.0f; /* that or infinity */
456 }
457
458 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
459 return 0.0f;
460 }
461
462 static int
463 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
464 enum pipe_shader_ir ir_type,
465 enum pipe_compute_cap param, void *data)
466 {
467 struct nvc0_screen *screen = nvc0_screen(pscreen);
468 const uint16_t obj_class = screen->compute->oclass;
469
470 #define RET(x) do { \
471 if (data) \
472 memcpy(data, x, sizeof(x)); \
473 return sizeof(x); \
474 } while (0)
475
476 switch (param) {
477 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
478 RET((uint64_t []) { 3 });
479 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
480 if (obj_class >= NVE4_COMPUTE_CLASS) {
481 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
482 } else {
483 RET(((uint64_t []) { 65535, 65535, 65535 }));
484 }
485 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
486 RET(((uint64_t []) { 1024, 1024, 64 }));
487 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
488 RET((uint64_t []) { 1024 });
489 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
490 if (obj_class >= NVE4_COMPUTE_CLASS) {
491 RET((uint64_t []) { 1024 });
492 } else {
493 RET((uint64_t []) { 512 });
494 }
495 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
496 RET((uint64_t []) { 1ULL << 40 });
497 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
498 switch (obj_class) {
499 case GM200_COMPUTE_CLASS:
500 RET((uint64_t []) { 96 << 10 });
501 break;
502 case GM107_COMPUTE_CLASS:
503 RET((uint64_t []) { 64 << 10 });
504 break;
505 default:
506 RET((uint64_t []) { 48 << 10 });
507 break;
508 }
509 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
510 RET((uint64_t []) { 512 << 10 });
511 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
512 RET((uint64_t []) { 4096 });
513 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
514 RET((uint32_t []) { 32 });
515 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
516 RET((uint64_t []) { 1ULL << 40 });
517 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
518 RET((uint32_t []) { 0 });
519 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
520 RET((uint32_t []) { screen->mp_count_compute });
521 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
522 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
523 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
524 RET((uint32_t []) { 64 });
525 default:
526 return 0;
527 }
528
529 #undef RET
530 }
531
532 static void
533 nvc0_screen_destroy(struct pipe_screen *pscreen)
534 {
535 struct nvc0_screen *screen = nvc0_screen(pscreen);
536
537 if (!nouveau_drm_screen_unref(&screen->base))
538 return;
539
540 if (screen->base.fence.current) {
541 struct nouveau_fence *current = NULL;
542
543 /* nouveau_fence_wait will create a new current fence, so wait on the
544 * _current_ one, and remove both.
545 */
546 nouveau_fence_ref(screen->base.fence.current, &current);
547 nouveau_fence_wait(current, NULL);
548 nouveau_fence_ref(NULL, &current);
549 nouveau_fence_ref(NULL, &screen->base.fence.current);
550 }
551 if (screen->base.pushbuf)
552 screen->base.pushbuf->user_priv = NULL;
553
554 if (screen->blitter)
555 nvc0_blitter_destroy(screen);
556 if (screen->pm.prog) {
557 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
558 nvc0_program_destroy(NULL, screen->pm.prog);
559 FREE(screen->pm.prog);
560 }
561
562 nouveau_bo_ref(NULL, &screen->text);
563 nouveau_bo_ref(NULL, &screen->uniform_bo);
564 nouveau_bo_ref(NULL, &screen->tls);
565 nouveau_bo_ref(NULL, &screen->txc);
566 nouveau_bo_ref(NULL, &screen->fence.bo);
567 nouveau_bo_ref(NULL, &screen->poly_cache);
568
569 nouveau_heap_destroy(&screen->lib_code);
570 nouveau_heap_destroy(&screen->text_heap);
571
572 FREE(screen->default_tsc);
573 FREE(screen->tic.entries);
574
575 nouveau_object_del(&screen->eng3d);
576 nouveau_object_del(&screen->eng2d);
577 nouveau_object_del(&screen->m2mf);
578 nouveau_object_del(&screen->compute);
579 nouveau_object_del(&screen->nvsw);
580
581 nouveau_screen_fini(&screen->base);
582
583 FREE(screen);
584 }
585
586 static int
587 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
588 unsigned size, const uint32_t *data)
589 {
590 struct nouveau_pushbuf *push = screen->base.pushbuf;
591
592 size /= 4;
593
594 assert((pos + size) <= 0x800);
595
596 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
597 PUSH_DATA (push, (m - 0x3800) / 8);
598 PUSH_DATA (push, pos);
599 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
600 PUSH_DATA (push, pos);
601 PUSH_DATAp(push, data, size);
602
603 return pos + size;
604 }
605
606 static void
607 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
608 {
609 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
610 PUSH_DATA (push, 0xff);
611 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
612 PUSH_DATA (push, 0xff);
613 PUSH_DATA (push, 0xff);
614 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
615 PUSH_DATA (push, 0xff);
616 PUSH_DATA (push, 0xff);
617 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
618 PUSH_DATA (push, 0x3f);
619
620 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
621 PUSH_DATA (push, (3 << 16) | 3);
622 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
623 PUSH_DATA (push, (2 << 16) | 2);
624
625 if (obj_class < GM107_3D_CLASS) {
626 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
627 PUSH_DATA (push, 0);
628 }
629 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
630 PUSH_DATA (push, 0x10);
631 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
632 PUSH_DATA (push, 0x10);
633 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
634 PUSH_DATA (push, 0x10);
635 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
636 PUSH_DATA (push, 0x10);
637 PUSH_DATA (push, 0x10);
638 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
639 PUSH_DATA (push, 0x10);
640 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
641 PUSH_DATA (push, 0xe);
642
643 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
644 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
645 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
646 PUSH_DATA (push, 0);
647 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
648 PUSH_DATA (push, 3);
649
650 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
651 PUSH_DATA (push, 0x3fffff);
652 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
653 PUSH_DATA (push, 1);
654 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
655 PUSH_DATA (push, 1);
656
657 if (obj_class < GM107_3D_CLASS) {
658 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
659 PUSH_DATA (push, 3);
660
661 if (obj_class >= NVE4_3D_CLASS) {
662 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
663 PUSH_DATA (push, 1);
664 }
665 }
666
667 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
668 * are supposed to do */
669 }
670
671 static void
672 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
673 {
674 struct nvc0_screen *screen = nvc0_screen(pscreen);
675 struct nouveau_pushbuf *push = screen->base.pushbuf;
676
677 /* we need to do it after possible flush in MARK_RING */
678 *sequence = ++screen->base.fence.sequence;
679
680 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
681 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
682 PUSH_DATAh(push, screen->fence.bo->offset);
683 PUSH_DATA (push, screen->fence.bo->offset);
684 PUSH_DATA (push, *sequence);
685 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
686 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
687 }
688
689 static u32
690 nvc0_screen_fence_update(struct pipe_screen *pscreen)
691 {
692 struct nvc0_screen *screen = nvc0_screen(pscreen);
693 return screen->fence.map[0];
694 }
695
696 static int
697 nvc0_screen_init_compute(struct nvc0_screen *screen)
698 {
699 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
700
701 switch (screen->base.device->chipset & ~0xf) {
702 case 0xc0:
703 case 0xd0:
704 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
705 case 0xe0:
706 case 0xf0:
707 case 0x100:
708 case 0x110:
709 case 0x120:
710 case 0x130:
711 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
712 default:
713 return -1;
714 }
715 }
716
717 static int
718 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
719 uint32_t lpos, uint32_t lneg, uint32_t cstack)
720 {
721 struct nouveau_bo *bo = NULL;
722 int ret;
723 uint64_t size = (lpos + lneg) * 32 + cstack;
724
725 if (size >= (1 << 20)) {
726 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
727 return -1;
728 }
729
730 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
731 size = align(size, 0x8000);
732 size *= screen->mp_count;
733
734 size = align(size, 1 << 17);
735
736 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
737 NULL, &bo);
738 if (ret)
739 return ret;
740 nouveau_bo_ref(NULL, &screen->tls);
741 screen->tls = bo;
742 return 0;
743 }
744
745 int
746 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
747 {
748 struct nouveau_pushbuf *push = screen->base.pushbuf;
749 struct nouveau_bo *bo;
750 int ret;
751
752 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
753 1 << 17, size, NULL, &bo);
754 if (ret)
755 return ret;
756
757 nouveau_bo_ref(NULL, &screen->text);
758 screen->text = bo;
759
760 nouveau_heap_destroy(&screen->lib_code);
761 nouveau_heap_destroy(&screen->text_heap);
762
763 /* XXX: getting a page fault at the end of the code buffer every few
764 * launches, don't use the last 256 bytes to work around them - prefetch ?
765 */
766 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
767
768 /* update the code segment setup */
769 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
770 PUSH_DATAh(push, screen->text->offset);
771 PUSH_DATA (push, screen->text->offset);
772 if (screen->compute) {
773 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
774 PUSH_DATAh(push, screen->text->offset);
775 PUSH_DATA (push, screen->text->offset);
776 }
777
778 return 0;
779 }
780
781 #define FAIL_SCREEN_INIT(str, err) \
782 do { \
783 NOUVEAU_ERR(str, err); \
784 goto fail; \
785 } while(0)
786
787 struct nouveau_screen *
788 nvc0_screen_create(struct nouveau_device *dev)
789 {
790 struct nvc0_screen *screen;
791 struct pipe_screen *pscreen;
792 struct nouveau_object *chan;
793 struct nouveau_pushbuf *push;
794 uint64_t value;
795 uint32_t obj_class;
796 uint32_t flags;
797 int ret;
798 unsigned i;
799
800 switch (dev->chipset & ~0xf) {
801 case 0xc0:
802 case 0xd0:
803 case 0xe0:
804 case 0xf0:
805 case 0x100:
806 case 0x110:
807 case 0x120:
808 case 0x130:
809 break;
810 default:
811 return NULL;
812 }
813
814 screen = CALLOC_STRUCT(nvc0_screen);
815 if (!screen)
816 return NULL;
817 pscreen = &screen->base.base;
818 pscreen->destroy = nvc0_screen_destroy;
819
820 ret = nouveau_screen_init(&screen->base, dev);
821 if (ret)
822 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
823 chan = screen->base.channel;
824 push = screen->base.pushbuf;
825 push->user_priv = screen;
826 push->rsvd_kick = 5;
827
828 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
829 PIPE_BIND_SHADER_BUFFER |
830 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
831 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
832 screen->base.sysmem_bindings |=
833 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
834
835 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
836 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
837 screen->base.vidmem_bindings = 0;
838 }
839
840 pscreen->context_create = nvc0_create;
841 pscreen->is_format_supported = nvc0_screen_is_format_supported;
842 pscreen->get_param = nvc0_screen_get_param;
843 pscreen->get_shader_param = nvc0_screen_get_shader_param;
844 pscreen->get_paramf = nvc0_screen_get_paramf;
845 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
846 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
847
848 nvc0_screen_init_resource_functions(pscreen);
849
850 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
851 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
852
853 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
854 if (screen->base.drm->version >= 0x01000202)
855 flags |= NOUVEAU_BO_COHERENT;
856
857 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
858 if (ret)
859 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
860 nouveau_bo_map(screen->fence.bo, 0, NULL);
861 screen->fence.map = screen->fence.bo->map;
862 screen->base.fence.emit = nvc0_screen_fence_emit;
863 screen->base.fence.update = nvc0_screen_fence_update;
864
865
866 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
867 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
868 if (ret)
869 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
870
871 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
872 PUSH_DATA (push, screen->nvsw->handle);
873
874 switch (dev->chipset & ~0xf) {
875 case 0x130:
876 case 0x120:
877 case 0x110:
878 case 0x100:
879 case 0xf0:
880 obj_class = NVF0_P2MF_CLASS;
881 break;
882 case 0xe0:
883 obj_class = NVE4_P2MF_CLASS;
884 break;
885 default:
886 obj_class = NVC0_M2MF_CLASS;
887 break;
888 }
889 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
890 &screen->m2mf);
891 if (ret)
892 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
893
894 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
895 PUSH_DATA (push, screen->m2mf->oclass);
896 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
897 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
898 PUSH_DATA (push, 0xa0b5);
899 }
900
901 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
902 &screen->eng2d);
903 if (ret)
904 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
905
906 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
907 PUSH_DATA (push, screen->eng2d->oclass);
908 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
909 PUSH_DATA (push, 0);
910 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
911 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
912 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
913 PUSH_DATA (push, 0);
914 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
915 PUSH_DATA (push, 0);
916 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
917 PUSH_DATA (push, 0x3f);
918 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
919 PUSH_DATA (push, 1);
920 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
921 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
922
923 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
924 PUSH_DATAh(push, screen->fence.bo->offset + 16);
925 PUSH_DATA (push, screen->fence.bo->offset + 16);
926
927 switch (dev->chipset & ~0xf) {
928 case 0x130:
929 switch (dev->chipset) {
930 case 0x130:
931 case 0x13b:
932 obj_class = GP100_3D_CLASS;
933 break;
934 default:
935 obj_class = GP102_3D_CLASS;
936 break;
937 }
938 break;
939 case 0x120:
940 obj_class = GM200_3D_CLASS;
941 break;
942 case 0x110:
943 obj_class = GM107_3D_CLASS;
944 break;
945 case 0x100:
946 case 0xf0:
947 obj_class = NVF0_3D_CLASS;
948 break;
949 case 0xe0:
950 switch (dev->chipset) {
951 case 0xea:
952 obj_class = NVEA_3D_CLASS;
953 break;
954 default:
955 obj_class = NVE4_3D_CLASS;
956 break;
957 }
958 break;
959 case 0xd0:
960 obj_class = NVC8_3D_CLASS;
961 break;
962 case 0xc0:
963 default:
964 switch (dev->chipset) {
965 case 0xc8:
966 obj_class = NVC8_3D_CLASS;
967 break;
968 case 0xc1:
969 obj_class = NVC1_3D_CLASS;
970 break;
971 default:
972 obj_class = NVC0_3D_CLASS;
973 break;
974 }
975 break;
976 }
977 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
978 &screen->eng3d);
979 if (ret)
980 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
981 screen->base.class_3d = obj_class;
982
983 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
984 PUSH_DATA (push, screen->eng3d->oclass);
985
986 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
987 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
988
989 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
990 /* kill shaders after about 1 second (at 100 MHz) */
991 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
992 PUSH_DATA (push, 0x17);
993 }
994
995 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
996 screen->base.drm->version >= 0x01000101);
997 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
998 for (i = 0; i < 8; ++i)
999 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1000
1001 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1002 PUSH_DATA (push, 1);
1003
1004 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1005 PUSH_DATA (push, 0);
1006 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1007 PUSH_DATA (push, 0);
1008 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1009 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1010 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1011 PUSH_DATA (push, 0);
1012 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1013 PUSH_DATA (push, 1);
1014 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1015 PUSH_DATA (push, 1);
1016 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1017 PUSH_DATA (push, 1);
1018 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1019 PUSH_DATA (push, 0);
1020 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1021 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1022 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1023 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1024 } else {
1025 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1026 PUSH_DATA (push, 15);
1027 }
1028 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1029 PUSH_DATA (push, 8); /* 128 */
1030 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1031 PUSH_DATA (push, 1);
1032 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1033 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1034 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1035 }
1036
1037 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1038
1039 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1040 if (ret)
1041 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1042
1043 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1044 &screen->uniform_bo);
1045 if (ret)
1046 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1047
1048 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1049
1050 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1051 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1052 PUSH_DATA (push, 256);
1053 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1054 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1055 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1056 PUSH_DATA (push, 0);
1057 PUSH_DATAf(push, 0.0f);
1058 PUSH_DATAf(push, 0.0f);
1059 PUSH_DATAf(push, 0.0f);
1060 PUSH_DATAf(push, 0.0f);
1061 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1062 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1063 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1064
1065 if (screen->base.drm->version >= 0x01000101) {
1066 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1067 if (ret)
1068 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1069 } else {
1070 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1071 value = (8 << 8) | 4;
1072 else
1073 value = (16 << 8) | 4;
1074 }
1075 screen->gpc_count = value & 0x000000ff;
1076 screen->mp_count = value >> 8;
1077 screen->mp_count_compute = screen->mp_count;
1078
1079 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1080 if (ret)
1081 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1082
1083 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1084 PUSH_DATAh(push, screen->tls->offset);
1085 PUSH_DATA (push, screen->tls->offset);
1086 PUSH_DATA (push, screen->tls->size >> 32);
1087 PUSH_DATA (push, screen->tls->size);
1088 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1089 PUSH_DATA (push, 0);
1090 /* Reduce likelihood of collision with real buffers by placing the hole at
1091 * the top of the 4G area. This will have to be dealt with for real
1092 * eventually by blocking off that area from the VM.
1093 */
1094 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1095 PUSH_DATA (push, 0xff << 24);
1096
1097 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1098 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1099 &screen->poly_cache);
1100 if (ret)
1101 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1102
1103 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1104 PUSH_DATAh(push, screen->poly_cache->offset);
1105 PUSH_DATA (push, screen->poly_cache->offset);
1106 PUSH_DATA (push, 3);
1107 }
1108
1109 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1110 &screen->txc);
1111 if (ret)
1112 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1113
1114 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1115 PUSH_DATAh(push, screen->txc->offset);
1116 PUSH_DATA (push, screen->txc->offset);
1117 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1118 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1119 screen->tic.maxwell = true;
1120 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1121 screen->tic.maxwell =
1122 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1123 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1124 }
1125 }
1126
1127 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1128 PUSH_DATAh(push, screen->txc->offset + 65536);
1129 PUSH_DATA (push, screen->txc->offset + 65536);
1130 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1131
1132 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1133 PUSH_DATA (push, 0);
1134 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1135 PUSH_DATA (push, 0);
1136 PUSH_DATA (push, 0);
1137 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1138 PUSH_DATA (push, 0x3f);
1139
1140 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1141 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1142 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1143 for (i = 0; i < 8 * 2; ++i)
1144 PUSH_DATA(push, 0);
1145 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1146 PUSH_DATA (push, 0);
1147 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1148 PUSH_DATA (push, 0);
1149
1150 /* neither scissors, viewport nor stencil mask should affect clears */
1151 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1152 PUSH_DATA (push, 0);
1153
1154 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1155 PUSH_DATA (push, 1);
1156 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1157 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1158 PUSH_DATAf(push, 0.0f);
1159 PUSH_DATAf(push, 1.0f);
1160 }
1161 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1162 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1163
1164 /* We use scissors instead of exact view volume clipping,
1165 * so they're always enabled.
1166 */
1167 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1168 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1169 PUSH_DATA (push, 1);
1170 PUSH_DATA (push, 8192 << 16);
1171 PUSH_DATA (push, 8192 << 16);
1172 }
1173
1174 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1175
1176 i = 0;
1177 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1178 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1179 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1180 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1181 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1182 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1183 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1184 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1185 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1186 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1187 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1188 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1189 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1190
1191 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1192 PUSH_DATA (push, 1);
1193 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1194 PUSH_DATA (push, 1);
1195 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1196 PUSH_DATA (push, 0x40);
1197 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1198 PUSH_DATA (push, 0);
1199 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1200 PUSH_DATA (push, 0x30);
1201 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1202 PUSH_DATA (push, 3);
1203 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1204 PUSH_DATA (push, 0x20);
1205 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1206 PUSH_DATA (push, 0x00);
1207 screen->save_state.patch_vertices = 3;
1208
1209 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1210 PUSH_DATA (push, 0);
1211 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1212 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1213
1214 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1215
1216 if (nvc0_screen_init_compute(screen))
1217 goto fail;
1218
1219 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1220 for (i = 0; i < 5; ++i) {
1221 /* TIC and TSC entries for each unit (nve4+ only) */
1222 /* auxiliary constants (6 user clip planes, base instance id) */
1223 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1224 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1225 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1226 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1227 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1228 PUSH_DATA (push, (15 << 4) | 1);
1229 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1230 unsigned j;
1231 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1232 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1233 for (j = 0; j < 8; ++j)
1234 PUSH_DATA(push, j);
1235 } else {
1236 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1237 PUSH_DATA (push, 0x54);
1238 }
1239
1240 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1241 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1242 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1243 PUSH_DATA (push, 0); /* 0 */
1244 PUSH_DATA (push, 0);
1245 PUSH_DATA (push, 1); /* 1 */
1246 PUSH_DATA (push, 0);
1247 PUSH_DATA (push, 0); /* 2 */
1248 PUSH_DATA (push, 1);
1249 PUSH_DATA (push, 1); /* 3 */
1250 PUSH_DATA (push, 1);
1251 PUSH_DATA (push, 2); /* 4 */
1252 PUSH_DATA (push, 0);
1253 PUSH_DATA (push, 3); /* 5 */
1254 PUSH_DATA (push, 0);
1255 PUSH_DATA (push, 2); /* 6 */
1256 PUSH_DATA (push, 1);
1257 PUSH_DATA (push, 3); /* 7 */
1258 PUSH_DATA (push, 1);
1259 }
1260 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1261 PUSH_DATA (push, 0);
1262
1263 PUSH_KICK (push);
1264
1265 screen->tic.entries = CALLOC(4096, sizeof(void *));
1266 screen->tsc.entries = screen->tic.entries + 2048;
1267
1268 if (!nvc0_blitter_create(screen))
1269 goto fail;
1270
1271 screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1272 screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1273
1274 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1275
1276 return &screen->base;
1277
1278 fail:
1279 screen->base.base.context_create = NULL;
1280 return &screen->base;
1281 }
1282
1283 int
1284 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1285 {
1286 int i = screen->tic.next;
1287
1288 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1289 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1290
1291 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1292
1293 if (screen->tic.entries[i])
1294 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1295
1296 screen->tic.entries[i] = entry;
1297 return i;
1298 }
1299
1300 int
1301 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1302 {
1303 int i = screen->tsc.next;
1304
1305 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1306 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1307
1308 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1309
1310 if (screen->tsc.entries[i])
1311 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1312
1313 screen->tsc.entries[i] = entry;
1314 return i;
1315 }