src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/nvc0_graph_macros.h"
  36
  37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  39 #endif
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    if (sample_count > 8)
  49       return FALSE;
  50    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  51       return FALSE;
  52
  53    if (!util_format_is_supported(format, bindings))
  54       return FALSE;
  55
  56    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  57       if (util_format_get_blocksizebits(format) == 3 * 32)
  58          return FALSE;
  59
  60    /* transfers & shared are always supported */
  61    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  62                  PIPE_BIND_TRANSFER_WRITE |
  63                  PIPE_BIND_SHARED);
  64
  65    return (nvc0_format_table[format].usage & bindings) == bindings;
  66 }
  67
  68 static int
  69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  70 {
  71    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  72
  73    switch (param) {
  74    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  75    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  76       return 15;
  77    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  78       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  79    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  80       return 2048;
  81    case PIPE_CAP_MIN_TEXEL_OFFSET:
  82       return -8;
  83    case PIPE_CAP_MAX_TEXEL_OFFSET:
  84       return 7;
  85    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  86    case PIPE_CAP_TEXTURE_SWIZZLE:
  87    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  88    case PIPE_CAP_NPOT_TEXTURES:
  89    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  90    case PIPE_CAP_ANISOTROPIC_FILTER:
  91    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  92    case PIPE_CAP_CUBE_MAP_ARRAY:
  93    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  94    case PIPE_CAP_TEXTURE_MULTISAMPLE:
  95       return 1;
  96    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  97       return 65536;
  98    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  99       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 100    case PIPE_CAP_TWO_SIDED_STENCIL:
 101    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 102    case PIPE_CAP_POINT_SPRITE:
 103    case PIPE_CAP_TGSI_TEXCOORD:
 104       return 1;
 105    case PIPE_CAP_SM3:
 106       return 1;
 107    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 108       return 330;
 109    case PIPE_CAP_MAX_RENDER_TARGETS:
 110       return 8;
 111    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 112       return 1;
 113    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 114    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 115    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 116       return 1;
 117    case PIPE_CAP_QUERY_TIMESTAMP:
 118    case PIPE_CAP_QUERY_TIME_ELAPSED:
 119    case PIPE_CAP_OCCLUSION_QUERY:
 120    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 121    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 122       return 1;
 123    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 124       return 4;
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127       return 128;
 128    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 129    case PIPE_CAP_INDEP_BLEND_ENABLE:
 130    case PIPE_CAP_INDEP_BLEND_FUNC:
 131       return 1;
 132    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 133    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 134       return 1;
 135    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 136    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 137       return 0;
 138    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 139       return 0;
 140    case PIPE_CAP_PRIMITIVE_RESTART:
 141    case PIPE_CAP_TGSI_INSTANCEID:
 142    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 143    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 144    case PIPE_CAP_CONDITIONAL_RENDER:
 145    case PIPE_CAP_TEXTURE_BARRIER:
 146    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 147    case PIPE_CAP_START_INSTANCE:
 148       return 1;
 149    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 150       return 0; /* state trackers will know better */
 151    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 152    case PIPE_CAP_USER_INDEX_BUFFERS:
 153    case PIPE_CAP_USER_VERTEX_BUFFERS:
 154       return 1;
 155    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 156       return 256;
 157    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 158       return 1; /* 256 for binding as RT, but that's not possible in GL */
 159    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 160       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 161    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 162    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 163    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 164       return 0;
 165    case PIPE_CAP_COMPUTE:
 166       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 167    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 168       return 1;
 169    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 170       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 171    case PIPE_CAP_ENDIANNESS:
 172       return PIPE_ENDIAN_LITTLE;
 173    case PIPE_CAP_TGSI_VS_LAYER:
 174       return 0;
 175    default:
 176       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 177       return 0;
 178    }
 179 }
 180
 181 static int
 182 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 183                              enum pipe_shader_cap param)
 184 {
 185    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 186
 187    switch (shader) {
 188    case PIPE_SHADER_VERTEX:
 189       /*
 190    case PIPE_SHADER_TESSELLATION_CONTROL:
 191    case PIPE_SHADER_TESSELLATION_EVALUATION:
 192       */
 193    case PIPE_SHADER_GEOMETRY:
 194    case PIPE_SHADER_FRAGMENT:
 195       break;
 196    case PIPE_SHADER_COMPUTE:
 197       if (class_3d < NVE4_3D_CLASS)
 198          return 0;
 199       break;
 200    default:
 201       return 0;
 202    }
 203
 204    switch (param) {
 205    case PIPE_SHADER_CAP_PREFERRED_IR:
 206       return PIPE_SHADER_IR_TGSI;
 207    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 208    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 209    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 210    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 211       return 16384;
 212    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 213       return 16;
 214    case PIPE_SHADER_CAP_MAX_INPUTS:
 215       if (shader == PIPE_SHADER_VERTEX)
 216          return 32;
 217       /* NOTE: These only count our slots for GENERIC varyings.
 218        * The address space may be larger, but the actual hard limit seems to be
 219        * less than what the address space layout permits, so don't add TEXCOORD,
 220        * COLOR, etc. here.
 221        */
 222       if (shader == PIPE_SHADER_FRAGMENT)
 223          return 0x1f0 / 16;
 224       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 225        * and excludes 0x60 per-patch inputs.
 226        */
 227       return 0x200 / 16;
 228    case PIPE_SHADER_CAP_MAX_CONSTS:
 229       return 65536 / 16;
 230    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 231       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 232          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 233       return NVC0_MAX_PIPE_CONSTBUFS;
 234    case PIPE_SHADER_CAP_MAX_ADDRS:
 235       return 1;
 236    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 237    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 238       return shader != PIPE_SHADER_FRAGMENT;
 239    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 240    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 241       return 1;
 242    case PIPE_SHADER_CAP_MAX_PREDS:
 243       return 0;
 244    case PIPE_SHADER_CAP_MAX_TEMPS:
 245       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 246    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 247       return 1;
 248    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 249       return 0;
 250    case PIPE_SHADER_CAP_SUBROUTINES:
 251       return 1;
 252    case PIPE_SHADER_CAP_INTEGERS:
 253       return 1;
 254    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 255       return 16; /* would be 32 in linked (OpenGL-style) mode */
 256    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 257       return 16; /* XXX not sure if more are really safe */
 258    default:
 259       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 260       return 0;
 261    }
 262 }
 263
 264 static float
 265 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 266 {
 267    switch (param) {
 268    case PIPE_CAPF_MAX_LINE_WIDTH:
 269    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 270       return 10.0f;
 271    case PIPE_CAPF_MAX_POINT_WIDTH:
 272       return 63.0f;
 273    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 274       return 63.375f;
 275    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 276       return 16.0f;
 277    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 278       return 15.0f;
 279    default:
 280       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 281       return 0.0f;
 282    }
 283 }
 284
 285 static int
 286 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 287                               enum pipe_compute_cap param, void *data)
 288 {
 289    uint64_t *data64 = (uint64_t *)data;
 290    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
 291
 292    switch (param) {
 293    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 294       data64[0] = 3;
 295       return 8;
 296    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 297       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
 298       data64[1] = 65535;
 299       data64[2] = 65535;
 300       return 24;
 301    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 302       data64[0] = 1024;
 303       data64[1] = 1024;
 304       data64[2] = 64;
 305       return 24;
 306    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 307       data64[0] = 1024;
 308       return 8;
 309    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 310       data64[0] = (uint64_t)1 << 40;
 311       return 8;
 312    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 313       data64[0] = 48 << 10;
 314       return 8;
 315    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 316       data64[0] = 512 << 10;
 317       return 8;
 318    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 319       data64[0] = 4096;
 320       return 8;
 321    default:
 322       return 0;
 323    }
 324 }
 325
 326 static void
 327 nvc0_screen_destroy(struct pipe_screen *pscreen)
 328 {
 329    struct nvc0_screen *screen = nvc0_screen(pscreen);
 330
 331    if (screen->base.fence.current) {
 332       nouveau_fence_wait(screen->base.fence.current);
 333       nouveau_fence_ref(NULL, &screen->base.fence.current);
 334    }
 335    if (screen->base.pushbuf)
 336       screen->base.pushbuf->user_priv = NULL;
 337
 338    if (screen->blitter)
 339       nvc0_blitter_destroy(screen);
 340    if (screen->pm.prog) {
 341       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 342       nvc0_program_destroy(NULL, screen->pm.prog);
 343    }
 344
 345    nouveau_bo_ref(NULL, &screen->text);
 346    nouveau_bo_ref(NULL, &screen->uniform_bo);
 347    nouveau_bo_ref(NULL, &screen->tls);
 348    nouveau_bo_ref(NULL, &screen->txc);
 349    nouveau_bo_ref(NULL, &screen->fence.bo);
 350    nouveau_bo_ref(NULL, &screen->poly_cache);
 351    nouveau_bo_ref(NULL, &screen->parm);
 352
 353    nouveau_heap_destroy(&screen->lib_code);
 354    nouveau_heap_destroy(&screen->text_heap);
 355
 356    FREE(screen->tic.entries);
 357
 358    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 359
 360    nouveau_object_del(&screen->eng3d);
 361    nouveau_object_del(&screen->eng2d);
 362    nouveau_object_del(&screen->m2mf);
 363    nouveau_object_del(&screen->compute);
 364    nouveau_object_del(&screen->nvsw);
 365
 366    nouveau_screen_fini(&screen->base);
 367
 368    FREE(screen);
 369 }
 370
 371 static int
 372 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 373                      unsigned size, const uint32_t *data)
 374 {
 375    struct nouveau_pushbuf *push = screen->base.pushbuf;
 376
 377    size /= 4;
 378
 379    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 380    PUSH_DATA (push, (m - 0x3800) / 8);
 381    PUSH_DATA (push, pos);
 382    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 383    PUSH_DATA (push, pos);
 384    PUSH_DATAp(push, data, size);
 385
 386    return pos + size;
 387 }
 388
 389 static void
 390 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 391 {
 392    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 393    PUSH_DATA (push, 0xff);
 394    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 395    PUSH_DATA (push, 0xff);
 396    PUSH_DATA (push, 0xff);
 397    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 398    PUSH_DATA (push, 0xff);
 399    PUSH_DATA (push, 0xff);
 400    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 401    PUSH_DATA (push, 0x3f);
 402
 403    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 404    PUSH_DATA (push, (3 << 16) | 3);
 405    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 406    PUSH_DATA (push, (2 << 16) | 2);
 407    BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
 408    PUSH_DATA (push, 1);
 409
 410    BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 411    PUSH_DATA (push, 0);
 412    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 413    PUSH_DATA (push, 0x10);
 414    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 415    PUSH_DATA (push, 0x10);
 416    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 417    PUSH_DATA (push, 0x10);
 418    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 419    PUSH_DATA (push, 0x10);
 420    PUSH_DATA (push, 0x10);
 421    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 422    PUSH_DATA (push, 0x10);
 423    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 424    PUSH_DATA (push, 0xe);
 425
 426    BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
 427    PUSH_DATA (push, 1 << 12);
 428    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 429    PUSH_DATA (push, 0);
 430    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 431    PUSH_DATA (push, 3);
 432
 433    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 434    PUSH_DATA (push, 0x3fffff);
 435    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 436    PUSH_DATA (push, 1);
 437    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 438    PUSH_DATA (push, 1);
 439    BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 440    PUSH_DATA (push, 3);
 441
 442    if (obj_class >= NVE4_3D_CLASS) {
 443       BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 444       PUSH_DATA (push, 1);
 445    }
 446
 447    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 448     * are supposed to do */
 449 }
 450
 451 static void
 452 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 453 {
 454    struct nvc0_screen *screen = nvc0_screen(pscreen);
 455    struct nouveau_pushbuf *push = screen->base.pushbuf;
 456
 457    /* we need to do it after possible flush in MARK_RING */
 458    *sequence = ++screen->base.fence.sequence;
 459
 460    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
 461    PUSH_DATAh(push, screen->fence.bo->offset);
 462    PUSH_DATA (push, screen->fence.bo->offset);
 463    PUSH_DATA (push, *sequence);
 464    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 465               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 466 }
 467
 468 static u32
 469 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 470 {
 471    struct nvc0_screen *screen = nvc0_screen(pscreen);
 472    return screen->fence.map[0];
 473 }
 474
 475 static int
 476 nvc0_screen_init_compute(struct nvc0_screen *screen)
 477 {
 478    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 479
 480    switch (screen->base.device->chipset & ~0xf) {
 481    case 0xc0:
 482    case 0xd0:
 483       /* Using COMPUTE has weird effects on 3D state, we need to
 484        * investigate this further before enabling it by default.
 485        */
 486       if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
 487          return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 488       return 0;
 489    case 0xe0:
 490    case 0xf0:
 491    case 0x100:
 492       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 493    default:
 494       return -1;
 495    }
 496 }
 497
 498 boolean
 499 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 500                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 501 {
 502    struct nouveau_bo *bo = NULL;
 503    int ret;
 504    uint64_t size = (lpos + lneg) * 32 + cstack;
 505
 506    if (size >= (1 << 20)) {
 507       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 508       return FALSE;
 509    }
 510
 511    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 512    size  = align(size, 0x8000);
 513    size *= screen->mp_count;
 514
 515    size = align(size, 1 << 17);
 516
 517    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
 518                         NULL, &bo);
 519    if (ret) {
 520       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 521       return FALSE;
 522    }
 523    nouveau_bo_ref(NULL, &screen->tls);
 524    screen->tls = bo;
 525    return TRUE;
 526 }
 527
 528 #define FAIL_SCREEN_INIT(str, err)                    \
 529    do {                                               \
 530       NOUVEAU_ERR(str, err);                          \
 531       nvc0_screen_destroy(pscreen);                   \
 532       return NULL;                                    \
 533    } while(0)
 534
 535 struct pipe_screen *
 536 nvc0_screen_create(struct nouveau_device *dev)
 537 {
 538    struct nvc0_screen *screen;
 539    struct pipe_screen *pscreen;
 540    struct nouveau_object *chan;
 541    struct nouveau_pushbuf *push;
 542    uint64_t value;
 543    uint32_t obj_class;
 544    int ret;
 545    unsigned i;
 546    union nouveau_bo_config mm_config;
 547
 548    switch (dev->chipset & ~0xf) {
 549    case 0xc0:
 550    case 0xd0:
 551    case 0xe0:
 552    case 0xf0:
 553    case 0x100:
 554       break;
 555    default:
 556       return NULL;
 557    }
 558
 559    screen = CALLOC_STRUCT(nvc0_screen);
 560    if (!screen)
 561       return NULL;
 562    pscreen = &screen->base.base;
 563
 564    ret = nouveau_screen_init(&screen->base, dev);
 565    if (ret) {
 566       nvc0_screen_destroy(pscreen);
 567       return NULL;
 568    }
 569    chan = screen->base.channel;
 570    push = screen->base.pushbuf;
 571    push->user_priv = screen;
 572    push->rsvd_kick = 5;
 573
 574    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 575       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 576    screen->base.sysmem_bindings |=
 577       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 578
 579    pscreen->destroy = nvc0_screen_destroy;
 580    pscreen->context_create = nvc0_create;
 581    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 582    pscreen->get_param = nvc0_screen_get_param;
 583    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 584    pscreen->get_paramf = nvc0_screen_get_paramf;
 585    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 586
 587    nvc0_screen_init_resource_functions(pscreen);
 588
 589    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 590    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 591
 592    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
 593                         &screen->fence.bo);
 594    if (ret)
 595       goto fail;
 596    nouveau_bo_map(screen->fence.bo, 0, NULL);
 597    screen->fence.map = screen->fence.bo->map;
 598    screen->base.fence.emit = nvc0_screen_fence_emit;
 599    screen->base.fence.update = nvc0_screen_fence_update;
 600
 601
 602    ret = nouveau_object_new(chan,
 603                             (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
 604                             NULL, 0, &screen->nvsw);
 605    if (ret)
 606       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 607
 608
 609    switch (dev->chipset & ~0xf) {
 610    case 0x100:
 611    case 0xf0:
 612       obj_class = NVF0_P2MF_CLASS;
 613       break;
 614    case 0xe0:
 615       obj_class = NVE4_P2MF_CLASS;
 616       break;
 617    default:
 618       obj_class = NVC0_M2MF_CLASS;
 619       break;
 620    }
 621    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 622                             &screen->m2mf);
 623    if (ret)
 624       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 625
 626    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 627    PUSH_DATA (push, screen->m2mf->oclass);
 628    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 629       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 630       PUSH_DATA (push, 0xa0b5);
 631    }
 632
 633    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 634                             &screen->eng2d);
 635    if (ret)
 636       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 637
 638    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 639    PUSH_DATA (push, screen->eng2d->oclass);
 640    BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
 641    PUSH_DATA (push, 0);
 642    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 643    PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
 644    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 645    PUSH_DATA (push, 0);
 646    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 647    PUSH_DATA (push, 0);
 648    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 649    PUSH_DATA (push, 0x3f);
 650    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 651    PUSH_DATA (push, 1);
 652
 653    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 654    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 655    PUSH_DATA (push, screen->fence.bo->offset + 16);
 656
 657    switch (dev->chipset & ~0xf) {
 658    case 0x100:
 659    case 0xf0:
 660       obj_class = NVF0_3D_CLASS;
 661       break;
 662    case 0xe0:
 663       obj_class = NVE4_3D_CLASS;
 664       break;
 665    case 0xd0:
 666       obj_class = NVC8_3D_CLASS;
 667       break;
 668    case 0xc0:
 669    default:
 670       switch (dev->chipset) {
 671       case 0xc8:
 672          obj_class = NVC8_3D_CLASS;
 673          break;
 674       case 0xc1:
 675          obj_class = NVC1_3D_CLASS;
 676          break;
 677       default:
 678          obj_class = NVC0_3D_CLASS;
 679          break;
 680       }
 681       break;
 682    }
 683    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 684                             &screen->eng3d);
 685    if (ret)
 686       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 687    screen->base.class_3d = obj_class;
 688
 689    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 690    PUSH_DATA (push, screen->eng3d->oclass);
 691
 692    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 693    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 694
 695    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 696       /* kill shaders after about 1 second (at 100 MHz) */
 697       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 698       PUSH_DATA (push, 0x17);
 699    }
 700
 701    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
 702    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 703    for (i = 0; i < 8; ++i)
 704            PUSH_DATA(push, dev->drm_version >= 0x01000101);
 705
 706    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 707    PUSH_DATA (push, 1);
 708
 709    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 710    PUSH_DATA (push, 0);
 711    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 712    PUSH_DATA (push, 0);
 713    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 714    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 715    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 716    PUSH_DATA (push, 0);
 717    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 718    PUSH_DATA (push, 1);
 719    BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
 720    PUSH_DATA (push, 0);
 721    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 722    PUSH_DATA (push, 1);
 723    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 724    PUSH_DATA (push, 0);
 725    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 726       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 727       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 728    } else {
 729       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 730       PUSH_DATA (push, 15);
 731    }
 732    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 733    PUSH_DATA (push, 8); /* 128 */
 734    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 735    PUSH_DATA (push, 1);
 736    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 737       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 738       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 739    }
 740
 741    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 742
 743    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 744                         &screen->text);
 745    if (ret)
 746       goto fail;
 747
 748    /* XXX: getting a page fault at the end of the code buffer every few
 749     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 750     */
 751    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 752
 753    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
 754                         &screen->uniform_bo);
 755    if (ret)
 756       goto fail;
 757
 758    PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 759
 760    for (i = 0; i < 5; ++i) {
 761       /* TIC and TSC entries for each unit (nve4+ only) */
 762       /* auxiliary constants (6 user clip planes, base instance id) */
 763       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 764       PUSH_DATA (push, 512);
 765       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 766       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 767       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 768       PUSH_DATA (push, (15 << 4) | 1);
 769       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 770          unsigned j;
 771          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 772          PUSH_DATA (push, 0);
 773          for (j = 0; j < 8; ++j)
 774             PUSH_DATA(push, j);
 775       } else {
 776          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 777          PUSH_DATA (push, 0x54);
 778       }
 779    }
 780    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 781    PUSH_DATA (push, 0);
 782
 783    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 784    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 785    PUSH_DATA (push, 256);
 786    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 787    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 788    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 789    PUSH_DATA (push, 0);
 790    PUSH_DATAf(push, 0.0f);
 791    PUSH_DATAf(push, 0.0f);
 792    PUSH_DATAf(push, 0.0f);
 793    PUSH_DATAf(push, 0.0f);
 794    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 795    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 796    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 797
 798    if (dev->drm_version >= 0x01000101) {
 799       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 800       if (ret) {
 801          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 802          goto fail;
 803       }
 804    } else {
 805       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 806          value = (8 << 8) | 4;
 807       else
 808          value = (16 << 8) | 4;
 809    }
 810    screen->mp_count = value >> 8;
 811    screen->mp_count_compute = screen->mp_count;
 812
 813    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 814
 815    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 816    PUSH_DATAh(push, screen->text->offset);
 817    PUSH_DATA (push, screen->text->offset);
 818    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 819    PUSH_DATAh(push, screen->tls->offset);
 820    PUSH_DATA (push, screen->tls->offset);
 821    PUSH_DATA (push, screen->tls->size >> 32);
 822    PUSH_DATA (push, screen->tls->size);
 823    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 824    PUSH_DATA (push, 0);
 825    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 826    PUSH_DATA (push, 0);
 827
 828    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 829                         &screen->poly_cache);
 830    if (ret)
 831       goto fail;
 832
 833    BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 834    PUSH_DATAh(push, screen->poly_cache->offset);
 835    PUSH_DATA (push, screen->poly_cache->offset);
 836    PUSH_DATA (push, 3);
 837
 838    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
 839                         &screen->txc);
 840    if (ret)
 841       goto fail;
 842
 843    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 844    PUSH_DATAh(push, screen->txc->offset);
 845    PUSH_DATA (push, screen->txc->offset);
 846    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 847
 848    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 849    PUSH_DATAh(push, screen->txc->offset + 65536);
 850    PUSH_DATA (push, screen->txc->offset + 65536);
 851    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 852
 853    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 854    PUSH_DATA (push, 0);
 855    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 856    PUSH_DATA (push, 0);
 857    PUSH_DATA (push, 0);
 858    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 859    PUSH_DATA (push, 0x3f);
 860
 861    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 862    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 863    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 864    for (i = 0; i < 8 * 2; ++i)
 865       PUSH_DATA(push, 0);
 866    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 867    PUSH_DATA (push, 0);
 868    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 869    PUSH_DATA (push, 0);
 870
 871    /* neither scissors, viewport nor stencil mask should affect clears */
 872    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 873    PUSH_DATA (push, 0);
 874
 875    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 876    PUSH_DATA (push, 1);
 877    BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
 878    PUSH_DATAf(push, 0.0f);
 879    PUSH_DATAf(push, 1.0f);
 880    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 881    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 882
 883    /* We use scissors instead of exact view volume clipping,
 884     * so they're always enabled.
 885     */
 886    BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
 887    PUSH_DATA (push, 1);
 888    PUSH_DATA (push, 8192 << 16);
 889    PUSH_DATA (push, 8192 << 16);
 890
 891 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 892
 893    i = 0;
 894    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
 895    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
 896    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 897    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
 898    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
 899    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 900    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 901
 902    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
 903    PUSH_DATA (push, 1);
 904    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
 905    PUSH_DATA (push, 1);
 906    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 907    PUSH_DATA (push, 0x40);
 908    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
 909    PUSH_DATA (push, 0);
 910    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 911    PUSH_DATA (push, 0x30);
 912    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
 913    PUSH_DATA (push, 3);
 914    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
 915    PUSH_DATA (push, 0x20);
 916    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
 917    PUSH_DATA (push, 0x00);
 918
 919    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
 920    PUSH_DATA (push, 0);
 921    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
 922    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
 923
 924    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
 925
 926    if (nvc0_screen_init_compute(screen))
 927       goto fail;
 928
 929    PUSH_KICK (push);
 930
 931    screen->tic.entries = CALLOC(4096, sizeof(void *));
 932    screen->tsc.entries = screen->tic.entries + 2048;
 933
 934    mm_config.nvc0.tile_mode = 0;
 935    mm_config.nvc0.memtype = 0xfe0;
 936    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
 937
 938    if (!nvc0_blitter_create(screen))
 939       goto fail;
 940
 941    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 942
 943    return pscreen;
 944
 945 fail:
 946    nvc0_screen_destroy(pscreen);
 947    return NULL;
 948 }
 949
 950 int
 951 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 952 {
 953    int i = screen->tic.next;
 954
 955    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 956       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 957
 958    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 959
 960    if (screen->tic.entries[i])
 961       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 962
 963    screen->tic.entries[i] = entry;
 964    return i;
 965 }
 966
 967 int
 968 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 969 {
 970    int i = screen->tsc.next;
 971
 972    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 973       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 974
 975    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 976
 977    if (screen->tsc.entries[i])
 978       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 979
 980    screen->tsc.entries[i] = entry;
 981    return i;
 982 }