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nv50,nvc0: use a face sysval to avoid the useless back-and-forth conversion
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 if (sample_count > 8)
48 return false;
49 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
50 return false;
51
52 if (!util_format_is_supported(format, bindings))
53 return false;
54
55 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
56 if (util_format_get_blocksizebits(format) == 3 * 32)
57 return false;
58
59 /* transfers & shared are always supported */
60 bindings &= ~(PIPE_BIND_TRANSFER_READ |
61 PIPE_BIND_TRANSFER_WRITE |
62 PIPE_BIND_SHARED);
63
64 return (nvc0_format_table[format].usage & bindings) == bindings;
65 }
66
67 static int
68 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
69 {
70 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
71 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
72
73 switch (param) {
74 /* non-boolean caps */
75 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
76 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
77 return 15;
78 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
79 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
80 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
81 return 2048;
82 case PIPE_CAP_MIN_TEXEL_OFFSET:
83 return -8;
84 case PIPE_CAP_MAX_TEXEL_OFFSET:
85 return 7;
86 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
87 return -32;
88 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
89 return 31;
90 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
91 return 128 * 1024 * 1024;
92 case PIPE_CAP_GLSL_FEATURE_LEVEL:
93 return 410;
94 case PIPE_CAP_MAX_RENDER_TARGETS:
95 return 8;
96 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
97 return 1;
98 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
99 return 4;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
101 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
102 return 128;
103 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
104 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
105 return 1024;
106 case PIPE_CAP_MAX_VERTEX_STREAMS:
107 return 4;
108 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
109 return 2048;
110 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
111 return 256;
112 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
113 return 1; /* 256 for binding as RT, but that's not possible in GL */
114 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
115 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
116 case PIPE_CAP_MAX_VIEWPORTS:
117 return NVC0_MAX_VIEWPORTS;
118 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
119 return 4;
120 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
121 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
122 case PIPE_CAP_ENDIANNESS:
123 return PIPE_ENDIAN_LITTLE;
124 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
125 return 30;
126
127 /* supported caps */
128 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
129 case PIPE_CAP_TEXTURE_SWIZZLE:
130 case PIPE_CAP_TEXTURE_SHADOW_MAP:
131 case PIPE_CAP_NPOT_TEXTURES:
132 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
133 case PIPE_CAP_ANISOTROPIC_FILTER:
134 case PIPE_CAP_SEAMLESS_CUBE_MAP:
135 case PIPE_CAP_CUBE_MAP_ARRAY:
136 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
137 case PIPE_CAP_TEXTURE_MULTISAMPLE:
138 case PIPE_CAP_TWO_SIDED_STENCIL:
139 case PIPE_CAP_DEPTH_CLIP_DISABLE:
140 case PIPE_CAP_POINT_SPRITE:
141 case PIPE_CAP_TGSI_TEXCOORD:
142 case PIPE_CAP_SM3:
143 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
144 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
145 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
146 case PIPE_CAP_QUERY_TIMESTAMP:
147 case PIPE_CAP_QUERY_TIME_ELAPSED:
148 case PIPE_CAP_OCCLUSION_QUERY:
149 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
150 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
151 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
152 case PIPE_CAP_INDEP_BLEND_ENABLE:
153 case PIPE_CAP_INDEP_BLEND_FUNC:
154 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
155 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
156 case PIPE_CAP_PRIMITIVE_RESTART:
157 case PIPE_CAP_TGSI_INSTANCEID:
158 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
159 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
160 case PIPE_CAP_CONDITIONAL_RENDER:
161 case PIPE_CAP_TEXTURE_BARRIER:
162 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
163 case PIPE_CAP_START_INSTANCE:
164 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
165 case PIPE_CAP_DRAW_INDIRECT:
166 case PIPE_CAP_USER_CONSTANT_BUFFERS:
167 case PIPE_CAP_USER_INDEX_BUFFERS:
168 case PIPE_CAP_USER_VERTEX_BUFFERS:
169 case PIPE_CAP_TEXTURE_QUERY_LOD:
170 case PIPE_CAP_SAMPLE_SHADING:
171 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
172 case PIPE_CAP_TEXTURE_GATHER_SM5:
173 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
174 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
175 case PIPE_CAP_SAMPLER_VIEW_TARGET:
176 case PIPE_CAP_CLIP_HALFZ:
177 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
178 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
179 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
180 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
181 case PIPE_CAP_DEPTH_BOUNDS_TEST:
182 case PIPE_CAP_TGSI_TXQS:
183 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
184 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
185 case PIPE_CAP_SHAREABLE_SHADERS:
186 case PIPE_CAP_CLEAR_TEXTURE:
187 case PIPE_CAP_DRAW_PARAMETERS:
188 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
189 case PIPE_CAP_MULTI_DRAW_INDIRECT:
190 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
191 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
192 return 1;
193 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
194 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
195 case PIPE_CAP_COMPUTE:
196 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
197 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
198 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
199
200 /* unsupported caps */
201 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
202 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
203 case PIPE_CAP_SHADER_STENCIL_EXPORT:
204 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
205 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
206 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
207 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
208 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
209 case PIPE_CAP_FAKE_SW_MSAA:
210 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
211 case PIPE_CAP_VERTEXID_NOBASE:
212 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
213 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
214 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
215 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
216 return 0;
217
218 case PIPE_CAP_VENDOR_ID:
219 return 0x10de;
220 case PIPE_CAP_DEVICE_ID: {
221 uint64_t device_id;
222 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
223 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
224 return -1;
225 }
226 return device_id;
227 }
228 case PIPE_CAP_ACCELERATED:
229 return 1;
230 case PIPE_CAP_VIDEO_MEMORY:
231 return dev->vram_size >> 20;
232 case PIPE_CAP_UMA:
233 return 0;
234 }
235
236 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
237 return 0;
238 }
239
240 static int
241 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
242 enum pipe_shader_cap param)
243 {
244 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
245
246 switch (shader) {
247 case PIPE_SHADER_VERTEX:
248 case PIPE_SHADER_GEOMETRY:
249 case PIPE_SHADER_FRAGMENT:
250 break;
251 case PIPE_SHADER_TESS_CTRL:
252 case PIPE_SHADER_TESS_EVAL:
253 if (class_3d >= GM107_3D_CLASS)
254 return 0;
255 break;
256 case PIPE_SHADER_COMPUTE:
257 if (class_3d > NVE4_3D_CLASS)
258 return 0;
259 break;
260 default:
261 return 0;
262 }
263
264 switch (param) {
265 case PIPE_SHADER_CAP_PREFERRED_IR:
266 return PIPE_SHADER_IR_TGSI;
267 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
268 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
269 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
270 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
271 return 16384;
272 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
273 return 16;
274 case PIPE_SHADER_CAP_MAX_INPUTS:
275 if (shader == PIPE_SHADER_VERTEX)
276 return 32;
277 /* NOTE: These only count our slots for GENERIC varyings.
278 * The address space may be larger, but the actual hard limit seems to be
279 * less than what the address space layout permits, so don't add TEXCOORD,
280 * COLOR, etc. here.
281 */
282 if (shader == PIPE_SHADER_FRAGMENT)
283 return 0x1f0 / 16;
284 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
285 * and excludes 0x60 per-patch inputs.
286 */
287 return 0x200 / 16;
288 case PIPE_SHADER_CAP_MAX_OUTPUTS:
289 return 32;
290 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
291 return 65536;
292 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
293 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
294 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
295 return NVC0_MAX_PIPE_CONSTBUFS;
296 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
297 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
298 return shader != PIPE_SHADER_FRAGMENT;
299 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
300 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
301 return 1;
302 case PIPE_SHADER_CAP_MAX_PREDS:
303 return 0;
304 case PIPE_SHADER_CAP_MAX_TEMPS:
305 return NVC0_CAP_MAX_PROGRAM_TEMPS;
306 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
307 return 1;
308 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
309 return 0;
310 case PIPE_SHADER_CAP_SUBROUTINES:
311 return 1;
312 case PIPE_SHADER_CAP_INTEGERS:
313 return 1;
314 case PIPE_SHADER_CAP_DOUBLES:
315 return 1;
316 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
317 return 1;
318 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
319 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
320 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
321 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
322 return 0;
323 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
324 return 16; /* would be 32 in linked (OpenGL-style) mode */
325 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
326 return 16; /* XXX not sure if more are really safe */
327 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
328 return 32;
329 default:
330 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
331 return 0;
332 }
333 }
334
335 static float
336 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
337 {
338 switch (param) {
339 case PIPE_CAPF_MAX_LINE_WIDTH:
340 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
341 return 10.0f;
342 case PIPE_CAPF_MAX_POINT_WIDTH:
343 return 63.0f;
344 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
345 return 63.375f;
346 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
347 return 16.0f;
348 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
349 return 15.0f;
350 case PIPE_CAPF_GUARD_BAND_LEFT:
351 case PIPE_CAPF_GUARD_BAND_TOP:
352 return 0.0f;
353 case PIPE_CAPF_GUARD_BAND_RIGHT:
354 case PIPE_CAPF_GUARD_BAND_BOTTOM:
355 return 0.0f; /* that or infinity */
356 }
357
358 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
359 return 0.0f;
360 }
361
362 static int
363 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
364 enum pipe_compute_cap param, void *data)
365 {
366 struct nvc0_screen *screen = nvc0_screen(pscreen);
367 const uint16_t obj_class = screen->compute->oclass;
368
369 #define RET(x) do { \
370 if (data) \
371 memcpy(data, x, sizeof(x)); \
372 return sizeof(x); \
373 } while (0)
374
375 switch (param) {
376 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
377 RET((uint64_t []) { 3 });
378 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
379 if (obj_class >= NVE4_COMPUTE_CLASS) {
380 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
381 } else {
382 RET(((uint64_t []) { 65535, 65535, 65535 }));
383 }
384 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
385 RET(((uint64_t []) { 1024, 1024, 64 }));
386 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
387 RET((uint64_t []) { 1024 });
388 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
389 RET((uint64_t []) { 1ULL << 40 });
390 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
391 RET((uint64_t []) { 48 << 10 });
392 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
393 RET((uint64_t []) { 512 << 10 });
394 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
395 RET((uint64_t []) { 4096 });
396 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
397 RET((uint32_t []) { 32 });
398 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
399 RET((uint64_t []) { 1ULL << 40 });
400 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
401 RET((uint32_t []) { 0 });
402 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
403 RET((uint32_t []) { screen->mp_count_compute });
404 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
405 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
406 default:
407 return 0;
408 }
409
410 #undef RET
411 }
412
413 static void
414 nvc0_screen_destroy(struct pipe_screen *pscreen)
415 {
416 struct nvc0_screen *screen = nvc0_screen(pscreen);
417
418 if (!nouveau_drm_screen_unref(&screen->base))
419 return;
420
421 if (screen->base.fence.current) {
422 struct nouveau_fence *current = NULL;
423
424 /* nouveau_fence_wait will create a new current fence, so wait on the
425 * _current_ one, and remove both.
426 */
427 nouveau_fence_ref(screen->base.fence.current, &current);
428 nouveau_fence_wait(current, NULL);
429 nouveau_fence_ref(NULL, &current);
430 nouveau_fence_ref(NULL, &screen->base.fence.current);
431 }
432 if (screen->base.pushbuf)
433 screen->base.pushbuf->user_priv = NULL;
434
435 if (screen->blitter)
436 nvc0_blitter_destroy(screen);
437 if (screen->pm.prog) {
438 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
439 nvc0_program_destroy(NULL, screen->pm.prog);
440 FREE(screen->pm.prog);
441 }
442
443 nouveau_bo_ref(NULL, &screen->text);
444 nouveau_bo_ref(NULL, &screen->uniform_bo);
445 nouveau_bo_ref(NULL, &screen->tls);
446 nouveau_bo_ref(NULL, &screen->txc);
447 nouveau_bo_ref(NULL, &screen->fence.bo);
448 nouveau_bo_ref(NULL, &screen->poly_cache);
449 nouveau_bo_ref(NULL, &screen->parm);
450
451 nouveau_heap_destroy(&screen->lib_code);
452 nouveau_heap_destroy(&screen->text_heap);
453
454 FREE(screen->tic.entries);
455
456 nouveau_object_del(&screen->eng3d);
457 nouveau_object_del(&screen->eng2d);
458 nouveau_object_del(&screen->m2mf);
459 nouveau_object_del(&screen->compute);
460 nouveau_object_del(&screen->nvsw);
461
462 nouveau_screen_fini(&screen->base);
463
464 FREE(screen);
465 }
466
467 static int
468 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
469 unsigned size, const uint32_t *data)
470 {
471 struct nouveau_pushbuf *push = screen->base.pushbuf;
472
473 size /= 4;
474
475 assert((pos + size) <= 0x800);
476
477 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
478 PUSH_DATA (push, (m - 0x3800) / 8);
479 PUSH_DATA (push, pos);
480 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
481 PUSH_DATA (push, pos);
482 PUSH_DATAp(push, data, size);
483
484 return pos + size;
485 }
486
487 static void
488 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
489 {
490 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
491 PUSH_DATA (push, 0xff);
492 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
493 PUSH_DATA (push, 0xff);
494 PUSH_DATA (push, 0xff);
495 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
496 PUSH_DATA (push, 0xff);
497 PUSH_DATA (push, 0xff);
498 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
499 PUSH_DATA (push, 0x3f);
500
501 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
502 PUSH_DATA (push, (3 << 16) | 3);
503 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
504 PUSH_DATA (push, (2 << 16) | 2);
505
506 if (obj_class < GM107_3D_CLASS) {
507 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
508 PUSH_DATA (push, 0);
509 }
510 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
511 PUSH_DATA (push, 0x10);
512 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
513 PUSH_DATA (push, 0x10);
514 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
515 PUSH_DATA (push, 0x10);
516 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
517 PUSH_DATA (push, 0x10);
518 PUSH_DATA (push, 0x10);
519 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
520 PUSH_DATA (push, 0x10);
521 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
522 PUSH_DATA (push, 0xe);
523
524 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
525 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
526 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
527 PUSH_DATA (push, 0);
528 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
529 PUSH_DATA (push, 3);
530
531 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
532 PUSH_DATA (push, 0x3fffff);
533 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
534 PUSH_DATA (push, 1);
535 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
536 PUSH_DATA (push, 1);
537
538 if (obj_class < GM107_3D_CLASS) {
539 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
540 PUSH_DATA (push, 3);
541
542 if (obj_class >= NVE4_3D_CLASS) {
543 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
544 PUSH_DATA (push, 1);
545 }
546 }
547
548 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
549 * are supposed to do */
550 }
551
552 static void
553 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
554 {
555 struct nvc0_screen *screen = nvc0_screen(pscreen);
556 struct nouveau_pushbuf *push = screen->base.pushbuf;
557
558 /* we need to do it after possible flush in MARK_RING */
559 *sequence = ++screen->base.fence.sequence;
560
561 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
562 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
563 PUSH_DATAh(push, screen->fence.bo->offset);
564 PUSH_DATA (push, screen->fence.bo->offset);
565 PUSH_DATA (push, *sequence);
566 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
567 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
568 }
569
570 static u32
571 nvc0_screen_fence_update(struct pipe_screen *pscreen)
572 {
573 struct nvc0_screen *screen = nvc0_screen(pscreen);
574 return screen->fence.map[0];
575 }
576
577 static int
578 nvc0_screen_init_compute(struct nvc0_screen *screen)
579 {
580 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
581
582 switch (screen->base.device->chipset & ~0xf) {
583 case 0xc0:
584 case 0xd0:
585 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
586 case 0xe0:
587 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
588 case 0xf0:
589 case 0x100:
590 case 0x110:
591 return 0;
592 default:
593 return -1;
594 }
595 }
596
597 bool
598 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
599 uint32_t lpos, uint32_t lneg, uint32_t cstack)
600 {
601 struct nouveau_bo *bo = NULL;
602 int ret;
603 uint64_t size = (lpos + lneg) * 32 + cstack;
604
605 if (size >= (1 << 20)) {
606 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
607 return false;
608 }
609
610 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
611 size = align(size, 0x8000);
612 size *= screen->mp_count;
613
614 size = align(size, 1 << 17);
615
616 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
617 NULL, &bo);
618 if (ret) {
619 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
620 return false;
621 }
622 nouveau_bo_ref(NULL, &screen->tls);
623 screen->tls = bo;
624 return true;
625 }
626
627 #define FAIL_SCREEN_INIT(str, err) \
628 do { \
629 NOUVEAU_ERR(str, err); \
630 goto fail; \
631 } while(0)
632
633 struct nouveau_screen *
634 nvc0_screen_create(struct nouveau_device *dev)
635 {
636 struct nvc0_screen *screen;
637 struct pipe_screen *pscreen;
638 struct nouveau_object *chan;
639 struct nouveau_pushbuf *push;
640 uint64_t value;
641 uint32_t obj_class;
642 uint32_t flags;
643 int ret;
644 unsigned i;
645
646 switch (dev->chipset & ~0xf) {
647 case 0xc0:
648 case 0xd0:
649 case 0xe0:
650 case 0xf0:
651 case 0x100:
652 case 0x110:
653 break;
654 default:
655 return NULL;
656 }
657
658 screen = CALLOC_STRUCT(nvc0_screen);
659 if (!screen)
660 return NULL;
661 pscreen = &screen->base.base;
662 pscreen->destroy = nvc0_screen_destroy;
663
664 ret = nouveau_screen_init(&screen->base, dev);
665 if (ret) {
666 nvc0_screen_destroy(pscreen);
667 return NULL;
668 }
669 chan = screen->base.channel;
670 push = screen->base.pushbuf;
671 push->user_priv = screen;
672 push->rsvd_kick = 5;
673
674 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
675 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
676 PIPE_BIND_COMMAND_ARGS_BUFFER;
677 screen->base.sysmem_bindings |=
678 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
679
680 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
681 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
682 screen->base.vidmem_bindings = 0;
683 }
684
685 pscreen->context_create = nvc0_create;
686 pscreen->is_format_supported = nvc0_screen_is_format_supported;
687 pscreen->get_param = nvc0_screen_get_param;
688 pscreen->get_shader_param = nvc0_screen_get_shader_param;
689 pscreen->get_paramf = nvc0_screen_get_paramf;
690 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
691 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
692
693 nvc0_screen_init_resource_functions(pscreen);
694
695 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
696 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
697
698 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
699 if (screen->base.drm->version >= 0x01000202)
700 flags |= NOUVEAU_BO_COHERENT;
701
702 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
703 if (ret)
704 goto fail;
705 nouveau_bo_map(screen->fence.bo, 0, NULL);
706 screen->fence.map = screen->fence.bo->map;
707 screen->base.fence.emit = nvc0_screen_fence_emit;
708 screen->base.fence.update = nvc0_screen_fence_update;
709
710
711 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
712 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
713 if (ret)
714 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
715
716 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
717 PUSH_DATA (push, screen->nvsw->handle);
718
719 switch (dev->chipset & ~0xf) {
720 case 0x110:
721 case 0x100:
722 case 0xf0:
723 obj_class = NVF0_P2MF_CLASS;
724 break;
725 case 0xe0:
726 obj_class = NVE4_P2MF_CLASS;
727 break;
728 default:
729 obj_class = NVC0_M2MF_CLASS;
730 break;
731 }
732 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
733 &screen->m2mf);
734 if (ret)
735 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
736
737 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
738 PUSH_DATA (push, screen->m2mf->oclass);
739 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
740 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
741 PUSH_DATA (push, 0xa0b5);
742 }
743
744 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
745 &screen->eng2d);
746 if (ret)
747 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
748
749 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
750 PUSH_DATA (push, screen->eng2d->oclass);
751 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
752 PUSH_DATA (push, 0);
753 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
754 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
755 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
756 PUSH_DATA (push, 0);
757 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
758 PUSH_DATA (push, 0);
759 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
760 PUSH_DATA (push, 0x3f);
761 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
762 PUSH_DATA (push, 1);
763 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
764 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
765
766 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
767 PUSH_DATAh(push, screen->fence.bo->offset + 16);
768 PUSH_DATA (push, screen->fence.bo->offset + 16);
769
770 switch (dev->chipset & ~0xf) {
771 case 0x110:
772 obj_class = GM107_3D_CLASS;
773 break;
774 case 0x100:
775 case 0xf0:
776 obj_class = NVF0_3D_CLASS;
777 break;
778 case 0xe0:
779 switch (dev->chipset) {
780 case 0xea:
781 obj_class = NVEA_3D_CLASS;
782 break;
783 default:
784 obj_class = NVE4_3D_CLASS;
785 break;
786 }
787 break;
788 case 0xd0:
789 obj_class = NVC8_3D_CLASS;
790 break;
791 case 0xc0:
792 default:
793 switch (dev->chipset) {
794 case 0xc8:
795 obj_class = NVC8_3D_CLASS;
796 break;
797 case 0xc1:
798 obj_class = NVC1_3D_CLASS;
799 break;
800 default:
801 obj_class = NVC0_3D_CLASS;
802 break;
803 }
804 break;
805 }
806 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
807 &screen->eng3d);
808 if (ret)
809 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
810 screen->base.class_3d = obj_class;
811
812 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
813 PUSH_DATA (push, screen->eng3d->oclass);
814
815 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
816 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
817
818 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
819 /* kill shaders after about 1 second (at 100 MHz) */
820 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
821 PUSH_DATA (push, 0x17);
822 }
823
824 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
825 screen->base.drm->version >= 0x01000101);
826 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
827 for (i = 0; i < 8; ++i)
828 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
829
830 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
831 PUSH_DATA (push, 1);
832
833 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
834 PUSH_DATA (push, 0);
835 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
836 PUSH_DATA (push, 0);
837 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
838 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
839 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
840 PUSH_DATA (push, 0);
841 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
842 PUSH_DATA (push, 1);
843 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
844 PUSH_DATA (push, 1);
845 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
846 PUSH_DATA (push, 1);
847 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
848 PUSH_DATA (push, 0);
849 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
850 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
851 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
852 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
853 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
854 } else {
855 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
856 PUSH_DATA (push, 15);
857 }
858 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
859 PUSH_DATA (push, 8); /* 128 */
860 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
861 PUSH_DATA (push, 1);
862 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
863 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
864 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
865 }
866
867 nvc0_magic_3d_init(push, screen->eng3d->oclass);
868
869 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
870 &screen->text);
871 if (ret)
872 goto fail;
873
874 /* XXX: getting a page fault at the end of the code buffer every few
875 * launches, don't use the last 256 bytes to work around them - prefetch ?
876 */
877 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
878
879 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
880 &screen->uniform_bo);
881 if (ret)
882 goto fail;
883
884 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
885
886 for (i = 0; i < 5; ++i) {
887 /* TIC and TSC entries for each unit (nve4+ only) */
888 /* auxiliary constants (6 user clip planes, base instance id) */
889 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
890 PUSH_DATA (push, 512);
891 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
892 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
893 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
894 PUSH_DATA (push, (15 << 4) | 1);
895 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
896 unsigned j;
897 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
898 PUSH_DATA (push, 0);
899 for (j = 0; j < 8; ++j)
900 PUSH_DATA(push, j);
901 } else {
902 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
903 PUSH_DATA (push, 0x54);
904 }
905 }
906 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
907 PUSH_DATA (push, 0);
908
909 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
910 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
911 PUSH_DATA (push, 256);
912 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
913 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
914 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
915 PUSH_DATA (push, 0);
916 PUSH_DATAf(push, 0.0f);
917 PUSH_DATAf(push, 0.0f);
918 PUSH_DATAf(push, 0.0f);
919 PUSH_DATAf(push, 0.0f);
920 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
921 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
922 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
923
924 if (screen->base.drm->version >= 0x01000101) {
925 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
926 if (ret) {
927 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
928 goto fail;
929 }
930 } else {
931 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
932 value = (8 << 8) | 4;
933 else
934 value = (16 << 8) | 4;
935 }
936 screen->gpc_count = value & 0x000000ff;
937 screen->mp_count = value >> 8;
938 screen->mp_count_compute = screen->mp_count;
939
940 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
941
942 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
943 PUSH_DATAh(push, screen->text->offset);
944 PUSH_DATA (push, screen->text->offset);
945 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
946 PUSH_DATAh(push, screen->tls->offset);
947 PUSH_DATA (push, screen->tls->offset);
948 PUSH_DATA (push, screen->tls->size >> 32);
949 PUSH_DATA (push, screen->tls->size);
950 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
951 PUSH_DATA (push, 0);
952 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
953 PUSH_DATA (push, 0);
954
955 if (screen->eng3d->oclass < GM107_3D_CLASS) {
956 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
957 &screen->poly_cache);
958 if (ret)
959 goto fail;
960
961 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
962 PUSH_DATAh(push, screen->poly_cache->offset);
963 PUSH_DATA (push, screen->poly_cache->offset);
964 PUSH_DATA (push, 3);
965 }
966
967 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
968 &screen->txc);
969 if (ret)
970 goto fail;
971
972 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
973 PUSH_DATAh(push, screen->txc->offset);
974 PUSH_DATA (push, screen->txc->offset);
975 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
976
977 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
978 PUSH_DATAh(push, screen->txc->offset + 65536);
979 PUSH_DATA (push, screen->txc->offset + 65536);
980 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
981
982 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
983 PUSH_DATA (push, 0);
984 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
985 PUSH_DATA (push, 0);
986 PUSH_DATA (push, 0);
987 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
988 PUSH_DATA (push, 0x3f);
989
990 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
991 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
992 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
993 for (i = 0; i < 8 * 2; ++i)
994 PUSH_DATA(push, 0);
995 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
996 PUSH_DATA (push, 0);
997 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
998 PUSH_DATA (push, 0);
999
1000 /* neither scissors, viewport nor stencil mask should affect clears */
1001 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1002 PUSH_DATA (push, 0);
1003
1004 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1005 PUSH_DATA (push, 1);
1006 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1007 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1008 PUSH_DATAf(push, 0.0f);
1009 PUSH_DATAf(push, 1.0f);
1010 }
1011 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1012 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1013
1014 /* We use scissors instead of exact view volume clipping,
1015 * so they're always enabled.
1016 */
1017 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1018 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1019 PUSH_DATA (push, 1);
1020 PUSH_DATA (push, 8192 << 16);
1021 PUSH_DATA (push, 8192 << 16);
1022 }
1023
1024 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1025
1026 i = 0;
1027 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1028 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1029 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1030 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1031 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1032 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1033 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1034 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1035 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1036 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1037 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1038
1039 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1040 PUSH_DATA (push, 1);
1041 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1042 PUSH_DATA (push, 1);
1043 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1044 PUSH_DATA (push, 0x40);
1045 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1046 PUSH_DATA (push, 0);
1047 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1048 PUSH_DATA (push, 0x30);
1049 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1050 PUSH_DATA (push, 3);
1051 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1052 PUSH_DATA (push, 0x20);
1053 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1054 PUSH_DATA (push, 0x00);
1055 screen->save_state.patch_vertices = 3;
1056
1057 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1058 PUSH_DATA (push, 0);
1059 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1060 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1061
1062 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1063
1064 if (nvc0_screen_init_compute(screen))
1065 goto fail;
1066
1067 PUSH_KICK (push);
1068
1069 screen->tic.entries = CALLOC(4096, sizeof(void *));
1070 screen->tsc.entries = screen->tic.entries + 2048;
1071
1072 if (!nvc0_blitter_create(screen))
1073 goto fail;
1074
1075 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1076
1077 return &screen->base;
1078
1079 fail:
1080 screen->base.base.context_create = NULL;
1081 return &screen->base;
1082 }
1083
1084 int
1085 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1086 {
1087 int i = screen->tic.next;
1088
1089 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1090 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1091
1092 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1093
1094 if (screen->tic.entries[i])
1095 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1096
1097 screen->tic.entries[i] = entry;
1098 return i;
1099 }
1100
1101 int
1102 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1103 {
1104 int i = screen->tsc.next;
1105
1106 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1107 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1108
1109 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1110
1111 if (screen->tsc.entries[i])
1112 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1113
1114 screen->tsc.entries[i] = entry;
1115 return i;
1116 }