src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    const struct util_format_description *desc = util_format_description(format);
  49
  50    if (sample_count > 8)
  51       return false;
  52    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  53       return false;
  54
  55    /* Short-circuit the rest of the logic -- this is used by the state tracker
  56     * to determine valid MS levels in a no-attachments scenario.
  57     */
  58    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  59       return true;
  60
  61    if (!util_format_is_supported(format, bindings))
  62       return false;
  63
  64    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  65       if (util_format_get_blocksizebits(format) == 3 * 32)
  66          return false;
  67
  68    if (bindings & PIPE_BIND_LINEAR)
  69       if (util_format_is_depth_or_stencil(format) ||
  70           (target != PIPE_TEXTURE_1D &&
  71            target != PIPE_TEXTURE_2D &&
  72            target != PIPE_TEXTURE_RECT) ||
  73           sample_count > 1)
  74          return false;
  75
  76    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  77     */
  78    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  79         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  80        /* The claim is that this should work on GM107 but it doesn't. Need to
  81         * test further and figure out if it's a nouveau issue or a HW one.
  82        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  83         */
  84        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  85       return false;
  86
  87    /* transfers & shared are always supported */
  88    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  89                  PIPE_BIND_TRANSFER_WRITE |
  90                  PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    return (( nvc0_format_table[format].usage |
  94             nvc0_vertex_format[format].usage) & bindings) == bindings;
  95 }
  96
  97 static int
  98 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  99 {
 100    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 101    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 102
 103    switch (param) {
 104    /* non-boolean caps */
 105    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 106    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 107       return 15;
 108    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 109       return 12;
 110    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 111       return 2048;
 112    case PIPE_CAP_MIN_TEXEL_OFFSET:
 113       return -8;
 114    case PIPE_CAP_MAX_TEXEL_OFFSET:
 115       return 7;
 116    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 117       return -32;
 118    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 119       return 31;
 120    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 121       return 128 * 1024 * 1024;
 122    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 123       if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
 124          return 420;
 125       return 410;
 126    case PIPE_CAP_MAX_RENDER_TARGETS:
 127       return 8;
 128    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 129       return 1;
 130    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 131       return 4;
 132    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 133    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 134       return 128;
 135    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 136    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 137       return 1024;
 138    case PIPE_CAP_MAX_VERTEX_STREAMS:
 139       return 4;
 140    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 141       return 2048;
 142    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 143       return 256;
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145       return 16; /* 256 for binding as RT, but that's not possible in GL */
 146    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 147       return 16;
 148    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 149       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 150    case PIPE_CAP_MAX_VIEWPORTS:
 151       return NVC0_MAX_VIEWPORTS;
 152    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 153       return 4;
 154    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 155       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 156    case PIPE_CAP_ENDIANNESS:
 157       return PIPE_ENDIAN_LITTLE;
 158    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 159       return 30;
 160
 161    /* supported caps */
 162    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 163    case PIPE_CAP_TEXTURE_SWIZZLE:
 164    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 165    case PIPE_CAP_NPOT_TEXTURES:
 166    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 167    case PIPE_CAP_ANISOTROPIC_FILTER:
 168    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 169    case PIPE_CAP_CUBE_MAP_ARRAY:
 170    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 171    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 172    case PIPE_CAP_TWO_SIDED_STENCIL:
 173    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 174    case PIPE_CAP_POINT_SPRITE:
 175    case PIPE_CAP_TGSI_TEXCOORD:
 176    case PIPE_CAP_SM3:
 177    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 178    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 179    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 180    case PIPE_CAP_QUERY_TIMESTAMP:
 181    case PIPE_CAP_QUERY_TIME_ELAPSED:
 182    case PIPE_CAP_OCCLUSION_QUERY:
 183    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 184    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 185    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 186    case PIPE_CAP_INDEP_BLEND_ENABLE:
 187    case PIPE_CAP_INDEP_BLEND_FUNC:
 188    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 189    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 190    case PIPE_CAP_PRIMITIVE_RESTART:
 191    case PIPE_CAP_TGSI_INSTANCEID:
 192    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 193    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 194    case PIPE_CAP_CONDITIONAL_RENDER:
 195    case PIPE_CAP_TEXTURE_BARRIER:
 196    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 197    case PIPE_CAP_START_INSTANCE:
 198    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 199    case PIPE_CAP_DRAW_INDIRECT:
 200    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 201    case PIPE_CAP_USER_INDEX_BUFFERS:
 202    case PIPE_CAP_USER_VERTEX_BUFFERS:
 203    case PIPE_CAP_TEXTURE_QUERY_LOD:
 204    case PIPE_CAP_SAMPLE_SHADING:
 205    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 206    case PIPE_CAP_TEXTURE_GATHER_SM5:
 207    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 208    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 209    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 210    case PIPE_CAP_CLIP_HALFZ:
 211    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 212    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 213    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 214    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 215    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 216    case PIPE_CAP_TGSI_TXQS:
 217    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 218    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 219    case PIPE_CAP_SHAREABLE_SHADERS:
 220    case PIPE_CAP_CLEAR_TEXTURE:
 221    case PIPE_CAP_DRAW_PARAMETERS:
 222    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 223    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 224    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 225    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 226    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 227    case PIPE_CAP_INVALIDATE_BUFFER:
 228    case PIPE_CAP_STRING_MARKER:
 229    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 230       return 1;
 231    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 232       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 233    case PIPE_CAP_COMPUTE:
 234       return 1;
 235    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 236       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 237
 238    /* unsupported caps */
 239    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 240    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 241    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 242    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 243    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 244    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 245    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 246    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 247    case PIPE_CAP_FAKE_SW_MSAA:
 248    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 249    case PIPE_CAP_VERTEXID_NOBASE:
 250    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 251    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 252    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 253    case PIPE_CAP_GENERATE_MIPMAP:
 254    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 255    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 256    case PIPE_CAP_QUERY_MEMORY_INFO:
 257    case PIPE_CAP_PCI_GROUP:
 258    case PIPE_CAP_PCI_BUS:
 259    case PIPE_CAP_PCI_DEVICE:
 260    case PIPE_CAP_PCI_FUNCTION:
 261    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 262       return 0;
 263
 264    case PIPE_CAP_VENDOR_ID:
 265       return 0x10de;
 266    case PIPE_CAP_DEVICE_ID: {
 267       uint64_t device_id;
 268       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 269          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 270          return -1;
 271       }
 272       return device_id;
 273    }
 274    case PIPE_CAP_ACCELERATED:
 275       return 1;
 276    case PIPE_CAP_VIDEO_MEMORY:
 277       return dev->vram_size >> 20;
 278    case PIPE_CAP_UMA:
 279       return 0;
 280    }
 281
 282    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 283    return 0;
 284 }
 285
 286 static int
 287 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 288                              enum pipe_shader_cap param)
 289 {
 290    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 291
 292    switch (shader) {
 293    case PIPE_SHADER_VERTEX:
 294    case PIPE_SHADER_GEOMETRY:
 295    case PIPE_SHADER_FRAGMENT:
 296    case PIPE_SHADER_COMPUTE:
 297       break;
 298    case PIPE_SHADER_TESS_CTRL:
 299    case PIPE_SHADER_TESS_EVAL:
 300       if (class_3d >= GM107_3D_CLASS)
 301          return 0;
 302       break;
 303    default:
 304       return 0;
 305    }
 306
 307    switch (param) {
 308    case PIPE_SHADER_CAP_PREFERRED_IR:
 309       return PIPE_SHADER_IR_TGSI;
 310    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 311       return 1 << PIPE_SHADER_IR_TGSI;
 312    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 313    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 314    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 315    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 316       return 16384;
 317    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 318       return 16;
 319    case PIPE_SHADER_CAP_MAX_INPUTS:
 320       if (shader == PIPE_SHADER_VERTEX)
 321          return 32;
 322       /* NOTE: These only count our slots for GENERIC varyings.
 323        * The address space may be larger, but the actual hard limit seems to be
 324        * less than what the address space layout permits, so don't add TEXCOORD,
 325        * COLOR, etc. here.
 326        */
 327       if (shader == PIPE_SHADER_FRAGMENT)
 328          return 0x1f0 / 16;
 329       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 330        * and excludes 0x60 per-patch inputs.
 331        */
 332       return 0x200 / 16;
 333    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 334       return 32;
 335    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 336       return 65536;
 337    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 338       return NVC0_MAX_PIPE_CONSTBUFS;
 339    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 340       return shader != PIPE_SHADER_FRAGMENT;
 341    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 342       return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
 343    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 344    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 345       return 1;
 346    case PIPE_SHADER_CAP_MAX_PREDS:
 347       return 0;
 348    case PIPE_SHADER_CAP_MAX_TEMPS:
 349       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 350    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 351       return 1;
 352    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 353       return 1;
 354    case PIPE_SHADER_CAP_SUBROUTINES:
 355       return 1;
 356    case PIPE_SHADER_CAP_INTEGERS:
 357       return 1;
 358    case PIPE_SHADER_CAP_DOUBLES:
 359       return 1;
 360    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 361       return 1;
 362    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 363       return 1;
 364    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 365    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 366       return 0;
 367    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 368       return NVC0_MAX_BUFFERS;
 369    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 370       return 16; /* would be 32 in linked (OpenGL-style) mode */
 371    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 372       return 16; /* XXX not sure if more are really safe */
 373    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 374       return 32;
 375    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 376       if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
 377          return NVC0_MAX_IMAGES;
 378       return 0;
 379    default:
 380       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 381       return 0;
 382    }
 383 }
 384
 385 static float
 386 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 387 {
 388    switch (param) {
 389    case PIPE_CAPF_MAX_LINE_WIDTH:
 390    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 391       return 10.0f;
 392    case PIPE_CAPF_MAX_POINT_WIDTH:
 393       return 63.0f;
 394    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 395       return 63.375f;
 396    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 397       return 16.0f;
 398    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 399       return 15.0f;
 400    case PIPE_CAPF_GUARD_BAND_LEFT:
 401    case PIPE_CAPF_GUARD_BAND_TOP:
 402       return 0.0f;
 403    case PIPE_CAPF_GUARD_BAND_RIGHT:
 404    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 405       return 0.0f; /* that or infinity */
 406    }
 407
 408    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 409    return 0.0f;
 410 }
 411
 412 static int
 413 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 414                               enum pipe_shader_ir ir_type,
 415                               enum pipe_compute_cap param, void *data)
 416 {
 417    struct nvc0_screen *screen = nvc0_screen(pscreen);
 418    const uint16_t obj_class = screen->compute->oclass;
 419
 420 #define RET(x) do {                  \
 421    if (data)                         \
 422       memcpy(data, x, sizeof(x));    \
 423    return sizeof(x);                 \
 424 } while (0)
 425
 426    switch (param) {
 427    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 428       RET((uint64_t []) { 3 });
 429    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 430       if (obj_class >= NVE4_COMPUTE_CLASS) {
 431          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 432       } else {
 433          RET(((uint64_t []) { 65535, 65535, 65535 }));
 434       }
 435    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 436       RET(((uint64_t []) { 1024, 1024, 64 }));
 437    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 438       RET((uint64_t []) { 1024 });
 439    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 440       RET((uint64_t []) { 1ULL << 40 });
 441    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 442       switch (obj_class) {
 443       case GM200_COMPUTE_CLASS:
 444          RET((uint64_t []) { 96 << 10 });
 445          break;
 446       case GM107_COMPUTE_CLASS:
 447          RET((uint64_t []) { 64 << 10 });
 448          break;
 449       default:
 450          RET((uint64_t []) { 48 << 10 });
 451          break;
 452       }
 453    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 454       RET((uint64_t []) { 512 << 10 });
 455    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 456       RET((uint64_t []) { 4096 });
 457    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 458       RET((uint32_t []) { 32 });
 459    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 460       RET((uint64_t []) { 1ULL << 40 });
 461    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 462       RET((uint32_t []) { 0 });
 463    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 464       RET((uint32_t []) { screen->mp_count_compute });
 465    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 466       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 467    default:
 468       return 0;
 469    }
 470
 471 #undef RET
 472 }
 473
 474 static void
 475 nvc0_screen_destroy(struct pipe_screen *pscreen)
 476 {
 477    struct nvc0_screen *screen = nvc0_screen(pscreen);
 478
 479    if (!nouveau_drm_screen_unref(&screen->base))
 480       return;
 481
 482    if (screen->base.fence.current) {
 483       struct nouveau_fence *current = NULL;
 484
 485       /* nouveau_fence_wait will create a new current fence, so wait on the
 486        * _current_ one, and remove both.
 487        */
 488       nouveau_fence_ref(screen->base.fence.current, &current);
 489       nouveau_fence_wait(current, NULL);
 490       nouveau_fence_ref(NULL, &current);
 491       nouveau_fence_ref(NULL, &screen->base.fence.current);
 492    }
 493    if (screen->base.pushbuf)
 494       screen->base.pushbuf->user_priv = NULL;
 495
 496    if (screen->blitter)
 497       nvc0_blitter_destroy(screen);
 498    if (screen->pm.prog) {
 499       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 500       nvc0_program_destroy(NULL, screen->pm.prog);
 501       FREE(screen->pm.prog);
 502    }
 503
 504    nouveau_bo_ref(NULL, &screen->text);
 505    nouveau_bo_ref(NULL, &screen->uniform_bo);
 506    nouveau_bo_ref(NULL, &screen->tls);
 507    nouveau_bo_ref(NULL, &screen->txc);
 508    nouveau_bo_ref(NULL, &screen->fence.bo);
 509    nouveau_bo_ref(NULL, &screen->poly_cache);
 510
 511    nouveau_heap_destroy(&screen->lib_code);
 512    nouveau_heap_destroy(&screen->text_heap);
 513
 514    FREE(screen->tic.entries);
 515
 516    nouveau_object_del(&screen->eng3d);
 517    nouveau_object_del(&screen->eng2d);
 518    nouveau_object_del(&screen->m2mf);
 519    nouveau_object_del(&screen->compute);
 520    nouveau_object_del(&screen->nvsw);
 521
 522    nouveau_screen_fini(&screen->base);
 523
 524    FREE(screen);
 525 }
 526
 527 static int
 528 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 529                      unsigned size, const uint32_t *data)
 530 {
 531    struct nouveau_pushbuf *push = screen->base.pushbuf;
 532
 533    size /= 4;
 534
 535    assert((pos + size) <= 0x800);
 536
 537    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 538    PUSH_DATA (push, (m - 0x3800) / 8);
 539    PUSH_DATA (push, pos);
 540    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 541    PUSH_DATA (push, pos);
 542    PUSH_DATAp(push, data, size);
 543
 544    return pos + size;
 545 }
 546
 547 static void
 548 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 549 {
 550    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 551    PUSH_DATA (push, 0xff);
 552    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 553    PUSH_DATA (push, 0xff);
 554    PUSH_DATA (push, 0xff);
 555    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 556    PUSH_DATA (push, 0xff);
 557    PUSH_DATA (push, 0xff);
 558    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 559    PUSH_DATA (push, 0x3f);
 560
 561    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 562    PUSH_DATA (push, (3 << 16) | 3);
 563    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 564    PUSH_DATA (push, (2 << 16) | 2);
 565
 566    if (obj_class < GM107_3D_CLASS) {
 567       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 568       PUSH_DATA (push, 0);
 569    }
 570    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 571    PUSH_DATA (push, 0x10);
 572    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 573    PUSH_DATA (push, 0x10);
 574    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 575    PUSH_DATA (push, 0x10);
 576    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 577    PUSH_DATA (push, 0x10);
 578    PUSH_DATA (push, 0x10);
 579    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 580    PUSH_DATA (push, 0x10);
 581    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 582    PUSH_DATA (push, 0xe);
 583
 584    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 585    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 586    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 587    PUSH_DATA (push, 0);
 588    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 589    PUSH_DATA (push, 3);
 590
 591    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 592    PUSH_DATA (push, 0x3fffff);
 593    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 594    PUSH_DATA (push, 1);
 595    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 596    PUSH_DATA (push, 1);
 597
 598    if (obj_class < GM107_3D_CLASS) {
 599       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 600       PUSH_DATA (push, 3);
 601
 602       if (obj_class >= NVE4_3D_CLASS) {
 603          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 604          PUSH_DATA (push, 1);
 605       }
 606    }
 607
 608    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 609     * are supposed to do */
 610 }
 611
 612 static void
 613 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 614 {
 615    struct nvc0_screen *screen = nvc0_screen(pscreen);
 616    struct nouveau_pushbuf *push = screen->base.pushbuf;
 617
 618    /* we need to do it after possible flush in MARK_RING */
 619    *sequence = ++screen->base.fence.sequence;
 620
 621    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 622    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 623    PUSH_DATAh(push, screen->fence.bo->offset);
 624    PUSH_DATA (push, screen->fence.bo->offset);
 625    PUSH_DATA (push, *sequence);
 626    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 627               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 628 }
 629
 630 static u32
 631 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 632 {
 633    struct nvc0_screen *screen = nvc0_screen(pscreen);
 634    return screen->fence.map[0];
 635 }
 636
 637 static int
 638 nvc0_screen_init_compute(struct nvc0_screen *screen)
 639 {
 640    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 641
 642    switch (screen->base.device->chipset & ~0xf) {
 643    case 0xc0:
 644    case 0xd0:
 645       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 646    case 0xe0:
 647    case 0xf0:
 648    case 0x100:
 649    case 0x110:
 650    case 0x120:
 651       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 652    default:
 653       return -1;
 654    }
 655 }
 656
 657 bool
 658 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 659                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 660 {
 661    struct nouveau_bo *bo = NULL;
 662    int ret;
 663    uint64_t size = (lpos + lneg) * 32 + cstack;
 664
 665    if (size >= (1 << 20)) {
 666       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 667       return false;
 668    }
 669
 670    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 671    size  = align(size, 0x8000);
 672    size *= screen->mp_count;
 673
 674    size = align(size, 1 << 17);
 675
 676    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 677                         NULL, &bo);
 678    if (ret) {
 679       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 680       return false;
 681    }
 682    nouveau_bo_ref(NULL, &screen->tls);
 683    screen->tls = bo;
 684    return true;
 685 }
 686
 687 #define FAIL_SCREEN_INIT(str, err)                    \
 688    do {                                               \
 689       NOUVEAU_ERR(str, err);                          \
 690       goto fail;                                      \
 691    } while(0)
 692
 693 struct nouveau_screen *
 694 nvc0_screen_create(struct nouveau_device *dev)
 695 {
 696    struct nvc0_screen *screen;
 697    struct pipe_screen *pscreen;
 698    struct nouveau_object *chan;
 699    struct nouveau_pushbuf *push;
 700    uint64_t value;
 701    uint32_t obj_class;
 702    uint32_t flags;
 703    int ret;
 704    unsigned i;
 705
 706    switch (dev->chipset & ~0xf) {
 707    case 0xc0:
 708    case 0xd0:
 709    case 0xe0:
 710    case 0xf0:
 711    case 0x100:
 712    case 0x110:
 713    case 0x120:
 714       break;
 715    default:
 716       return NULL;
 717    }
 718
 719    screen = CALLOC_STRUCT(nvc0_screen);
 720    if (!screen)
 721       return NULL;
 722    pscreen = &screen->base.base;
 723    pscreen->destroy = nvc0_screen_destroy;
 724
 725    ret = nouveau_screen_init(&screen->base, dev);
 726    if (ret) {
 727       nvc0_screen_destroy(pscreen);
 728       return NULL;
 729    }
 730    chan = screen->base.channel;
 731    push = screen->base.pushbuf;
 732    push->user_priv = screen;
 733    push->rsvd_kick = 5;
 734
 735    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 736       PIPE_BIND_SHADER_BUFFER |
 737       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 738       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 739    screen->base.sysmem_bindings |=
 740       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 741
 742    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 743       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 744       screen->base.vidmem_bindings = 0;
 745    }
 746
 747    pscreen->context_create = nvc0_create;
 748    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 749    pscreen->get_param = nvc0_screen_get_param;
 750    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 751    pscreen->get_paramf = nvc0_screen_get_paramf;
 752    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 753    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 754
 755    nvc0_screen_init_resource_functions(pscreen);
 756
 757    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 758    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 759
 760    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 761    if (screen->base.drm->version >= 0x01000202)
 762       flags |= NOUVEAU_BO_COHERENT;
 763
 764    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 765    if (ret)
 766       goto fail;
 767    nouveau_bo_map(screen->fence.bo, 0, NULL);
 768    screen->fence.map = screen->fence.bo->map;
 769    screen->base.fence.emit = nvc0_screen_fence_emit;
 770    screen->base.fence.update = nvc0_screen_fence_update;
 771
 772
 773    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 774                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 775    if (ret)
 776       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 777
 778    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 779    PUSH_DATA (push, screen->nvsw->handle);
 780
 781    switch (dev->chipset & ~0xf) {
 782    case 0x120:
 783    case 0x110:
 784    case 0x100:
 785    case 0xf0:
 786       obj_class = NVF0_P2MF_CLASS;
 787       break;
 788    case 0xe0:
 789       obj_class = NVE4_P2MF_CLASS;
 790       break;
 791    default:
 792       obj_class = NVC0_M2MF_CLASS;
 793       break;
 794    }
 795    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 796                             &screen->m2mf);
 797    if (ret)
 798       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 799
 800    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 801    PUSH_DATA (push, screen->m2mf->oclass);
 802    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 803       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 804       PUSH_DATA (push, 0xa0b5);
 805    }
 806
 807    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 808                             &screen->eng2d);
 809    if (ret)
 810       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 811
 812    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 813    PUSH_DATA (push, screen->eng2d->oclass);
 814    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 815    PUSH_DATA (push, 0);
 816    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 817    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 818    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 819    PUSH_DATA (push, 0);
 820    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 821    PUSH_DATA (push, 0);
 822    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 823    PUSH_DATA (push, 0x3f);
 824    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 825    PUSH_DATA (push, 1);
 826    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 827    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 828
 829    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 830    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 831    PUSH_DATA (push, screen->fence.bo->offset + 16);
 832
 833    switch (dev->chipset & ~0xf) {
 834    case 0x120:
 835       obj_class = GM200_3D_CLASS;
 836       break;
 837    case 0x110:
 838       obj_class = GM107_3D_CLASS;
 839       break;
 840    case 0x100:
 841    case 0xf0:
 842       obj_class = NVF0_3D_CLASS;
 843       break;
 844    case 0xe0:
 845       switch (dev->chipset) {
 846       case 0xea:
 847          obj_class = NVEA_3D_CLASS;
 848          break;
 849       default:
 850          obj_class = NVE4_3D_CLASS;
 851          break;
 852       }
 853       break;
 854    case 0xd0:
 855       obj_class = NVC8_3D_CLASS;
 856       break;
 857    case 0xc0:
 858    default:
 859       switch (dev->chipset) {
 860       case 0xc8:
 861          obj_class = NVC8_3D_CLASS;
 862          break;
 863       case 0xc1:
 864          obj_class = NVC1_3D_CLASS;
 865          break;
 866       default:
 867          obj_class = NVC0_3D_CLASS;
 868          break;
 869       }
 870       break;
 871    }
 872    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 873                             &screen->eng3d);
 874    if (ret)
 875       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 876    screen->base.class_3d = obj_class;
 877
 878    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 879    PUSH_DATA (push, screen->eng3d->oclass);
 880
 881    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 882    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 883
 884    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 885       /* kill shaders after about 1 second (at 100 MHz) */
 886       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 887       PUSH_DATA (push, 0x17);
 888    }
 889
 890    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 891                     screen->base.drm->version >= 0x01000101);
 892    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 893    for (i = 0; i < 8; ++i)
 894            PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 895
 896    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 897    PUSH_DATA (push, 1);
 898
 899    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 900    PUSH_DATA (push, 0);
 901    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 902    PUSH_DATA (push, 0);
 903    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 904    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 905    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 906    PUSH_DATA (push, 0);
 907    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 908    PUSH_DATA (push, 1);
 909    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 910    PUSH_DATA (push, 1);
 911    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 912    PUSH_DATA (push, 1);
 913    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 914    PUSH_DATA (push, 0);
 915    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 916    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 917    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 918       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 919    } else {
 920       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 921       PUSH_DATA (push, 15);
 922    }
 923    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 924    PUSH_DATA (push, 8); /* 128 */
 925    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 926    PUSH_DATA (push, 1);
 927    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 928       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 929       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 930    }
 931
 932    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 933
 934    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
 935                         &screen->text);
 936    if (ret)
 937       goto fail;
 938
 939    /* XXX: getting a page fault at the end of the code buffer every few
 940     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 941     */
 942    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 943
 944    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
 945                         &screen->uniform_bo);
 946    if (ret)
 947       goto fail;
 948
 949    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
 950
 951    for (i = 0; i < 5; ++i) {
 952       /* TIC and TSC entries for each unit (nve4+ only) */
 953       /* auxiliary constants (6 user clip planes, base instance id) */
 954       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 955       PUSH_DATA (push, 2048);
 956       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 957       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 958       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 959       PUSH_DATA (push, (15 << 4) | 1);
 960       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 961          unsigned j;
 962          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 963          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
 964          for (j = 0; j < 8; ++j)
 965             PUSH_DATA(push, j);
 966       } else {
 967          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 968          PUSH_DATA (push, 0x54);
 969       }
 970    }
 971    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 972    PUSH_DATA (push, 0);
 973
 974    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 975    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 976    PUSH_DATA (push, 256);
 977    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 978    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 979    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 980    PUSH_DATA (push, 0);
 981    PUSH_DATAf(push, 0.0f);
 982    PUSH_DATAf(push, 0.0f);
 983    PUSH_DATAf(push, 0.0f);
 984    PUSH_DATAf(push, 0.0f);
 985    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 986    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 987    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 988
 989    if (screen->base.drm->version >= 0x01000101) {
 990       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 991       if (ret) {
 992          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 993          goto fail;
 994       }
 995    } else {
 996       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 997          value = (8 << 8) | 4;
 998       else
 999          value = (16 << 8) | 4;
1000    }
1001    screen->gpc_count = value & 0x000000ff;
1002    screen->mp_count = value >> 8;
1003    screen->mp_count_compute = screen->mp_count;
1004
1005    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1006
1007    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
1008    PUSH_DATAh(push, screen->text->offset);
1009    PUSH_DATA (push, screen->text->offset);
1010    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1011    PUSH_DATAh(push, screen->tls->offset);
1012    PUSH_DATA (push, screen->tls->offset);
1013    PUSH_DATA (push, screen->tls->size >> 32);
1014    PUSH_DATA (push, screen->tls->size);
1015    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1016    PUSH_DATA (push, 0);
1017    /* Reduce likelihood of collision with real buffers by placing the hole at
1018     * the top of the 4G area. This will have to be dealt with for real
1019     * eventually by blocking off that area from the VM.
1020     */
1021    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1022    PUSH_DATA (push, 0xff << 24);
1023
1024    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1025       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1026                            &screen->poly_cache);
1027       if (ret)
1028          goto fail;
1029
1030       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1031       PUSH_DATAh(push, screen->poly_cache->offset);
1032       PUSH_DATA (push, screen->poly_cache->offset);
1033       PUSH_DATA (push, 3);
1034    }
1035
1036    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1037                         &screen->txc);
1038    if (ret)
1039       goto fail;
1040
1041    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1042    PUSH_DATAh(push, screen->txc->offset);
1043    PUSH_DATA (push, screen->txc->offset);
1044    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1045    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1046       screen->tic.maxwell = true;
1047       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1048          screen->tic.maxwell =
1049             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1050          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1051       }
1052    }
1053
1054    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1055    PUSH_DATAh(push, screen->txc->offset + 65536);
1056    PUSH_DATA (push, screen->txc->offset + 65536);
1057    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1058
1059    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1060    PUSH_DATA (push, 0);
1061    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1062    PUSH_DATA (push, 0);
1063    PUSH_DATA (push, 0);
1064    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1065    PUSH_DATA (push, 0x3f);
1066
1067    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1068    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1069    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1070    for (i = 0; i < 8 * 2; ++i)
1071       PUSH_DATA(push, 0);
1072    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1073    PUSH_DATA (push, 0);
1074    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1075    PUSH_DATA (push, 0);
1076
1077    /* neither scissors, viewport nor stencil mask should affect clears */
1078    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1079    PUSH_DATA (push, 0);
1080
1081    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1082    PUSH_DATA (push, 1);
1083    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1084       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1085       PUSH_DATAf(push, 0.0f);
1086       PUSH_DATAf(push, 1.0f);
1087    }
1088    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1089    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1090
1091    /* We use scissors instead of exact view volume clipping,
1092     * so they're always enabled.
1093     */
1094    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1095       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1096       PUSH_DATA (push, 1);
1097       PUSH_DATA (push, 8192 << 16);
1098       PUSH_DATA (push, 8192 << 16);
1099    }
1100
1101 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1102
1103    i = 0;
1104    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1105    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1106    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1107    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1108    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1109    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1110    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1111    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1112    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1113    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1114    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1115    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1116    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1117
1118    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1119    PUSH_DATA (push, 1);
1120    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1121    PUSH_DATA (push, 1);
1122    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1123    PUSH_DATA (push, 0x40);
1124    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1125    PUSH_DATA (push, 0);
1126    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1127    PUSH_DATA (push, 0x30);
1128    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1129    PUSH_DATA (push, 3);
1130    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1131    PUSH_DATA (push, 0x20);
1132    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1133    PUSH_DATA (push, 0x00);
1134    screen->save_state.patch_vertices = 3;
1135
1136    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1137    PUSH_DATA (push, 0);
1138    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1139    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1140
1141    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1142
1143    if (nvc0_screen_init_compute(screen))
1144       goto fail;
1145
1146    PUSH_KICK (push);
1147
1148    screen->tic.entries = CALLOC(4096, sizeof(void *));
1149    screen->tsc.entries = screen->tic.entries + 2048;
1150
1151    if (!nvc0_blitter_create(screen))
1152       goto fail;
1153
1154    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1155
1156    return &screen->base;
1157
1158 fail:
1159    screen->base.base.context_create = NULL;
1160    return &screen->base;
1161 }
1162
1163 int
1164 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1165 {
1166    int i = screen->tic.next;
1167
1168    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1169       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1170
1171    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1172
1173    if (screen->tic.entries[i])
1174       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1175
1176    screen->tic.entries[i] = entry;
1177    return i;
1178 }
1179
1180 int
1181 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1182 {
1183    int i = screen->tsc.next;
1184
1185    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1186       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1187
1188    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1189
1190    if (screen->tsc.entries[i])
1191       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1192
1193    screen->tsc.entries[i] = entry;
1194    return i;
1195 }