src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    const struct util_format_description *desc = util_format_description(format);
  49
  50    if (sample_count > 8)
  51       return false;
  52    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  53       return false;
  54
  55    /* Short-circuit the rest of the logic -- this is used by the state tracker
  56     * to determine valid MS levels in a no-attachments scenario.
  57     */
  58    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  59       return true;
  60
  61    if (!util_format_is_supported(format, bindings))
  62       return false;
  63
  64    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  65       if (util_format_get_blocksizebits(format) == 3 * 32)
  66          return false;
  67
  68    if (bindings & PIPE_BIND_LINEAR)
  69       if (util_format_is_depth_or_stencil(format) ||
  70           (target != PIPE_TEXTURE_1D &&
  71            target != PIPE_TEXTURE_2D &&
  72            target != PIPE_TEXTURE_RECT) ||
  73           sample_count > 1)
  74          return false;
  75
  76    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  77     */
  78    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  79         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  80        /* The claim is that this should work on GM107 but it doesn't. Need to
  81         * test further and figure out if it's a nouveau issue or a HW one.
  82        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  83         */
  84        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  85       return false;
  86
  87    /* transfers & shared are always supported */
  88    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  89                  PIPE_BIND_TRANSFER_WRITE |
  90                  PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
  94        nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
  95       /* MS images are currently unsupported on Maxwell because they have to
  96        * be handled explicitly. */
  97       return false;
  98    }
  99
 100    return (( nvc0_format_table[format].usage |
 101             nvc0_vertex_format[format].usage) & bindings) == bindings;
 102 }
 103
 104 static int
 105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 106 {
 107    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 108    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 109
 110    switch (param) {
 111    /* non-boolean caps */
 112    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 113    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 114       return 15;
 115    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 116       return 12;
 117    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 118       return 2048;
 119    case PIPE_CAP_MIN_TEXEL_OFFSET:
 120       return -8;
 121    case PIPE_CAP_MAX_TEXEL_OFFSET:
 122       return 7;
 123    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 124       return -32;
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126       return 31;
 127    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 128       return 128 * 1024 * 1024;
 129    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 130       if (class_3d <= NVF0_3D_CLASS)
 131          return 430;
 132       return 410;
 133    case PIPE_CAP_MAX_RENDER_TARGETS:
 134       return 8;
 135    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 136       return 1;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 138       return 4;
 139    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 140    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 141       return 128;
 142    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 143    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 144       return 1024;
 145    case PIPE_CAP_MAX_VERTEX_STREAMS:
 146       return 4;
 147    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 148       return 2048;
 149    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 150       return 256;
 151    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 152       return 16; /* 256 for binding as RT, but that's not possible in GL */
 153    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 154       return 16;
 155    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 156       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 157    case PIPE_CAP_MAX_VIEWPORTS:
 158       return NVC0_MAX_VIEWPORTS;
 159    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 160       return 4;
 161    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 162       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 163    case PIPE_CAP_ENDIANNESS:
 164       return PIPE_ENDIAN_LITTLE;
 165    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 166       return 30;
 167    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 168       return NVC0_MAX_WINDOW_RECTANGLES;
 169
 170    /* supported caps */
 171    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 172    case PIPE_CAP_TEXTURE_SWIZZLE:
 173    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 174    case PIPE_CAP_NPOT_TEXTURES:
 175    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 176    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 177    case PIPE_CAP_ANISOTROPIC_FILTER:
 178    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 179    case PIPE_CAP_CUBE_MAP_ARRAY:
 180    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 181    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 182    case PIPE_CAP_TWO_SIDED_STENCIL:
 183    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 184    case PIPE_CAP_POINT_SPRITE:
 185    case PIPE_CAP_TGSI_TEXCOORD:
 186    case PIPE_CAP_SM3:
 187    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 188    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 189    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 190    case PIPE_CAP_QUERY_TIMESTAMP:
 191    case PIPE_CAP_QUERY_TIME_ELAPSED:
 192    case PIPE_CAP_OCCLUSION_QUERY:
 193    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 194    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 195    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 196    case PIPE_CAP_INDEP_BLEND_ENABLE:
 197    case PIPE_CAP_INDEP_BLEND_FUNC:
 198    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 199    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 200    case PIPE_CAP_PRIMITIVE_RESTART:
 201    case PIPE_CAP_TGSI_INSTANCEID:
 202    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 203    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 204    case PIPE_CAP_CONDITIONAL_RENDER:
 205    case PIPE_CAP_TEXTURE_BARRIER:
 206    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 207    case PIPE_CAP_START_INSTANCE:
 208    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 209    case PIPE_CAP_DRAW_INDIRECT:
 210    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 211    case PIPE_CAP_USER_INDEX_BUFFERS:
 212    case PIPE_CAP_USER_VERTEX_BUFFERS:
 213    case PIPE_CAP_TEXTURE_QUERY_LOD:
 214    case PIPE_CAP_SAMPLE_SHADING:
 215    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 216    case PIPE_CAP_TEXTURE_GATHER_SM5:
 217    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 218    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 219    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 220    case PIPE_CAP_CLIP_HALFZ:
 221    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 222    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 223    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 224    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 225    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 226    case PIPE_CAP_TGSI_TXQS:
 227    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 228    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 229    case PIPE_CAP_SHAREABLE_SHADERS:
 230    case PIPE_CAP_CLEAR_TEXTURE:
 231    case PIPE_CAP_DRAW_PARAMETERS:
 232    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 233    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 234    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 235    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 236    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 237    case PIPE_CAP_INVALIDATE_BUFFER:
 238    case PIPE_CAP_STRING_MARKER:
 239    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 240    case PIPE_CAP_CULL_DISTANCE:
 241    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 242    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 243    case PIPE_CAP_TGSI_VOTE:
 244    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 245       return 1;
 246    case PIPE_CAP_COMPUTE:
 247       return (class_3d < GP100_3D_CLASS);
 248    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 249       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 250    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 251       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 252
 253    /* unsupported caps */
 254    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 255    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 256    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 257    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 258    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 259    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 260    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 261    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 262    case PIPE_CAP_FAKE_SW_MSAA:
 263    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 264    case PIPE_CAP_VERTEXID_NOBASE:
 265    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 266    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 267    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 268    case PIPE_CAP_GENERATE_MIPMAP:
 269    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 270    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 271    case PIPE_CAP_QUERY_MEMORY_INFO:
 272    case PIPE_CAP_PCI_GROUP:
 273    case PIPE_CAP_PCI_BUS:
 274    case PIPE_CAP_PCI_DEVICE:
 275    case PIPE_CAP_PCI_FUNCTION:
 276    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 277       return 0;
 278
 279    case PIPE_CAP_VENDOR_ID:
 280       return 0x10de;
 281    case PIPE_CAP_DEVICE_ID: {
 282       uint64_t device_id;
 283       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 284          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 285          return -1;
 286       }
 287       return device_id;
 288    }
 289    case PIPE_CAP_ACCELERATED:
 290       return 1;
 291    case PIPE_CAP_VIDEO_MEMORY:
 292       return dev->vram_size >> 20;
 293    case PIPE_CAP_UMA:
 294       return 0;
 295    }
 296
 297    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 298    return 0;
 299 }
 300
 301 static int
 302 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 303                              enum pipe_shader_cap param)
 304 {
 305    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 306
 307    switch (shader) {
 308    case PIPE_SHADER_VERTEX:
 309    case PIPE_SHADER_GEOMETRY:
 310    case PIPE_SHADER_FRAGMENT:
 311    case PIPE_SHADER_COMPUTE:
 312    case PIPE_SHADER_TESS_CTRL:
 313    case PIPE_SHADER_TESS_EVAL:
 314       break;
 315    default:
 316       return 0;
 317    }
 318
 319    switch (param) {
 320    case PIPE_SHADER_CAP_PREFERRED_IR:
 321       return PIPE_SHADER_IR_TGSI;
 322    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 323       return 1 << PIPE_SHADER_IR_TGSI;
 324    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 325    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 326    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 327    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 328       return 16384;
 329    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 330       return 16;
 331    case PIPE_SHADER_CAP_MAX_INPUTS:
 332       if (shader == PIPE_SHADER_VERTEX)
 333          return 32;
 334       /* NOTE: These only count our slots for GENERIC varyings.
 335        * The address space may be larger, but the actual hard limit seems to be
 336        * less than what the address space layout permits, so don't add TEXCOORD,
 337        * COLOR, etc. here.
 338        */
 339       if (shader == PIPE_SHADER_FRAGMENT)
 340          return 0x1f0 / 16;
 341       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 342        * and excludes 0x60 per-patch inputs.
 343        */
 344       return 0x200 / 16;
 345    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 346       return 32;
 347    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 348       return 65536;
 349    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 350       return NVC0_MAX_PIPE_CONSTBUFS;
 351    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 352       return shader != PIPE_SHADER_FRAGMENT;
 353    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 354       return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
 355    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 356    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 357       return 1;
 358    case PIPE_SHADER_CAP_MAX_PREDS:
 359       return 0;
 360    case PIPE_SHADER_CAP_MAX_TEMPS:
 361       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 362    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 363       return 1;
 364    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 365       return 1;
 366    case PIPE_SHADER_CAP_SUBROUTINES:
 367       return 1;
 368    case PIPE_SHADER_CAP_INTEGERS:
 369       return 1;
 370    case PIPE_SHADER_CAP_DOUBLES:
 371       return 1;
 372    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 373       return 1;
 374    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 375       return 1;
 376    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 377    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 378       return 0;
 379    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 380       return NVC0_MAX_BUFFERS;
 381    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 382       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 383    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 384       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 385    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 386       return 32;
 387    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 388       if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
 389          return NVC0_MAX_IMAGES;
 390       if (class_3d < NVE4_3D_CLASS)
 391          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 392             return NVC0_MAX_IMAGES;
 393       return 0;
 394    default:
 395       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 396       return 0;
 397    }
 398 }
 399
 400 static float
 401 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 402 {
 403    switch (param) {
 404    case PIPE_CAPF_MAX_LINE_WIDTH:
 405    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 406       return 10.0f;
 407    case PIPE_CAPF_MAX_POINT_WIDTH:
 408       return 63.0f;
 409    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 410       return 63.375f;
 411    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 412       return 16.0f;
 413    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 414       return 15.0f;
 415    case PIPE_CAPF_GUARD_BAND_LEFT:
 416    case PIPE_CAPF_GUARD_BAND_TOP:
 417       return 0.0f;
 418    case PIPE_CAPF_GUARD_BAND_RIGHT:
 419    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 420       return 0.0f; /* that or infinity */
 421    }
 422
 423    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 424    return 0.0f;
 425 }
 426
 427 static int
 428 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 429                               enum pipe_shader_ir ir_type,
 430                               enum pipe_compute_cap param, void *data)
 431 {
 432    struct nvc0_screen *screen = nvc0_screen(pscreen);
 433    const uint16_t obj_class = screen->compute->oclass;
 434
 435 #define RET(x) do {                  \
 436    if (data)                         \
 437       memcpy(data, x, sizeof(x));    \
 438    return sizeof(x);                 \
 439 } while (0)
 440
 441    switch (param) {
 442    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 443       RET((uint64_t []) { 3 });
 444    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 445       if (obj_class >= NVE4_COMPUTE_CLASS) {
 446          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 447       } else {
 448          RET(((uint64_t []) { 65535, 65535, 65535 }));
 449       }
 450    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 451       RET(((uint64_t []) { 1024, 1024, 64 }));
 452    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 453       RET((uint64_t []) { 1024 });
 454    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 455       RET((uint64_t []) { 1ULL << 40 });
 456    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 457       switch (obj_class) {
 458       case GM200_COMPUTE_CLASS:
 459          RET((uint64_t []) { 96 << 10 });
 460          break;
 461       case GM107_COMPUTE_CLASS:
 462          RET((uint64_t []) { 64 << 10 });
 463          break;
 464       default:
 465          RET((uint64_t []) { 48 << 10 });
 466          break;
 467       }
 468    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 469       RET((uint64_t []) { 512 << 10 });
 470    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 471       RET((uint64_t []) { 4096 });
 472    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 473       RET((uint32_t []) { 32 });
 474    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 475       RET((uint64_t []) { 1ULL << 40 });
 476    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 477       RET((uint32_t []) { 0 });
 478    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 479       RET((uint32_t []) { screen->mp_count_compute });
 480    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 481       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 482    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 483       RET((uint32_t []) { 64 });
 484    default:
 485       return 0;
 486    }
 487
 488 #undef RET
 489 }
 490
 491 static void
 492 nvc0_screen_destroy(struct pipe_screen *pscreen)
 493 {
 494    struct nvc0_screen *screen = nvc0_screen(pscreen);
 495
 496    if (!nouveau_drm_screen_unref(&screen->base))
 497       return;
 498
 499    if (screen->base.fence.current) {
 500       struct nouveau_fence *current = NULL;
 501
 502       /* nouveau_fence_wait will create a new current fence, so wait on the
 503        * _current_ one, and remove both.
 504        */
 505       nouveau_fence_ref(screen->base.fence.current, &current);
 506       nouveau_fence_wait(current, NULL);
 507       nouveau_fence_ref(NULL, &current);
 508       nouveau_fence_ref(NULL, &screen->base.fence.current);
 509    }
 510    if (screen->base.pushbuf)
 511       screen->base.pushbuf->user_priv = NULL;
 512
 513    if (screen->blitter)
 514       nvc0_blitter_destroy(screen);
 515    if (screen->pm.prog) {
 516       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 517       nvc0_program_destroy(NULL, screen->pm.prog);
 518       FREE(screen->pm.prog);
 519    }
 520
 521    nouveau_bo_ref(NULL, &screen->text);
 522    nouveau_bo_ref(NULL, &screen->uniform_bo);
 523    nouveau_bo_ref(NULL, &screen->tls);
 524    nouveau_bo_ref(NULL, &screen->txc);
 525    nouveau_bo_ref(NULL, &screen->fence.bo);
 526    nouveau_bo_ref(NULL, &screen->poly_cache);
 527
 528    nouveau_heap_destroy(&screen->lib_code);
 529    nouveau_heap_destroy(&screen->text_heap);
 530
 531    FREE(screen->tic.entries);
 532
 533    nouveau_object_del(&screen->eng3d);
 534    nouveau_object_del(&screen->eng2d);
 535    nouveau_object_del(&screen->m2mf);
 536    nouveau_object_del(&screen->compute);
 537    nouveau_object_del(&screen->nvsw);
 538
 539    nouveau_screen_fini(&screen->base);
 540
 541    FREE(screen);
 542 }
 543
 544 static int
 545 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 546                      unsigned size, const uint32_t *data)
 547 {
 548    struct nouveau_pushbuf *push = screen->base.pushbuf;
 549
 550    size /= 4;
 551
 552    assert((pos + size) <= 0x800);
 553
 554    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 555    PUSH_DATA (push, (m - 0x3800) / 8);
 556    PUSH_DATA (push, pos);
 557    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 558    PUSH_DATA (push, pos);
 559    PUSH_DATAp(push, data, size);
 560
 561    return pos + size;
 562 }
 563
 564 static void
 565 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 566 {
 567    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 568    PUSH_DATA (push, 0xff);
 569    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 570    PUSH_DATA (push, 0xff);
 571    PUSH_DATA (push, 0xff);
 572    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 573    PUSH_DATA (push, 0xff);
 574    PUSH_DATA (push, 0xff);
 575    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 576    PUSH_DATA (push, 0x3f);
 577
 578    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 579    PUSH_DATA (push, (3 << 16) | 3);
 580    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 581    PUSH_DATA (push, (2 << 16) | 2);
 582
 583    if (obj_class < GM107_3D_CLASS) {
 584       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 585       PUSH_DATA (push, 0);
 586    }
 587    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 588    PUSH_DATA (push, 0x10);
 589    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 590    PUSH_DATA (push, 0x10);
 591    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 592    PUSH_DATA (push, 0x10);
 593    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 594    PUSH_DATA (push, 0x10);
 595    PUSH_DATA (push, 0x10);
 596    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 597    PUSH_DATA (push, 0x10);
 598    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 599    PUSH_DATA (push, 0xe);
 600
 601    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 602    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 603    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 604    PUSH_DATA (push, 0);
 605    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 606    PUSH_DATA (push, 3);
 607
 608    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 609    PUSH_DATA (push, 0x3fffff);
 610    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 611    PUSH_DATA (push, 1);
 612    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 613    PUSH_DATA (push, 1);
 614
 615    if (obj_class < GM107_3D_CLASS) {
 616       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 617       PUSH_DATA (push, 3);
 618
 619       if (obj_class >= NVE4_3D_CLASS) {
 620          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 621          PUSH_DATA (push, 1);
 622       }
 623    }
 624
 625    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 626     * are supposed to do */
 627 }
 628
 629 static void
 630 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 631 {
 632    struct nvc0_screen *screen = nvc0_screen(pscreen);
 633    struct nouveau_pushbuf *push = screen->base.pushbuf;
 634
 635    /* we need to do it after possible flush in MARK_RING */
 636    *sequence = ++screen->base.fence.sequence;
 637
 638    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 639    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 640    PUSH_DATAh(push, screen->fence.bo->offset);
 641    PUSH_DATA (push, screen->fence.bo->offset);
 642    PUSH_DATA (push, *sequence);
 643    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 644               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 645 }
 646
 647 static u32
 648 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 649 {
 650    struct nvc0_screen *screen = nvc0_screen(pscreen);
 651    return screen->fence.map[0];
 652 }
 653
 654 static int
 655 nvc0_screen_init_compute(struct nvc0_screen *screen)
 656 {
 657    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 658
 659    switch (screen->base.device->chipset & ~0xf) {
 660    case 0xc0:
 661    case 0xd0:
 662       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 663    case 0xe0:
 664    case 0xf0:
 665    case 0x100:
 666    case 0x110:
 667    case 0x120:
 668       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 669    case 0x130:
 670       return 0;
 671    default:
 672       return -1;
 673    }
 674 }
 675
 676 static int
 677 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 678                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 679 {
 680    struct nouveau_bo *bo = NULL;
 681    int ret;
 682    uint64_t size = (lpos + lneg) * 32 + cstack;
 683
 684    if (size >= (1 << 20)) {
 685       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 686       return -1;
 687    }
 688
 689    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 690    size  = align(size, 0x8000);
 691    size *= screen->mp_count;
 692
 693    size = align(size, 1 << 17);
 694
 695    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 696                         NULL, &bo);
 697    if (ret)
 698       return ret;
 699    nouveau_bo_ref(NULL, &screen->tls);
 700    screen->tls = bo;
 701    return 0;
 702 }
 703
 704 int
 705 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 706 {
 707    struct nouveau_pushbuf *push = screen->base.pushbuf;
 708    struct nouveau_bo *bo;
 709    int ret;
 710
 711    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 712                         1 << 17, size, NULL, &bo);
 713    if (ret)
 714       return ret;
 715
 716    nouveau_bo_ref(NULL, &screen->text);
 717    screen->text = bo;
 718
 719    nouveau_heap_destroy(&screen->lib_code);
 720    nouveau_heap_destroy(&screen->text_heap);
 721
 722    /* XXX: getting a page fault at the end of the code buffer every few
 723     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 724     */
 725    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 726
 727    /* update the code segment setup */
 728    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 729    PUSH_DATAh(push, screen->text->offset);
 730    PUSH_DATA (push, screen->text->offset);
 731    if (screen->compute) {
 732       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 733       PUSH_DATAh(push, screen->text->offset);
 734       PUSH_DATA (push, screen->text->offset);
 735    }
 736
 737    return 0;
 738 }
 739
 740 #define FAIL_SCREEN_INIT(str, err)                    \
 741    do {                                               \
 742       NOUVEAU_ERR(str, err);                          \
 743       goto fail;                                      \
 744    } while(0)
 745
 746 struct nouveau_screen *
 747 nvc0_screen_create(struct nouveau_device *dev)
 748 {
 749    struct nvc0_screen *screen;
 750    struct pipe_screen *pscreen;
 751    struct nouveau_object *chan;
 752    struct nouveau_pushbuf *push;
 753    uint64_t value;
 754    uint32_t obj_class;
 755    uint32_t flags;
 756    int ret;
 757    unsigned i;
 758
 759    switch (dev->chipset & ~0xf) {
 760    case 0xc0:
 761    case 0xd0:
 762    case 0xe0:
 763    case 0xf0:
 764    case 0x100:
 765    case 0x110:
 766    case 0x120:
 767    case 0x130:
 768       break;
 769    default:
 770       return NULL;
 771    }
 772
 773    screen = CALLOC_STRUCT(nvc0_screen);
 774    if (!screen)
 775       return NULL;
 776    pscreen = &screen->base.base;
 777    pscreen->destroy = nvc0_screen_destroy;
 778
 779    ret = nouveau_screen_init(&screen->base, dev);
 780    if (ret)
 781       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 782    chan = screen->base.channel;
 783    push = screen->base.pushbuf;
 784    push->user_priv = screen;
 785    push->rsvd_kick = 5;
 786
 787    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 788       PIPE_BIND_SHADER_BUFFER |
 789       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 790       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 791    screen->base.sysmem_bindings |=
 792       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 793
 794    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 795       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 796       screen->base.vidmem_bindings = 0;
 797    }
 798
 799    pscreen->context_create = nvc0_create;
 800    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 801    pscreen->get_param = nvc0_screen_get_param;
 802    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 803    pscreen->get_paramf = nvc0_screen_get_paramf;
 804    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 805    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 806
 807    nvc0_screen_init_resource_functions(pscreen);
 808
 809    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 810    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 811
 812    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 813    if (screen->base.drm->version >= 0x01000202)
 814       flags |= NOUVEAU_BO_COHERENT;
 815
 816    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 817    if (ret)
 818       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 819    nouveau_bo_map(screen->fence.bo, 0, NULL);
 820    screen->fence.map = screen->fence.bo->map;
 821    screen->base.fence.emit = nvc0_screen_fence_emit;
 822    screen->base.fence.update = nvc0_screen_fence_update;
 823
 824
 825    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 826                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 827    if (ret)
 828       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 829
 830    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 831    PUSH_DATA (push, screen->nvsw->handle);
 832
 833    switch (dev->chipset & ~0xf) {
 834    case 0x130:
 835    case 0x120:
 836    case 0x110:
 837    case 0x100:
 838    case 0xf0:
 839       obj_class = NVF0_P2MF_CLASS;
 840       break;
 841    case 0xe0:
 842       obj_class = NVE4_P2MF_CLASS;
 843       break;
 844    default:
 845       obj_class = NVC0_M2MF_CLASS;
 846       break;
 847    }
 848    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 849                             &screen->m2mf);
 850    if (ret)
 851       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 852
 853    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 854    PUSH_DATA (push, screen->m2mf->oclass);
 855    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 856       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 857       PUSH_DATA (push, 0xa0b5);
 858    }
 859
 860    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 861                             &screen->eng2d);
 862    if (ret)
 863       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 864
 865    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 866    PUSH_DATA (push, screen->eng2d->oclass);
 867    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 868    PUSH_DATA (push, 0);
 869    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 870    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 871    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 872    PUSH_DATA (push, 0);
 873    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 874    PUSH_DATA (push, 0);
 875    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 876    PUSH_DATA (push, 0x3f);
 877    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 878    PUSH_DATA (push, 1);
 879    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 880    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 881
 882    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 883    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 884    PUSH_DATA (push, screen->fence.bo->offset + 16);
 885
 886    switch (dev->chipset & ~0xf) {
 887    case 0x130:
 888       obj_class = GP100_3D_CLASS;
 889       break;
 890    case 0x120:
 891       obj_class = GM200_3D_CLASS;
 892       break;
 893    case 0x110:
 894       obj_class = GM107_3D_CLASS;
 895       break;
 896    case 0x100:
 897    case 0xf0:
 898       obj_class = NVF0_3D_CLASS;
 899       break;
 900    case 0xe0:
 901       switch (dev->chipset) {
 902       case 0xea:
 903          obj_class = NVEA_3D_CLASS;
 904          break;
 905       default:
 906          obj_class = NVE4_3D_CLASS;
 907          break;
 908       }
 909       break;
 910    case 0xd0:
 911       obj_class = NVC8_3D_CLASS;
 912       break;
 913    case 0xc0:
 914    default:
 915       switch (dev->chipset) {
 916       case 0xc8:
 917          obj_class = NVC8_3D_CLASS;
 918          break;
 919       case 0xc1:
 920          obj_class = NVC1_3D_CLASS;
 921          break;
 922       default:
 923          obj_class = NVC0_3D_CLASS;
 924          break;
 925       }
 926       break;
 927    }
 928    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 929                             &screen->eng3d);
 930    if (ret)
 931       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 932    screen->base.class_3d = obj_class;
 933
 934    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 935    PUSH_DATA (push, screen->eng3d->oclass);
 936
 937    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 938    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 939
 940    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 941       /* kill shaders after about 1 second (at 100 MHz) */
 942       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 943       PUSH_DATA (push, 0x17);
 944    }
 945
 946    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 947                     screen->base.drm->version >= 0x01000101);
 948    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 949    for (i = 0; i < 8; ++i)
 950       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 951
 952    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 953    PUSH_DATA (push, 1);
 954
 955    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 956    PUSH_DATA (push, 0);
 957    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 958    PUSH_DATA (push, 0);
 959    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 960    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 961    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 962    PUSH_DATA (push, 0);
 963    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 964    PUSH_DATA (push, 1);
 965    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 966    PUSH_DATA (push, 1);
 967    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 968    PUSH_DATA (push, 1);
 969    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 970    PUSH_DATA (push, 0);
 971    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 972    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 973    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 974       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 975    } else {
 976       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 977       PUSH_DATA (push, 15);
 978    }
 979    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 980    PUSH_DATA (push, 8); /* 128 */
 981    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 982    PUSH_DATA (push, 1);
 983    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 984       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 985       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 986    }
 987
 988    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 989
 990    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
 991    if (ret)
 992       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
 993
 994    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
 995                         &screen->uniform_bo);
 996    if (ret)
 997       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
 998
 999    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1000
1001    for (i = 0; i < 5; ++i) {
1002       /* TIC and TSC entries for each unit (nve4+ only) */
1003       /* auxiliary constants (6 user clip planes, base instance id) */
1004       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1005       PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1006       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1007       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1008       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1009       PUSH_DATA (push, (15 << 4) | 1);
1010       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1011          unsigned j;
1012          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1013          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1014          for (j = 0; j < 8; ++j)
1015             PUSH_DATA(push, j);
1016       } else {
1017          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1018          PUSH_DATA (push, 0x54);
1019       }
1020
1021       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1022       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1023       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1024       PUSH_DATA (push, 0); /* 0 */
1025       PUSH_DATA (push, 0);
1026       PUSH_DATA (push, 1); /* 1 */
1027       PUSH_DATA (push, 0);
1028       PUSH_DATA (push, 0); /* 2 */
1029       PUSH_DATA (push, 1);
1030       PUSH_DATA (push, 1); /* 3 */
1031       PUSH_DATA (push, 1);
1032       PUSH_DATA (push, 2); /* 4 */
1033       PUSH_DATA (push, 0);
1034       PUSH_DATA (push, 3); /* 5 */
1035       PUSH_DATA (push, 0);
1036       PUSH_DATA (push, 2); /* 6 */
1037       PUSH_DATA (push, 1);
1038       PUSH_DATA (push, 3); /* 7 */
1039       PUSH_DATA (push, 1);
1040    }
1041    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1042    PUSH_DATA (push, 0);
1043
1044    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1045    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1046    PUSH_DATA (push, 256);
1047    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1048    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1049    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1050    PUSH_DATA (push, 0);
1051    PUSH_DATAf(push, 0.0f);
1052    PUSH_DATAf(push, 0.0f);
1053    PUSH_DATAf(push, 0.0f);
1054    PUSH_DATAf(push, 0.0f);
1055    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1056    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1057    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1058
1059    if (screen->base.drm->version >= 0x01000101) {
1060       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1061       if (ret)
1062          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1063    } else {
1064       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1065          value = (8 << 8) | 4;
1066       else
1067          value = (16 << 8) | 4;
1068    }
1069    screen->gpc_count = value & 0x000000ff;
1070    screen->mp_count = value >> 8;
1071    screen->mp_count_compute = screen->mp_count;
1072
1073    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1074    if (ret)
1075       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1076
1077    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1078    PUSH_DATAh(push, screen->tls->offset);
1079    PUSH_DATA (push, screen->tls->offset);
1080    PUSH_DATA (push, screen->tls->size >> 32);
1081    PUSH_DATA (push, screen->tls->size);
1082    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1083    PUSH_DATA (push, 0);
1084    /* Reduce likelihood of collision with real buffers by placing the hole at
1085     * the top of the 4G area. This will have to be dealt with for real
1086     * eventually by blocking off that area from the VM.
1087     */
1088    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1089    PUSH_DATA (push, 0xff << 24);
1090
1091    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1092       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1093                            &screen->poly_cache);
1094       if (ret)
1095          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1096
1097       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1098       PUSH_DATAh(push, screen->poly_cache->offset);
1099       PUSH_DATA (push, screen->poly_cache->offset);
1100       PUSH_DATA (push, 3);
1101    }
1102
1103    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1104                         &screen->txc);
1105    if (ret)
1106       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1107
1108    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1109    PUSH_DATAh(push, screen->txc->offset);
1110    PUSH_DATA (push, screen->txc->offset);
1111    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1112    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1113       screen->tic.maxwell = true;
1114       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1115          screen->tic.maxwell =
1116             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1117          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1118       }
1119    }
1120
1121    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1122    PUSH_DATAh(push, screen->txc->offset + 65536);
1123    PUSH_DATA (push, screen->txc->offset + 65536);
1124    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1125
1126    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1127    PUSH_DATA (push, 0);
1128    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1129    PUSH_DATA (push, 0);
1130    PUSH_DATA (push, 0);
1131    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1132    PUSH_DATA (push, 0x3f);
1133
1134    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1135    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1136    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1137    for (i = 0; i < 8 * 2; ++i)
1138       PUSH_DATA(push, 0);
1139    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1140    PUSH_DATA (push, 0);
1141    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1142    PUSH_DATA (push, 0);
1143
1144    /* neither scissors, viewport nor stencil mask should affect clears */
1145    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1146    PUSH_DATA (push, 0);
1147
1148    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1149    PUSH_DATA (push, 1);
1150    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1151       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1152       PUSH_DATAf(push, 0.0f);
1153       PUSH_DATAf(push, 1.0f);
1154    }
1155    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1156    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1157
1158    /* We use scissors instead of exact view volume clipping,
1159     * so they're always enabled.
1160     */
1161    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1162       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1163       PUSH_DATA (push, 1);
1164       PUSH_DATA (push, 8192 << 16);
1165       PUSH_DATA (push, 8192 << 16);
1166    }
1167
1168 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1169
1170    i = 0;
1171    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1172    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1173    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1174    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1175    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1176    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1177    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1178    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1179    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1180    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1181    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1182    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1183    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1184
1185    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1186    PUSH_DATA (push, 1);
1187    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1188    PUSH_DATA (push, 1);
1189    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1190    PUSH_DATA (push, 0x40);
1191    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1192    PUSH_DATA (push, 0);
1193    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1194    PUSH_DATA (push, 0x30);
1195    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1196    PUSH_DATA (push, 3);
1197    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1198    PUSH_DATA (push, 0x20);
1199    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1200    PUSH_DATA (push, 0x00);
1201    screen->save_state.patch_vertices = 3;
1202
1203    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1204    PUSH_DATA (push, 0);
1205    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1206    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1207
1208    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1209
1210    if (nvc0_screen_init_compute(screen))
1211       goto fail;
1212
1213    PUSH_KICK (push);
1214
1215    screen->tic.entries = CALLOC(4096, sizeof(void *));
1216    screen->tsc.entries = screen->tic.entries + 2048;
1217
1218    if (!nvc0_blitter_create(screen))
1219       goto fail;
1220
1221    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1222
1223    return &screen->base;
1224
1225 fail:
1226    screen->base.base.context_create = NULL;
1227    return &screen->base;
1228 }
1229
1230 int
1231 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1232 {
1233    int i = screen->tic.next;
1234
1235    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1236       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1237
1238    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1239
1240    if (screen->tic.entries[i])
1241       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1242
1243    screen->tic.entries[i] = entry;
1244    return i;
1245 }
1246
1247 int
1248 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1249 {
1250    int i = screen->tsc.next;
1251
1252    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1253       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1254
1255    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1256
1257    if (screen->tsc.entries[i])
1258       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1259
1260    screen->tsc.entries[i] = entry;
1261    return i;
1262 }