2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
30 #include "nouveau_vp3_video.h"
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
35 #include "nvc0/mme/com9097.mme.h"
36 #include "nvc0/mme/com90c0.mme.h"
38 #include "nv50/g80_texture.xml.h"
41 nvc0_screen_is_format_supported(struct pipe_screen
*pscreen
,
42 enum pipe_format format
,
43 enum pipe_texture_target target
,
44 unsigned sample_count
,
47 const struct util_format_description
*desc
= util_format_description(format
);
51 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
54 /* Short-circuit the rest of the logic -- this is used by the state tracker
55 * to determine valid MS levels in a no-attachments scenario.
57 if (format
== PIPE_FORMAT_NONE
&& bindings
& PIPE_BIND_RENDER_TARGET
)
60 if ((bindings
& PIPE_BIND_SAMPLER_VIEW
) && (target
!= PIPE_BUFFER
))
61 if (util_format_get_blocksizebits(format
) == 3 * 32)
64 if (bindings
& PIPE_BIND_LINEAR
)
65 if (util_format_is_depth_or_stencil(format
) ||
66 (target
!= PIPE_TEXTURE_1D
&&
67 target
!= PIPE_TEXTURE_2D
&&
68 target
!= PIPE_TEXTURE_RECT
) ||
72 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
74 if ((desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
||
75 desc
->layout
== UTIL_FORMAT_LAYOUT_ASTC
) &&
76 /* The claim is that this should work on GM107 but it doesn't. Need to
77 * test further and figure out if it's a nouveau issue or a HW one.
78 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
80 nouveau_screen(pscreen
)->class_3d
!= NVEA_3D_CLASS
)
83 /* shared is always supported */
84 bindings
&= ~(PIPE_BIND_LINEAR
|
87 if (bindings
& PIPE_BIND_SHADER_IMAGE
) {
88 if (format
== PIPE_FORMAT_B8G8R8A8_UNORM
&&
89 nouveau_screen(pscreen
)->class_3d
< NVE4_3D_CLASS
) {
90 /* This should work on Fermi, but for currently unknown reasons it
91 * does not and results in breaking reads from pbos. */
96 return (( nvc0_format_table
[format
].usage
|
97 nvc0_vertex_format
[format
].usage
) & bindings
) == bindings
;
101 nvc0_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
103 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
104 struct nouveau_device
*dev
= nouveau_screen(pscreen
)->device
;
107 /* non-boolean caps */
108 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
109 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
111 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
113 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
115 case PIPE_CAP_MIN_TEXEL_OFFSET
:
117 case PIPE_CAP_MAX_TEXEL_OFFSET
:
119 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
121 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
123 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
124 return 128 * 1024 * 1024;
125 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
127 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
129 case PIPE_CAP_MAX_RENDER_TARGETS
:
131 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
133 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
135 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
136 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
138 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
139 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
141 case PIPE_CAP_MAX_VERTEX_STREAMS
:
143 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
145 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
147 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
148 if (class_3d
< GM107_3D_CLASS
)
149 return 256; /* IMAGE bindings require alignment to 256 */
151 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
153 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
154 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
155 case PIPE_CAP_MAX_VIEWPORTS
:
156 return NVC0_MAX_VIEWPORTS
;
157 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
159 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
160 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50
;
161 case PIPE_CAP_ENDIANNESS
:
162 return PIPE_ENDIAN_LITTLE
;
163 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
165 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
166 return NVC0_MAX_WINDOW_RECTANGLES
;
167 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
168 return class_3d
>= GM200_3D_CLASS
? 8 : 0;
171 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
172 case PIPE_CAP_TEXTURE_SWIZZLE
:
173 case PIPE_CAP_NPOT_TEXTURES
:
174 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
175 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
176 case PIPE_CAP_ANISOTROPIC_FILTER
:
177 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
178 case PIPE_CAP_CUBE_MAP_ARRAY
:
179 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
180 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
181 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
182 case PIPE_CAP_POINT_SPRITE
:
183 case PIPE_CAP_TGSI_TEXCOORD
:
185 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
186 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
187 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
188 case PIPE_CAP_QUERY_TIMESTAMP
:
189 case PIPE_CAP_QUERY_TIME_ELAPSED
:
190 case PIPE_CAP_OCCLUSION_QUERY
:
191 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
192 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
193 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
194 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
195 case PIPE_CAP_INDEP_BLEND_ENABLE
:
196 case PIPE_CAP_INDEP_BLEND_FUNC
:
197 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
198 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
199 case PIPE_CAP_PRIMITIVE_RESTART
:
200 case PIPE_CAP_TGSI_INSTANCEID
:
201 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
202 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
203 case PIPE_CAP_CONDITIONAL_RENDER
:
204 case PIPE_CAP_TEXTURE_BARRIER
:
205 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
206 case PIPE_CAP_START_INSTANCE
:
207 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
208 case PIPE_CAP_DRAW_INDIRECT
:
209 case PIPE_CAP_USER_VERTEX_BUFFERS
:
210 case PIPE_CAP_TEXTURE_QUERY_LOD
:
211 case PIPE_CAP_SAMPLE_SHADING
:
212 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
213 case PIPE_CAP_TEXTURE_GATHER_SM5
:
214 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
215 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
216 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
217 case PIPE_CAP_CLIP_HALFZ
:
218 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
219 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
220 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
221 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
222 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
223 case PIPE_CAP_TGSI_TXQS
:
224 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
225 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
226 case PIPE_CAP_SHAREABLE_SHADERS
:
227 case PIPE_CAP_CLEAR_TEXTURE
:
228 case PIPE_CAP_DRAW_PARAMETERS
:
229 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
230 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
231 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
232 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
233 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
234 case PIPE_CAP_INVALIDATE_BUFFER
:
235 case PIPE_CAP_STRING_MARKER
:
236 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
237 case PIPE_CAP_CULL_DISTANCE
:
238 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
239 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
240 case PIPE_CAP_TGSI_VOTE
:
241 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
242 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
243 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
244 case PIPE_CAP_DOUBLES
:
246 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
247 case PIPE_CAP_TGSI_CLOCK
:
248 case PIPE_CAP_COMPUTE
:
249 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
250 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
251 case PIPE_CAP_QUERY_SO_OVERFLOW
:
253 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
254 return nouveau_screen(pscreen
)->vram_domain
& NOUVEAU_BO_VRAM
? 1 : 0;
255 case PIPE_CAP_TGSI_FS_FBFETCH
:
256 return class_3d
>= NVE4_3D_CLASS
; /* needs testing on fermi */
257 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
258 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
259 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
260 case PIPE_CAP_POST_DEPTH_COVERAGE
:
261 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
262 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
263 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
264 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
265 return class_3d
>= GM200_3D_CLASS
;
266 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
267 return class_3d
>= GP100_3D_CLASS
;
268 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
269 case PIPE_CAP_TGSI_BALLOT
:
270 case PIPE_CAP_BINDLESS_TEXTURE
:
271 return class_3d
>= NVE4_3D_CLASS
;
273 /* unsupported caps */
274 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
275 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
276 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
277 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
278 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
279 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
280 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
281 case PIPE_CAP_FAKE_SW_MSAA
:
282 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
283 case PIPE_CAP_VERTEXID_NOBASE
:
284 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
285 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
286 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
287 case PIPE_CAP_GENERATE_MIPMAP
:
288 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
289 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
290 case PIPE_CAP_QUERY_MEMORY_INFO
:
291 case PIPE_CAP_PCI_GROUP
:
292 case PIPE_CAP_PCI_BUS
:
293 case PIPE_CAP_PCI_DEVICE
:
294 case PIPE_CAP_PCI_FUNCTION
:
295 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
296 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
297 case PIPE_CAP_NATIVE_FENCE_FD
:
298 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
299 case PIPE_CAP_INT64_DIVMOD
:
300 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
301 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
302 case PIPE_CAP_MEMOBJ
:
303 case PIPE_CAP_LOAD_CONSTBUF
:
304 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
305 case PIPE_CAP_TILE_RASTER_ORDER
:
306 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
307 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
308 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
309 case PIPE_CAP_FENCE_SIGNAL
:
310 case PIPE_CAP_CONSTBUF0_FLAGS
:
311 case PIPE_CAP_PACKED_UNIFORMS
:
312 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
315 case PIPE_CAP_VENDOR_ID
:
317 case PIPE_CAP_DEVICE_ID
: {
319 if (nouveau_getparam(dev
, NOUVEAU_GETPARAM_PCI_DEVICE
, &device_id
)) {
320 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
325 case PIPE_CAP_ACCELERATED
:
327 case PIPE_CAP_VIDEO_MEMORY
:
328 return dev
->vram_size
>> 20;
333 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
338 nvc0_screen_get_shader_param(struct pipe_screen
*pscreen
,
339 enum pipe_shader_type shader
,
340 enum pipe_shader_cap param
)
342 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
345 case PIPE_SHADER_VERTEX
:
346 case PIPE_SHADER_GEOMETRY
:
347 case PIPE_SHADER_FRAGMENT
:
348 case PIPE_SHADER_COMPUTE
:
349 case PIPE_SHADER_TESS_CTRL
:
350 case PIPE_SHADER_TESS_EVAL
:
357 case PIPE_SHADER_CAP_PREFERRED_IR
:
358 return PIPE_SHADER_IR_TGSI
;
359 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
360 return 1 << PIPE_SHADER_IR_TGSI
;
361 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
362 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
363 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
364 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
366 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
368 case PIPE_SHADER_CAP_MAX_INPUTS
:
369 if (shader
== PIPE_SHADER_VERTEX
)
371 /* NOTE: These only count our slots for GENERIC varyings.
372 * The address space may be larger, but the actual hard limit seems to be
373 * less than what the address space layout permits, so don't add TEXCOORD,
376 if (shader
== PIPE_SHADER_FRAGMENT
)
378 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
379 * and excludes 0x60 per-patch inputs.
382 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
384 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
385 return NVC0_MAX_CONSTBUF_SIZE
;
386 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
387 return NVC0_MAX_PIPE_CONSTBUFS
;
388 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
389 return shader
!= PIPE_SHADER_FRAGMENT
;
390 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
391 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
392 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
394 case PIPE_SHADER_CAP_MAX_TEMPS
:
395 return NVC0_CAP_MAX_PROGRAM_TEMPS
;
396 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
398 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
400 case PIPE_SHADER_CAP_SUBROUTINES
:
402 case PIPE_SHADER_CAP_INTEGERS
:
404 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
406 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
408 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
410 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
411 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
412 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
413 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
414 case PIPE_SHADER_CAP_INT64_ATOMICS
:
415 case PIPE_SHADER_CAP_FP16
:
416 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
417 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
419 case PIPE_SHADER_CAP_SCALAR_ISA
:
421 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
422 return NVC0_MAX_BUFFERS
;
423 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
424 return (class_3d
>= NVE4_3D_CLASS
) ? 32 : 16;
425 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
426 return (class_3d
>= NVE4_3D_CLASS
) ? 32 : 16;
427 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
429 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
430 if (class_3d
>= NVE4_3D_CLASS
)
431 return NVC0_MAX_IMAGES
;
432 if (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
)
433 return NVC0_MAX_IMAGES
;
436 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
442 nvc0_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
444 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
447 case PIPE_CAPF_MAX_LINE_WIDTH
:
448 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
450 case PIPE_CAPF_MAX_POINT_WIDTH
:
452 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
454 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
456 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
458 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
460 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
461 return class_3d
>= GM200_3D_CLASS
? 0.75f
: 0.0f
;
462 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
463 return class_3d
>= GM200_3D_CLASS
? 0.25f
: 0.0f
;
466 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param
);
471 nvc0_screen_get_compute_param(struct pipe_screen
*pscreen
,
472 enum pipe_shader_ir ir_type
,
473 enum pipe_compute_cap param
, void *data
)
475 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
476 const uint16_t obj_class
= screen
->compute
->oclass
;
478 #define RET(x) do { \
480 memcpy(data, x, sizeof(x)); \
485 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
486 RET((uint64_t []) { 3 });
487 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
488 if (obj_class
>= NVE4_COMPUTE_CLASS
) {
489 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
491 RET(((uint64_t []) { 65535, 65535, 65535 }));
493 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
494 RET(((uint64_t []) { 1024, 1024, 64 }));
495 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
496 RET((uint64_t []) { 1024 });
497 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
498 if (obj_class
>= NVE4_COMPUTE_CLASS
) {
499 RET((uint64_t []) { 1024 });
501 RET((uint64_t []) { 512 });
503 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
: /* g[] */
504 RET((uint64_t []) { 1ULL << 40 });
505 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
: /* s[] */
507 case GM200_COMPUTE_CLASS
:
508 RET((uint64_t []) { 96 << 10 });
510 case GM107_COMPUTE_CLASS
:
511 RET((uint64_t []) { 64 << 10 });
514 RET((uint64_t []) { 48 << 10 });
517 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
: /* l[] */
518 RET((uint64_t []) { 512 << 10 });
519 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
: /* c[], arbitrary limit */
520 RET((uint64_t []) { 4096 });
521 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
522 RET((uint32_t []) { 32 });
523 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
524 RET((uint64_t []) { 1ULL << 40 });
525 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
526 RET((uint32_t []) { 0 });
527 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
528 RET((uint32_t []) { screen
->mp_count_compute
});
529 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
530 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
531 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
532 RET((uint32_t []) { 64 });
541 nvc0_screen_get_sample_pixel_grid(struct pipe_screen
*pscreen
,
542 unsigned sample_count
,
543 unsigned *width
, unsigned *height
)
545 switch (sample_count
) {
548 /* this could be 4x4, but the GL state tracker makes it difficult to
549 * create a 1x MSAA texture and smaller grids save CB space */
571 nvc0_screen_destroy(struct pipe_screen
*pscreen
)
573 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
575 if (!nouveau_drm_screen_unref(&screen
->base
))
578 if (screen
->base
.fence
.current
) {
579 struct nouveau_fence
*current
= NULL
;
581 /* nouveau_fence_wait will create a new current fence, so wait on the
582 * _current_ one, and remove both.
584 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
585 nouveau_fence_wait(current
, NULL
);
586 nouveau_fence_ref(NULL
, ¤t
);
587 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
589 if (screen
->base
.pushbuf
)
590 screen
->base
.pushbuf
->user_priv
= NULL
;
593 nvc0_blitter_destroy(screen
);
594 if (screen
->pm
.prog
) {
595 screen
->pm
.prog
->code
= NULL
; /* hardcoded, don't FREE */
596 nvc0_program_destroy(NULL
, screen
->pm
.prog
);
597 FREE(screen
->pm
.prog
);
600 nouveau_bo_ref(NULL
, &screen
->text
);
601 nouveau_bo_ref(NULL
, &screen
->uniform_bo
);
602 nouveau_bo_ref(NULL
, &screen
->tls
);
603 nouveau_bo_ref(NULL
, &screen
->txc
);
604 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
605 nouveau_bo_ref(NULL
, &screen
->poly_cache
);
607 nouveau_heap_destroy(&screen
->lib_code
);
608 nouveau_heap_destroy(&screen
->text_heap
);
610 FREE(screen
->default_tsc
);
611 FREE(screen
->tic
.entries
);
613 nouveau_object_del(&screen
->eng3d
);
614 nouveau_object_del(&screen
->eng2d
);
615 nouveau_object_del(&screen
->m2mf
);
616 nouveau_object_del(&screen
->compute
);
617 nouveau_object_del(&screen
->nvsw
);
619 nouveau_screen_fini(&screen
->base
);
625 nvc0_graph_set_macro(struct nvc0_screen
*screen
, uint32_t m
, unsigned pos
,
626 unsigned size
, const uint32_t *data
)
628 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
632 assert((pos
+ size
) <= 0x800);
634 BEGIN_NVC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_ID
), 2);
635 PUSH_DATA (push
, (m
- 0x3800) / 8);
636 PUSH_DATA (push
, pos
);
637 BEGIN_1IC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS
), size
+ 1);
638 PUSH_DATA (push
, pos
);
639 PUSH_DATAp(push
, data
, size
);
645 nvc0_magic_3d_init(struct nouveau_pushbuf
*push
, uint16_t obj_class
)
647 BEGIN_NVC0(push
, SUBC_3D(0x10cc), 1);
648 PUSH_DATA (push
, 0xff);
649 BEGIN_NVC0(push
, SUBC_3D(0x10e0), 2);
650 PUSH_DATA (push
, 0xff);
651 PUSH_DATA (push
, 0xff);
652 BEGIN_NVC0(push
, SUBC_3D(0x10ec), 2);
653 PUSH_DATA (push
, 0xff);
654 PUSH_DATA (push
, 0xff);
655 BEGIN_NVC0(push
, SUBC_3D(0x074c), 1);
656 PUSH_DATA (push
, 0x3f);
658 BEGIN_NVC0(push
, SUBC_3D(0x16a8), 1);
659 PUSH_DATA (push
, (3 << 16) | 3);
660 BEGIN_NVC0(push
, SUBC_3D(0x1794), 1);
661 PUSH_DATA (push
, (2 << 16) | 2);
663 if (obj_class
< GM107_3D_CLASS
) {
664 BEGIN_NVC0(push
, SUBC_3D(0x12ac), 1);
667 BEGIN_NVC0(push
, SUBC_3D(0x0218), 1);
668 PUSH_DATA (push
, 0x10);
669 BEGIN_NVC0(push
, SUBC_3D(0x10fc), 1);
670 PUSH_DATA (push
, 0x10);
671 BEGIN_NVC0(push
, SUBC_3D(0x1290), 1);
672 PUSH_DATA (push
, 0x10);
673 BEGIN_NVC0(push
, SUBC_3D(0x12d8), 2);
674 PUSH_DATA (push
, 0x10);
675 PUSH_DATA (push
, 0x10);
676 BEGIN_NVC0(push
, SUBC_3D(0x1140), 1);
677 PUSH_DATA (push
, 0x10);
678 BEGIN_NVC0(push
, SUBC_3D(0x1610), 1);
679 PUSH_DATA (push
, 0xe);
681 BEGIN_NVC0(push
, NVC0_3D(VERTEX_ID_GEN_MODE
), 1);
682 PUSH_DATA (push
, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START
);
683 BEGIN_NVC0(push
, SUBC_3D(0x030c), 1);
685 BEGIN_NVC0(push
, SUBC_3D(0x0300), 1);
688 BEGIN_NVC0(push
, SUBC_3D(0x02d0), 1);
689 PUSH_DATA (push
, 0x3fffff);
690 BEGIN_NVC0(push
, SUBC_3D(0x0fdc), 1);
692 BEGIN_NVC0(push
, SUBC_3D(0x19c0), 1);
695 if (obj_class
< GM107_3D_CLASS
) {
696 BEGIN_NVC0(push
, SUBC_3D(0x075c), 1);
699 if (obj_class
>= NVE4_3D_CLASS
) {
700 BEGIN_NVC0(push
, SUBC_3D(0x07fc), 1);
705 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
706 * are supposed to do */
710 nvc0_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
712 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
713 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
715 /* we need to do it after possible flush in MARK_RING */
716 *sequence
= ++screen
->base
.fence
.sequence
;
718 assert(PUSH_AVAIL(push
) + push
->rsvd_kick
>= 5);
719 PUSH_DATA (push
, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH
), 4));
720 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
721 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
722 PUSH_DATA (push
, *sequence
);
723 PUSH_DATA (push
, NVC0_3D_QUERY_GET_FENCE
| NVC0_3D_QUERY_GET_SHORT
|
724 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT
));
728 nvc0_screen_fence_update(struct pipe_screen
*pscreen
)
730 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
731 return screen
->fence
.map
[0];
735 nvc0_screen_init_compute(struct nvc0_screen
*screen
)
737 screen
->base
.base
.get_compute_param
= nvc0_screen_get_compute_param
;
739 switch (screen
->base
.device
->chipset
& ~0xf) {
742 return nvc0_screen_compute_setup(screen
, screen
->base
.pushbuf
);
749 return nve4_screen_compute_setup(screen
, screen
->base
.pushbuf
);
756 nvc0_screen_resize_tls_area(struct nvc0_screen
*screen
,
757 uint32_t lpos
, uint32_t lneg
, uint32_t cstack
)
759 struct nouveau_bo
*bo
= NULL
;
761 uint64_t size
= (lpos
+ lneg
) * 32 + cstack
;
763 if (size
>= (1 << 20)) {
764 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64
"\n", size
);
768 size
*= (screen
->base
.device
->chipset
>= 0xe0) ? 64 : 48; /* max warps */
769 size
= align(size
, 0x8000);
770 size
*= screen
->mp_count
;
772 size
= align(size
, 1 << 17);
774 ret
= nouveau_bo_new(screen
->base
.device
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 17, size
,
779 /* Make sure that the pushbuf has acquired a reference to the old tls
780 * segment, as it may have commands that will reference it.
783 PUSH_REFN(screen
->base
.pushbuf
, screen
->tls
,
784 NV_VRAM_DOMAIN(&screen
->base
) | NOUVEAU_BO_RDWR
);
785 nouveau_bo_ref(NULL
, &screen
->tls
);
791 nvc0_screen_resize_text_area(struct nvc0_screen
*screen
, uint64_t size
)
793 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
794 struct nouveau_bo
*bo
;
797 ret
= nouveau_bo_new(screen
->base
.device
, NV_VRAM_DOMAIN(&screen
->base
),
798 1 << 17, size
, NULL
, &bo
);
802 /* Make sure that the pushbuf has acquired a reference to the old text
803 * segment, as it may have commands that will reference it.
806 PUSH_REFN(push
, screen
->text
,
807 NV_VRAM_DOMAIN(&screen
->base
) | NOUVEAU_BO_RD
);
808 nouveau_bo_ref(NULL
, &screen
->text
);
811 nouveau_heap_destroy(&screen
->lib_code
);
812 nouveau_heap_destroy(&screen
->text_heap
);
814 /* XXX: getting a page fault at the end of the code buffer every few
815 * launches, don't use the last 256 bytes to work around them - prefetch ?
817 nouveau_heap_init(&screen
->text_heap
, 0, size
- 0x100);
819 /* update the code segment setup */
820 BEGIN_NVC0(push
, NVC0_3D(CODE_ADDRESS_HIGH
), 2);
821 PUSH_DATAh(push
, screen
->text
->offset
);
822 PUSH_DATA (push
, screen
->text
->offset
);
823 if (screen
->compute
) {
824 BEGIN_NVC0(push
, NVC0_CP(CODE_ADDRESS_HIGH
), 2);
825 PUSH_DATAh(push
, screen
->text
->offset
);
826 PUSH_DATA (push
, screen
->text
->offset
);
833 nvc0_screen_bind_cb_3d(struct nvc0_screen
*screen
, bool *can_serialize
,
834 int stage
, int index
, int size
, uint64_t addr
)
838 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
840 if (screen
->base
.class_3d
>= GM107_3D_CLASS
) {
841 struct nvc0_cb_binding
*binding
= &screen
->cb_bindings
[stage
][index
];
843 // TODO: Better figure out the conditions in which this is needed
844 bool serialize
= binding
->addr
== addr
&& binding
->size
!= size
;
846 serialize
= serialize
&& *can_serialize
;
848 IMMED_NVC0(push
, NVC0_3D(SERIALIZE
), 0);
850 *can_serialize
= false;
853 binding
->addr
= addr
;
854 binding
->size
= size
;
858 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
859 PUSH_DATA (push
, size
);
860 PUSH_DATAh(push
, addr
);
861 PUSH_DATA (push
, addr
);
863 IMMED_NVC0(push
, NVC0_3D(CB_BIND(stage
)), (index
<< 4) | (size
>= 0));
866 #define FAIL_SCREEN_INIT(str, err) \
868 NOUVEAU_ERR(str, err); \
872 struct nouveau_screen
*
873 nvc0_screen_create(struct nouveau_device
*dev
)
875 struct nvc0_screen
*screen
;
876 struct pipe_screen
*pscreen
;
877 struct nouveau_object
*chan
;
878 struct nouveau_pushbuf
*push
;
885 switch (dev
->chipset
& ~0xf) {
899 screen
= CALLOC_STRUCT(nvc0_screen
);
902 pscreen
= &screen
->base
.base
;
903 pscreen
->destroy
= nvc0_screen_destroy
;
905 ret
= nouveau_screen_init(&screen
->base
, dev
);
907 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret
);
908 chan
= screen
->base
.channel
;
909 push
= screen
->base
.pushbuf
;
910 push
->user_priv
= screen
;
913 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
914 PIPE_BIND_SHADER_BUFFER
|
915 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
|
916 PIPE_BIND_COMMAND_ARGS_BUFFER
| PIPE_BIND_QUERY_BUFFER
;
917 screen
->base
.sysmem_bindings
|=
918 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
920 if (screen
->base
.vram_domain
& NOUVEAU_BO_GART
) {
921 screen
->base
.sysmem_bindings
|= screen
->base
.vidmem_bindings
;
922 screen
->base
.vidmem_bindings
= 0;
925 pscreen
->context_create
= nvc0_create
;
926 pscreen
->is_format_supported
= nvc0_screen_is_format_supported
;
927 pscreen
->get_param
= nvc0_screen_get_param
;
928 pscreen
->get_shader_param
= nvc0_screen_get_shader_param
;
929 pscreen
->get_paramf
= nvc0_screen_get_paramf
;
930 pscreen
->get_sample_pixel_grid
= nvc0_screen_get_sample_pixel_grid
;
931 pscreen
->get_driver_query_info
= nvc0_screen_get_driver_query_info
;
932 pscreen
->get_driver_query_group_info
= nvc0_screen_get_driver_query_group_info
;
934 nvc0_screen_init_resource_functions(pscreen
);
936 screen
->base
.base
.get_video_param
= nouveau_vp3_screen_get_video_param
;
937 screen
->base
.base
.is_video_format_supported
= nouveau_vp3_screen_video_supported
;
939 flags
= NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
;
940 if (screen
->base
.drm
->version
>= 0x01000202)
941 flags
|= NOUVEAU_BO_COHERENT
;
943 ret
= nouveau_bo_new(dev
, flags
, 0, 4096, NULL
, &screen
->fence
.bo
);
945 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret
);
946 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
947 screen
->fence
.map
= screen
->fence
.bo
->map
;
948 screen
->base
.fence
.emit
= nvc0_screen_fence_emit
;
949 screen
->base
.fence
.update
= nvc0_screen_fence_update
;
952 ret
= nouveau_object_new(chan
, (dev
->chipset
< 0xe0) ? 0x1f906e : 0x906e,
953 NVIF_CLASS_SW_GF100
, NULL
, 0, &screen
->nvsw
);
955 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret
);
957 BEGIN_NVC0(push
, SUBC_SW(NV01_SUBCHAN_OBJECT
), 1);
958 PUSH_DATA (push
, screen
->nvsw
->handle
);
960 switch (dev
->chipset
& ~0xf) {
966 obj_class
= NVF0_P2MF_CLASS
;
969 obj_class
= NVE4_P2MF_CLASS
;
972 obj_class
= NVC0_M2MF_CLASS
;
975 ret
= nouveau_object_new(chan
, 0xbeef323f, obj_class
, NULL
, 0,
978 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret
);
980 BEGIN_NVC0(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
981 PUSH_DATA (push
, screen
->m2mf
->oclass
);
982 if (screen
->m2mf
->oclass
== NVE4_P2MF_CLASS
) {
983 BEGIN_NVC0(push
, SUBC_COPY(NV01_SUBCHAN_OBJECT
), 1);
984 PUSH_DATA (push
, 0xa0b5);
987 ret
= nouveau_object_new(chan
, 0xbeef902d, NVC0_2D_CLASS
, NULL
, 0,
990 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret
);
992 BEGIN_NVC0(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
993 PUSH_DATA (push
, screen
->eng2d
->oclass
);
994 BEGIN_NVC0(push
, SUBC_2D(NVC0_2D_SINGLE_GPC
), 1);
996 BEGIN_NVC0(push
, NVC0_2D(OPERATION
), 1);
997 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY
);
998 BEGIN_NVC0(push
, NVC0_2D(CLIP_ENABLE
), 1);
1000 BEGIN_NVC0(push
, NVC0_2D(COLOR_KEY_ENABLE
), 1);
1001 PUSH_DATA (push
, 0);
1002 BEGIN_NVC0(push
, SUBC_2D(0x0884), 1);
1003 PUSH_DATA (push
, 0x3f);
1004 BEGIN_NVC0(push
, SUBC_2D(0x0888), 1);
1005 PUSH_DATA (push
, 1);
1006 BEGIN_NVC0(push
, NVC0_2D(COND_MODE
), 1);
1007 PUSH_DATA (push
, NV50_2D_COND_MODE_ALWAYS
);
1009 BEGIN_NVC0(push
, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH
), 2);
1010 PUSH_DATAh(push
, screen
->fence
.bo
->offset
+ 16);
1011 PUSH_DATA (push
, screen
->fence
.bo
->offset
+ 16);
1013 switch (dev
->chipset
& ~0xf) {
1015 switch (dev
->chipset
) {
1018 obj_class
= GP100_3D_CLASS
;
1021 obj_class
= GP102_3D_CLASS
;
1026 obj_class
= GM200_3D_CLASS
;
1029 obj_class
= GM107_3D_CLASS
;
1033 obj_class
= NVF0_3D_CLASS
;
1036 switch (dev
->chipset
) {
1038 obj_class
= NVEA_3D_CLASS
;
1041 obj_class
= NVE4_3D_CLASS
;
1046 obj_class
= NVC8_3D_CLASS
;
1050 switch (dev
->chipset
) {
1052 obj_class
= NVC8_3D_CLASS
;
1055 obj_class
= NVC1_3D_CLASS
;
1058 obj_class
= NVC0_3D_CLASS
;
1063 ret
= nouveau_object_new(chan
, 0xbeef003d, obj_class
, NULL
, 0,
1066 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret
);
1067 screen
->base
.class_3d
= obj_class
;
1069 BEGIN_NVC0(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
1070 PUSH_DATA (push
, screen
->eng3d
->oclass
);
1072 BEGIN_NVC0(push
, NVC0_3D(COND_MODE
), 1);
1073 PUSH_DATA (push
, NVC0_3D_COND_MODE_ALWAYS
);
1075 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1076 /* kill shaders after about 1 second (at 100 MHz) */
1077 BEGIN_NVC0(push
, NVC0_3D(WATCHDOG_TIMER
), 1);
1078 PUSH_DATA (push
, 0x17);
1081 IMMED_NVC0(push
, NVC0_3D(ZETA_COMP_ENABLE
),
1082 screen
->base
.drm
->version
>= 0x01000101);
1083 BEGIN_NVC0(push
, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1084 for (i
= 0; i
< 8; ++i
)
1085 PUSH_DATA(push
, screen
->base
.drm
->version
>= 0x01000101);
1087 BEGIN_NVC0(push
, NVC0_3D(RT_CONTROL
), 1);
1088 PUSH_DATA (push
, 1);
1090 BEGIN_NVC0(push
, NVC0_3D(CSAA_ENABLE
), 1);
1091 PUSH_DATA (push
, 0);
1092 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_ENABLE
), 1);
1093 PUSH_DATA (push
, 0);
1094 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_MODE
), 1);
1095 PUSH_DATA (push
, NVC0_3D_MULTISAMPLE_MODE_MS1
);
1096 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_CTRL
), 1);
1097 PUSH_DATA (push
, 0);
1098 BEGIN_NVC0(push
, NVC0_3D(LINE_WIDTH_SEPARATE
), 1);
1099 PUSH_DATA (push
, 1);
1100 BEGIN_NVC0(push
, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS
), 1);
1101 PUSH_DATA (push
, 1);
1102 BEGIN_NVC0(push
, NVC0_3D(BLEND_SEPARATE_ALPHA
), 1);
1103 PUSH_DATA (push
, 1);
1104 BEGIN_NVC0(push
, NVC0_3D(BLEND_ENABLE_COMMON
), 1);
1105 PUSH_DATA (push
, 0);
1106 BEGIN_NVC0(push
, NVC0_3D(SHADE_MODEL
), 1);
1107 PUSH_DATA (push
, NVC0_3D_SHADE_MODEL_SMOOTH
);
1108 if (screen
->eng3d
->oclass
< NVE4_3D_CLASS
) {
1109 IMMED_NVC0(push
, NVC0_3D(TEX_MISC
), 0);
1111 BEGIN_NVC0(push
, NVE4_3D(TEX_CB_INDEX
), 1);
1112 PUSH_DATA (push
, 15);
1114 BEGIN_NVC0(push
, NVC0_3D(CALL_LIMIT_LOG
), 1);
1115 PUSH_DATA (push
, 8); /* 128 */
1116 BEGIN_NVC0(push
, NVC0_3D(ZCULL_STATCTRS_ENABLE
), 1);
1117 PUSH_DATA (push
, 1);
1118 if (screen
->eng3d
->oclass
>= NVC1_3D_CLASS
) {
1119 BEGIN_NVC0(push
, NVC0_3D(CACHE_SPLIT
), 1);
1120 PUSH_DATA (push
, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1
);
1123 nvc0_magic_3d_init(push
, screen
->eng3d
->oclass
);
1125 ret
= nvc0_screen_resize_text_area(screen
, 1 << 19);
1127 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret
);
1129 /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1130 ret
= nouveau_bo_new(dev
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 12, 13 << 16, NULL
,
1131 &screen
->uniform_bo
);
1133 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret
);
1135 PUSH_REFN (push
, screen
->uniform_bo
, NV_VRAM_DOMAIN(&screen
->base
) | NOUVEAU_BO_WR
);
1137 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1138 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
1139 PUSH_DATA (push
, 256);
1140 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_RUNOUT_INFO
);
1141 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_RUNOUT_INFO
);
1142 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 5);
1143 PUSH_DATA (push
, 0);
1144 PUSH_DATAf(push
, 0.0f
);
1145 PUSH_DATAf(push
, 0.0f
);
1146 PUSH_DATAf(push
, 0.0f
);
1147 PUSH_DATAf(push
, 0.0f
);
1148 BEGIN_NVC0(push
, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH
), 2);
1149 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_RUNOUT_INFO
);
1150 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ NVC0_CB_AUX_RUNOUT_INFO
);
1152 if (screen
->base
.drm
->version
>= 0x01000101) {
1153 ret
= nouveau_getparam(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
1155 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret
);
1157 if (dev
->chipset
>= 0xe0 && dev
->chipset
< 0xf0)
1158 value
= (8 << 8) | 4;
1160 value
= (16 << 8) | 4;
1162 screen
->gpc_count
= value
& 0x000000ff;
1163 screen
->mp_count
= value
>> 8;
1164 screen
->mp_count_compute
= screen
->mp_count
;
1166 ret
= nvc0_screen_resize_tls_area(screen
, 128 * 16, 0, 0x200);
1168 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret
);
1170 BEGIN_NVC0(push
, NVC0_3D(TEMP_ADDRESS_HIGH
), 4);
1171 PUSH_DATAh(push
, screen
->tls
->offset
);
1172 PUSH_DATA (push
, screen
->tls
->offset
);
1173 PUSH_DATA (push
, screen
->tls
->size
>> 32);
1174 PUSH_DATA (push
, screen
->tls
->size
);
1175 BEGIN_NVC0(push
, NVC0_3D(WARP_TEMP_ALLOC
), 1);
1176 PUSH_DATA (push
, 0);
1177 /* Reduce likelihood of collision with real buffers by placing the hole at
1178 * the top of the 4G area. This will have to be dealt with for real
1179 * eventually by blocking off that area from the VM.
1181 BEGIN_NVC0(push
, NVC0_3D(LOCAL_BASE
), 1);
1182 PUSH_DATA (push
, 0xff << 24);
1184 if (screen
->eng3d
->oclass
< GM107_3D_CLASS
) {
1185 ret
= nouveau_bo_new(dev
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 17, 1 << 20, NULL
,
1186 &screen
->poly_cache
);
1188 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret
);
1190 BEGIN_NVC0(push
, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH
), 3);
1191 PUSH_DATAh(push
, screen
->poly_cache
->offset
);
1192 PUSH_DATA (push
, screen
->poly_cache
->offset
);
1193 PUSH_DATA (push
, 3);
1196 ret
= nouveau_bo_new(dev
, NV_VRAM_DOMAIN(&screen
->base
), 1 << 17, 1 << 17, NULL
,
1199 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret
);
1201 BEGIN_NVC0(push
, NVC0_3D(TIC_ADDRESS_HIGH
), 3);
1202 PUSH_DATAh(push
, screen
->txc
->offset
);
1203 PUSH_DATA (push
, screen
->txc
->offset
);
1204 PUSH_DATA (push
, NVC0_TIC_MAX_ENTRIES
- 1);
1205 if (screen
->eng3d
->oclass
>= GM107_3D_CLASS
) {
1206 screen
->tic
.maxwell
= true;
1207 if (screen
->eng3d
->oclass
== GM107_3D_CLASS
) {
1208 screen
->tic
.maxwell
=
1209 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1210 IMMED_NVC0(push
, SUBC_3D(0x0f10), screen
->tic
.maxwell
);
1214 BEGIN_NVC0(push
, NVC0_3D(TSC_ADDRESS_HIGH
), 3);
1215 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
1216 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
1217 PUSH_DATA (push
, NVC0_TSC_MAX_ENTRIES
- 1);
1219 BEGIN_NVC0(push
, NVC0_3D(SCREEN_Y_CONTROL
), 1);
1220 PUSH_DATA (push
, 0);
1221 BEGIN_NVC0(push
, NVC0_3D(WINDOW_OFFSET_X
), 2);
1222 PUSH_DATA (push
, 0);
1223 PUSH_DATA (push
, 0);
1224 BEGIN_NVC0(push
, NVC0_3D(ZCULL_REGION
), 1); /* deactivate ZCULL */
1225 PUSH_DATA (push
, 0x3f);
1227 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_MODE
), 1);
1228 PUSH_DATA (push
, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
1229 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1230 for (i
= 0; i
< 8 * 2; ++i
)
1232 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_EN
), 1);
1233 PUSH_DATA (push
, 0);
1234 BEGIN_NVC0(push
, NVC0_3D(CLIPID_ENABLE
), 1);
1235 PUSH_DATA (push
, 0);
1237 /* neither scissors, viewport nor stencil mask should affect clears */
1238 BEGIN_NVC0(push
, NVC0_3D(CLEAR_FLAGS
), 1);
1239 PUSH_DATA (push
, 0);
1241 BEGIN_NVC0(push
, NVC0_3D(VIEWPORT_TRANSFORM_EN
), 1);
1242 PUSH_DATA (push
, 1);
1243 for (i
= 0; i
< NVC0_MAX_VIEWPORTS
; i
++) {
1244 BEGIN_NVC0(push
, NVC0_3D(DEPTH_RANGE_NEAR(i
)), 2);
1245 PUSH_DATAf(push
, 0.0f
);
1246 PUSH_DATAf(push
, 1.0f
);
1248 BEGIN_NVC0(push
, NVC0_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
1249 PUSH_DATA (push
, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
);
1251 /* We use scissors instead of exact view volume clipping,
1252 * so they're always enabled.
1254 for (i
= 0; i
< NVC0_MAX_VIEWPORTS
; i
++) {
1255 BEGIN_NVC0(push
, NVC0_3D(SCISSOR_ENABLE(i
)), 3);
1256 PUSH_DATA (push
, 1);
1257 PUSH_DATA (push
, 8192 << 16);
1258 PUSH_DATA (push
, 8192 << 16);
1261 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1264 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE
, mme9097_per_instance_bf
);
1265 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES
, mme9097_blend_enables
);
1266 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT
, mme9097_vertex_array_select
);
1267 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT
, mme9097_tep_select
);
1268 MK_MACRO(NVC0_3D_MACRO_GP_SELECT
, mme9097_gp_select
);
1269 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT
, mme9097_poly_mode_front
);
1270 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK
, mme9097_poly_mode_back
);
1271 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT
, mme9097_draw_arrays_indirect
);
1272 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT
, mme9097_draw_elts_indirect
);
1273 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT
, mme9097_draw_arrays_indirect_count
);
1274 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT
, mme9097_draw_elts_indirect_count
);
1275 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE
, mme9097_query_buffer_write
);
1276 MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE
, mme9097_conservative_raster_state
);
1277 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT
, mme90c0_launch_grid_indirect
);
1279 BEGIN_NVC0(push
, NVC0_3D(RASTERIZE_ENABLE
), 1);
1280 PUSH_DATA (push
, 1);
1281 BEGIN_NVC0(push
, NVC0_3D(RT_SEPARATE_FRAG_DATA
), 1);
1282 PUSH_DATA (push
, 1);
1283 BEGIN_NVC0(push
, NVC0_3D(MACRO_GP_SELECT
), 1);
1284 PUSH_DATA (push
, 0x40);
1285 BEGIN_NVC0(push
, NVC0_3D(LAYER
), 1);
1286 PUSH_DATA (push
, 0);
1287 BEGIN_NVC0(push
, NVC0_3D(MACRO_TEP_SELECT
), 1);
1288 PUSH_DATA (push
, 0x30);
1289 BEGIN_NVC0(push
, NVC0_3D(PATCH_VERTICES
), 1);
1290 PUSH_DATA (push
, 3);
1291 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(2)), 1);
1292 PUSH_DATA (push
, 0x20);
1293 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(0)), 1);
1294 PUSH_DATA (push
, 0x00);
1295 screen
->save_state
.patch_vertices
= 3;
1297 BEGIN_NVC0(push
, NVC0_3D(POINT_COORD_REPLACE
), 1);
1298 PUSH_DATA (push
, 0);
1299 BEGIN_NVC0(push
, NVC0_3D(POINT_RASTER_RULES
), 1);
1300 PUSH_DATA (push
, NVC0_3D_POINT_RASTER_RULES_OGL
);
1302 IMMED_NVC0(push
, NVC0_3D(EDGEFLAG
), 1);
1304 if (nvc0_screen_init_compute(screen
))
1307 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1308 for (i
= 0; i
< 5; ++i
) {
1310 for (j
= 0; j
< 16; j
++)
1311 screen
->cb_bindings
[i
][j
].size
= -1;
1313 /* TIC and TSC entries for each unit (nve4+ only) */
1314 /* auxiliary constants (6 user clip planes, base instance id) */
1315 nvc0_screen_bind_cb_3d(screen
, NULL
, i
, 15, NVC0_CB_AUX_SIZE
,
1316 screen
->uniform_bo
->offset
+ NVC0_CB_AUX_INFO(i
));
1317 if (screen
->eng3d
->oclass
>= NVE4_3D_CLASS
) {
1319 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 9);
1320 PUSH_DATA (push
, NVC0_CB_AUX_UNK_INFO
);
1321 for (j
= 0; j
< 8; ++j
)
1324 BEGIN_NVC0(push
, NVC0_3D(TEX_LIMITS(i
)), 1);
1325 PUSH_DATA (push
, 0x54);
1328 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1329 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 1 + 2 * 8);
1330 PUSH_DATA (push
, NVC0_CB_AUX_MS_INFO
);
1331 PUSH_DATA (push
, 0); /* 0 */
1332 PUSH_DATA (push
, 0);
1333 PUSH_DATA (push
, 1); /* 1 */
1334 PUSH_DATA (push
, 0);
1335 PUSH_DATA (push
, 0); /* 2 */
1336 PUSH_DATA (push
, 1);
1337 PUSH_DATA (push
, 1); /* 3 */
1338 PUSH_DATA (push
, 1);
1339 PUSH_DATA (push
, 2); /* 4 */
1340 PUSH_DATA (push
, 0);
1341 PUSH_DATA (push
, 3); /* 5 */
1342 PUSH_DATA (push
, 0);
1343 PUSH_DATA (push
, 2); /* 6 */
1344 PUSH_DATA (push
, 1);
1345 PUSH_DATA (push
, 3); /* 7 */
1346 PUSH_DATA (push
, 1);
1348 BEGIN_NVC0(push
, NVC0_3D(LINKED_TSC
), 1);
1349 PUSH_DATA (push
, 0);
1353 screen
->tic
.entries
= CALLOC(
1354 NVC0_TIC_MAX_ENTRIES
+ NVC0_TSC_MAX_ENTRIES
+ NVE4_IMG_MAX_HANDLES
,
1356 screen
->tsc
.entries
= screen
->tic
.entries
+ NVC0_TIC_MAX_ENTRIES
;
1357 screen
->img
.entries
= (void *)(screen
->tsc
.entries
+ NVC0_TSC_MAX_ENTRIES
);
1359 if (!nvc0_blitter_create(screen
))
1362 screen
->default_tsc
= CALLOC_STRUCT(nv50_tsc_entry
);
1363 screen
->default_tsc
->tsc
[0] = G80_TSC_0_SRGB_CONVERSION
;
1365 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
);
1367 return &screen
->base
;
1370 screen
->base
.base
.context_create
= NULL
;
1371 return &screen
->base
;
1375 nvc0_screen_tic_alloc(struct nvc0_screen
*screen
, void *entry
)
1377 int i
= screen
->tic
.next
;
1379 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
1380 i
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
1382 screen
->tic
.next
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
1384 if (screen
->tic
.entries
[i
])
1385 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
1387 screen
->tic
.entries
[i
] = entry
;
1392 nvc0_screen_tsc_alloc(struct nvc0_screen
*screen
, void *entry
)
1394 int i
= screen
->tsc
.next
;
1396 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
1397 i
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
1399 screen
->tsc
.next
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
1401 if (screen
->tsc
.entries
[i
])
1402 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
1404 screen
->tsc
.entries
[i
] = entry
;